Circuit Techniques Research Articles

Comparative Analysis Domino Logic Based Techniques For VLSI Circuit

Domino logic is a CMOS-based evolution of the dynamic logic techniques  based on either PMOS or NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.

Integrated Inverter/Converter Circuit and Control Technique of Motor Drives With Dual-Mode Control for EV/HEV Applications

A new integrated circuit for motor drives with dual-mode control for EV/HEV applications is proposed. The proposed integrated circuit allows the permanent magnet synchronous motor to operate in motor mode or acts as boost inductors of the boost converter, and thereby boosting the output torque coupled to the same transmission system or dc-link voltage of the inverter connected to the output of the integrated circuit. In motor mode, the proposed integrated circuit acts as an inverter and it becomes a boost-type boost converter, while using the motor windings as the boost inductors to boost the converter output voltage. Moreover, a new control technique for the proposed integrated circuit under boost converter mode is proposed to increase the efficiency. The proposed control technique is to use interleaved control to significantly reduce the current ripple and thereby reducing the losses and thermal stress under heavy-load condition. In contrast, single-phase control is used for not invoking additional switching and conduction losses under light-load condition. Experimental results derived from digital-controlled 3-kW inverter/converter using digital signal processing show the voltage boost ratio can go up to 600 W to 3 kW. And the efficiency is 93.83% under full-load condition while keeping the motor temperature at the atmosphere level. These results fully confirm the claimed merits for the proposed integrated circuit.

A Self-Steering Receiver Array Using Jointly Coupled Oscillators and Phased-Locked Loops

This paper presents an analog circuit scheme to steer phased-array receivers in the direction of an incoming signal. The proposed circuit technique utilizes a coupled-oscillator array along with a coupled-phased-locked loop to auto-align an N-element receive array towards the direction of the incident RF signal. A four-element receiver array is implemented in 45-nm CMOS SOI process and achieves auto-steering range of ±35° from broadside. A three-element version of the array demonstrates higher auto-steering angle covering ±70° range. The receiver also performs signal demodulation for the incident modulated RF signal, allowing high-data rate communication. A 60-Mbps 64-QAM modulated RF signal is demodulated with error-vector-magnitude (EVM) less than 4% across the steering angle range. The chip area is 3.45 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including a pad frame with 30-mW/element power consumption. To the best of authors' knowledge, this is the first demonstration of an analog self-steering array in an integrated circuit.

Verification of Asynchronous FIFO using System Verilog

Mohit Arora, The Art of Hardware Architecture: Design Methods and Techniques for Digital Circuits, Springer, 2011, ch 3, sec 3. 3, pp 54-55 Clifford E. Cummings, Simulation and Techniques for Asynchronous FIFO Design, SNUG 2000 Users Group Conference, San Jose, CA, 2002) User Papers, March 2002. Clifford E. Cummings, Synthesis and Scripting Techniques for Designing

An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at &lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;${\rm VDD}=$&lt;/tex&gt;&lt;/formula&gt; 0 V Achieving Zero Leakage With &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${&amp;lt;}$&lt;/tex&gt; &lt;/formula&gt;400-ns Wakeup Time for ULP Applications

This paper presents a nonvolatile logic (NVL)-based 32-b microcontroller system-on-chip (SoC) that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400 ns to restore the system state upon power-up. Nonvolatile Fe-Cap-based mini-arrays backup the machine state and allow the chip to wake up instantly after a power cycle. Without NVL, a chip would either have to keep all flip-flops powered, resulting in high standby power, or waste energy and time rebooting after power-up. NVL allows systems to use leakier processes to achieve higher performance/lower dynamic power while still having zero leakage in the sleep mode. Optimized system, architecture, and circuit techniques are presented that make NVL practical by adding only 3.6% to the SoC area. Since nonvolatile elements are added to the SoC, reliability and testability have to be key features of the design. This is the first NVL SoC with measured NVL bitcell read signal margin data and extensive test and debug capabilities. The chip is fabricated in a commercial 130-nm low-leakage process and uses a single 1.5-V power supply.

Optimization of Transmission Conditions in Waveform Relaxation Techniques for RC Circuits

Waveform relaxation techniques have become increasingly important with the wide availability of parallel computers with a large number of processors. A limiting factor for classical waveform relaxation, however, is the convergence speed for an important class of problems, especially if long time windows are considered. In contrast, the optimized waveform relaxation algorithm discussed in this paper is well suited to address this problem. Today several numerical analyses have shown that optimized waveform relaxation algorithms can overcome slow convergence over long time windows. However, the optimized waveform relaxation techniques require the determination of optimized parameters. In this paper, we present a theoretical foundation for the determination of the optimized parameters for an important class of RC circuits.

Performance of Buck-Boost Converter with Mode Select Circuit and Feed Forward Technique

DC-DC converter topologies, the controllable switches are operated in switch mode where they are required to turn the entire load current on and off during each switching cycle. This work proposes a high- efficiency positive buck- boost converter with mode-select circuits and feed-forward techniques. Four power transistors produce more conduction and more switching losses when the positive and negative buck-boost converter operates in buck-boost mode. Utilizing the mode-select circuit, the proposed converter can decrease the loss of switches and let the positive buck-boost converter operate in buck, buck-boost, or boost mode. By adding feed-forward techniques, similarly for the proposed converter can improve transient response when the supply voltages are changed. The positive and negative feed forward technique of the buck boost converter is to be compared. The analysis and design method of the proposed work is carried out using MATLAB/ Simulink. PI controller is controlled using ABC algorithm. Index Terms: DC-DC converter, Positive output Buck-Boost converter, Proportional-Integral (PI) control.

Ultra-low-power circuit techniques for mm-size wireless sensor nodes with energy harvesting

Ultra-low-power circuit techniques for mm-size wireless sensor nodes with energy harvesting

Preface to the Special Issue on “Electronic Circuit Techniques for Smart Community”

Preface to the Special Issue on “Electronic Circuit Techniques for Smart Community”

40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170 $^{\circ}$C

First-ever 40-nm embedded split-gate MONOS (SG-MONOS) flash macros for automotive micro-controller unit (MCU) have been successfully developed. A SG-MONOS cell realizes high performance with low power consumption and intrinsically high data reliability thanks to the combination of split-gate and charge-trapping structure. In addition, newly developed circuit techniques greatly enhance the advantages of SG-MONOS cells and enable fast and reliable operations even at the junction temperature (Tj) of 170°C with small peripheral circuit area; 1) a sense amplifier with digital offset cancellation (SA-DOC) provides fast read operation over 160 MHz; 2) adaptable program current control scheme (APCCS) and intelligent erase scheme (IES) significantly decrease the program and erase time, which also results in improving the memory cells' reliability; and, 3) 3-D stacked unit capacitors achieve area-efficient charge pump. Two types of embedded flash (eFlash) macros with these technologies, code macro of 2 MB and data macro of 64 KB, were fabricated in a 40-nm eFlash process. The code macro demonstrates the capability of 160-MHz random read operation at Tj= 170°C, reaching 5.1 GB/s read throughput by simultaneous 256 bits read-out from two code macros. The data macro achieves the program/erase endurance over 10 million cycles at Tj= 170°C without any software-assisted techniques.

Circuit Techniques for Reducing the Effect of Analog Signal Conditioning Imperfections in EEG Measuring

Abstract New ideas are necessary to improve the quality of electroencephalogram (EEG) type bio-signal recordings, as a module of a brain computer interface (BCI). The EEG signals are a result of noninvasive recording technology. The recorded signals are usually of low amplitude (in μV domain) and noisy signals. To be able to extract technically usable information from these signals, it is necessary to amplify and filter them. To amplify and filter bio-signals, special and quality electronic concepts must be used. In this paper we are able to present the structure of an amplifier based on an original concept as a result of our NSRG research. The concept is implemented and tested. This amplifier should have a successful contribution to reduce the effect of imperfect conditioning of the analog channel of bio-signal recording.

Novel Circuit Technique for Low Power CMOS design

Novel Circuit Technique for Low Power CMOS design

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

This paper presents circuit techniques to reduce both active and standby mode power, especially at room temperature (RT). A bit-line power calculator is used to adaptively set the cell supply voltage (VCS) in the active mode. A digitally controllable retention circuit regulates VCS in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28-nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25 °C is reduced by 27% and 85%, respectively.

A low-leakage and NBTI-mitigated N-type domino logic

NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDD, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.

Speed Estimation of Three Phase Induction Motor Using Artificial Neural Network

Three phase induction motors being the most widely used motor for domestic, commercial and industrial applications, demands a more detailed understanding and improved analysis of its performance characteristics. The conventional method of using the equivalent circuit for assessing the motor performance cannot incorporate the non-linearities involved in the speed torque characteristics into the performance of the motor to the fullest extent. This paper presents an ANN based modeling of three phase induction motor to overcome this problem. The model has been tested and validated with actual experimental data. The performance of the model has been compared with that of a classical equivalent circuit technique both graphically and statistically and found to be superior. The model can thus offer a better method of speed estimation and control of the induction motor for input voltage variation with and without input frequency change.

Design optimization of double-sided permanent-magnet radial-flux eddy-current couplers

It is essential for engineers to improve overall performance of electromagnetic devices. In this paper, single/multi-objective design optimization of double-sided permanent-magnet radial-flux eddy-current couplers is carried out. To this end, an analytical model of such devices is developed by combining conventional magnetic equivalent circuit techniques with Faraday's and Ampere's laws. The model is capable of easily dealing with complex geometries and material properties such as iron saturation and the PM characteristics as well as the associated design constraints so that the designs that are more realistic can be achieved. A genetic algorithm that enjoys a flexible objective function is finally adopted to find the optimal machine parameters. Finite-element method is also employed to verify the results.

The Isolation DC-DC Partial Voltage Charge Equalization on Lithium-Ion Power Battery

The inconsistency of power battery pack is one of the key factors decreasing the battery performance. The common equalization techniques have some problems like control is complex; the equalization effect is not obvious and low efficiency. In this paper, an equalization charge apparatus was designed based on DC-DC partial voltage technique with the multiple secondary invert circuit and DSP technique and analyzed the main characteristics of this method. Its input is the energy of the whole battery pack. At last, an equilibrium charging experiment was done adopting a lithium-ion power battery pack constituted by 84 series 80Ah cells. The results show that the method can effectively improve the consistency of the battery, give full play to the performance of power battery and good equilibrium effect.

Numerical and experimental analysis of unidirectional meander-line coil electromagnetic acoustic transducers

The elastic waves generated by traditional meander-line coil electromagnetic acoustic transducers (EMATs) propagate in two directions, overlapping the echo signals from defects with the same distances, and the defect echo signal is hard to distinguish from the edge-reflected signal when the EMATs are near the edge of a specimen. In this paper, a unidirectional EMAT with two meander-line coils is proposed. A finite element model is used to simulate the directivity of the Rayleigh and shear vertical waves generated by these EMATs. Six transducers are fabricated using the printed circuit technique. The unidirectional Rayleigh wave and shear vertical wave are tested, and the results agree well with the simulation.

Achieving Ultralow Standby Power With an Efficient SCCMOS Bias Generator

Standby power frequently dominates the power budget of battery-operated ultralow power sensor nodes. Reducing standby power is therefore a key challenge for further power reduction. Applying known circuit techniques for standby power reduction is challenging since standby power of state-of-the-art sensor node systems is now on the order of nanowatts or less. Hence, the overhead of any leakage reduction technique quickly overshadows any gains. This brief proposes an efficient implementation method for super cutoff CMOS that exploits the unique conditions of power gating to enable a highly efficient charge pump design. The proposed techniques are applied to logic blocks and memory devices. For a very low initial standby power value of tens of picowatts, standby power reduction of up to 19.3 × and 29% is achieved for logic blocks and memory, respectively.

DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY

Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrading the performance of digital electronics circuit where adder is employed. In this paper, a single bit full adder circuit has been designed with the help of double gate (MOSFET), the used parameters value has been varied significantly for improving the performance of full adder circuit. Double gate transistor circuit considers as a promising candidate for low power application domain as well as used in radio frequency (RF) devices. Multi-threshold CMOS (MTCMOS) is the most used circuit technique to reduce the leakage current in idle circuit. In this paper, different parameters are analyzed on MTCMOS Technique. MTCMOS technique achieves 99.6% reduction of leakage current, active power is reduced by 42.64% and delay is reduced by 71.9% as compared with conventional double gate 14T full adder. Simulation results of double gate full adder have been performed on cadence virtuoso tool with 45 nm technology.