Circuit Structure Research Articles

ФОТОННА ІНТЕГРАЛЬНА СХЕМА ТА ЇЇ КАЛІБРУВАННЯ

The article proposes a new structure of a photonic integrated circuit for multiplying vector signals by a matrix. The architecture and principles of operation of modern photonic integrated circuits according to the given classification are briefly described. The proposed system consists of three layers, which includes a radiating, receiving and intermediate block with apertures. The connection of the photonic integrated circuit to the necessary electrical circuit for the investigation of the output signals of the photonic integrated circuit is described. With the help of the electrical circuit, we can monitor and control the input signals on each waveguide of the radiating unit, and track the change of the output signals that have passed through the system and fixed at the output of each waveguide. In the course of the study, we develop graphs of the levels of input and output signals of the system. With the help of which we represent the system errors and the change of signals, which makes it possible to calibrate the system. Calibration of the photonic integrated circuit is carried out by calibrating all electrical elements of the radiation and the receiving unit. In the emitting unit, it is necessary to select the same LEDs according to their characteristics, and with the help of variable resistors, which are connected to each pair of LEDs, calibrate the LED to the same brightness. We control the uniformity of brightness with the help of an IR camera. To calibrate the receiving unit, we fix the shadow noise and enter the reference coefficients for each receiver. After all the units were configured, the system was tested. A block with a specific aperture location was created, and the output signal was removed. Based on the results of the study, we proved that the system calibration is correct and that the system is operational.

A Load-Adaptive Driving Method for a Quasi-Continuous-Wave Laser Diode.

A quasi-continuous-wave (QCW) laser diode (LD) driver is commonly used to drive diode bars and stacks designed specifically for QCW operations in solid-state lasers. Such drivers are optimized to deliver peak current and voltage pulses to LDs while maintaining low average power levels. As a result, they are widely used in laser processing devices and laser instruments. Traditional high-energy QCW LD drivers primarily use capacitors as energy storage components and pulsed constant-current sources with op-amps and power metal-oxide-semiconductor field-effect transistors (MOSFETs) as their core circuits for generating repeated constant-current pulses. The drawback of this type of driver is that the driver's output voltage needs to be manually adjusted according to the operating voltage of the load before use to maximize driver efficiency while providing a sufficient current. Another drawback is its inability to automatically adjust the output voltage to maintain high efficiency when the load changes during the driver operation. Drastic changes in the load can cause the driver to fail to function properly in extreme cases. Based on the above traditional circuit structure, this study designed a stability compensation circuit and realized a QCW LD driver for driving a GS20 diode stack with a maximum repetition rate of 100 Hz, a constant current of approximately 300 A, a load voltage of approximately 10 V, and a pulse width of approximately 300 μs. In particular, a high-efficiency, load-adaptive driving method was used with the MOSFETs in the critical saturation region (i.e., between the linear and saturated regions), controlling its power loss effectively while achieving maximum output current of the driver. The experiments demonstrated that the driver efficiency could be maintained at more than 80% when the load current varied from 50 to 300 A.

A 20-GHz On-Chip Six-Port Reflectometer Using Simple Lumped Passive Devices and Bipolar Junction Transistors

This paper proposes an on-chip six-port reflectometer (SPR) fabricated in the 0.13-μm IBM BiCMOS-8HP technology. The SPR enjoys a compact circuit structure, with only four amplitude detectors as active devices, one resistive power divider, and one lumped phase shifter as passive devices. The power divider and phase shifter are responsible for manipulating the radio-frequency (RF) signals appropriately, whereas the detectors are responsible for sensing the processed signals. The chip area, which can be further reduced, is 1.25 mm in width and 1 mm in height. The SPR can perform in-situ measurement of reflection coefficients of devices under test (DUTs) and reduce testing costs of RF chips by using vector network analyzers (VNAs). The SPR demonstrates excellent performance in measuring the reflection coefficients of DUTs at around 20 GHz. The experimental results indicate that the maximum error of the measured reflection coefficients in absolute value is about -26 dB.

Study of oscillation characteristics for quartz crystal oscillators based on equivalent multi‐physics model

AbstractIn recent years, high‐performance quartz‐crystal oscillators (XOs) for integrated circuits have been receiving considerable attention due to their featuring low voltage and high‐frequency stability. However, recent studies tend to focus solely on the impact of temperature as a single factor on crystal oscillator circuits, overlooking the circuit structure of the crystal oscillator itself. In this paper, a novel four‐parameter crystal model of XOs is detailed demonstrated, and analyzed to interpret typical XO oscillation characteristics at room temperature. The relationship between the RLC circuit and the oscillation was investigated. Meanwhile, the study delves into the various factors that influence oscillation behavior, paving the way for a comprehensive understanding of XOs' performance characteristics. temperature sweep simulations were induced to verify the theory and found that the parameter drift and thermal perturbation are close to the theory we proposed, which can be applied in temperature‐compatible XOs. The significance of this study lies not only in its contribution to the design and implementation of compact footprint XOs in the oscillator circuit platform but also in its provision of experimental evidence for fabricating wide temperature range compensated XO devices. The results show that the capacitance in the equivalent model of a crystal oscillator plays a dominant role in shaping the output waveform and exhibits relatively good temperature stability characteristics and serve as a valuable resource for engineers and researchers working on improving the performance and reliability of XOs, ultimately enabling the development of more advanced and efficient integrated circuits.

Design and experiment study of a novel dual-channel independent-coil magnetorheological grease damper

In order to address the issue of reduced damping force dynamic range in magnetorheological (MR) damper caused by the high zero-field viscosity of MR grease, known for its sedimentation stability, this paper introduces a novel dual-channel independent-coil MR damper (DCICMRD). Firstly, the dual-channel configuration and the magnetic circuit structure of independent coils were meticulously designed, and a genetic algorithm was employed to conduct multi-objective optimization of the structural parameters for DCICMRD. The optimization results indicate that all performance metrics of the damper post-optimization exhibit improvements exceeding 15%. Then, the theocratical model of the damping force for DCICMRD under three operational modes are established, and the output damping force of various input currents for different operating mode is obtained. Finally, the DCICMRD was manufactured and subjected to dynamic performance testing. The results revealed that the damping force dynamic range in Mode III, i.e. dual-channel structure, can achieve approximately 15 times, whereas Mode I, i.e. traditional single-channel structure, only attains approximately 9 times. The aforementioned research holds significant implications for expanding the further engineering applications of MR dampers.

Design and optimization of CMOS based 4-bit comparator

The paper primarily focuses on optimizing circuit delay and energy consumption, specifically in gate-level circuits. Three methods are employed for circuit optimization. The first method aims to minimize transistor usage to reduce both delay and energy consumption. The second method involves prioritizing logic gates based on underlying hardware, favoring simpler circuit structures whenever possible, given that our design primarily revolves around logic gates. The third method entails adjusting the number of stages to enhance delay optimization. To validate these rules, three distinct circuits were designed to implement a 4-bit absolute value comparator, each corresponding to one of the rules. Through simulation, calculation, and comparison, the best circuit was identified, providing validation for the rules. The second part of the paper shifts its focus towards optimizing delay and energy consumption by adjusting the sizing of logic gates and the supply voltage to achieve optimal overall performance. In conclusion, further research is needed to corroborate these three rules and identify additional rules, laying the foundation for intelligent circuit optimization.

Resonant Gate Drive Circuit with Active Clamping to Increase Efficiency and Reliability

In power converters with high switching frequency, drive losses constitute a significant portion of the overall power losses. Resonant gate drivers can reduce drive losses, thereby enhancing the efficiency. However, resonant drivers suffer certain challenges: parameter drifts lead to the mismatch between the resonant frequency and the control frequency, and this mismatch can cause gate-to-source voltage overshoot. Moreover, the resonant driver is susceptible to external interference. This paper proposes a resonant circuit structure and control timing scheme aimed at overcoming these limitations. By incorporating a half-bridge clamp circuit, the proposed design achieves voltage clamping, thereby insulating the system from disturbances caused by mains power fluctuations. When there is a mismatch in resonant frequencies, the strategy employs a combination of hardware circuit diodes and control system timing to prevent overvoltage issues. Additionally, the utilization of MOSFETs minimizes the loss caused by prolonged current flow through body diodes, further reducing the resonant driving losses. Simulations have demonstrated the system’s stability under varying resonant parameters and its effective anti-interference capabilities in voltage clamping. Experiments achieved a power saving of 83.3% at a 1 MHz operating frequency. Both simulations and experimental validations confirm the feasibility of the proposed solution, its effectiveness in interference suppression, handling of resonant mismatches, and its role in further augmenting power conservation.

Rabies virus-based barcoded neuroanatomy resolved by single-cell RNA and in situ sequencing

Mapping the connectivity of diverse neuronal types provides the foundation for understanding the structure and function of neural circuits. High-throughput and low-cost neuroanatomical techniques based on RNA barcode sequencing have the potential to map circuits at cellular resolution and a brain-wide scale, but existing Sindbis virus-based techniques can only map long-range projections using anterograde tracing approaches. Rabies virus can complement anterograde tracing approaches by enabling either retrograde labeling of projection neurons or monosynaptic tracing of direct inputs to genetically targeted postsynaptic neurons. However, barcoded rabies virus has so far been only used to map non-neuronal cellular interactions in vivo and synaptic connectivity of cultured neurons. Here we combine barcoded rabies virus with single-cell and in situ sequencing to perform retrograde labeling and transsynaptic labeling in the mouse brain. We sequenced 96 retrogradely labeled cells and 295 transsynaptically labeled cells using single-cell RNA-seq, and 4130 retrogradely labeled cells and 2914 transsynaptically labeled cells in situ. We found that the transcriptomic identities of rabies virus-infected cells can be robustly identified using both single-cell RNA-seq and in situ sequencing. By associating gene expression with connectivity inferred from barcode sequencing, we distinguished long-range projecting cortical cell types from multiple cortical areas and identified cell types with converging or diverging synaptic connectivity. Combining in situ sequencing with barcoded rabies virus complements existing sequencing-based neuroanatomical techniques and provides a potential path for mapping synaptic connectivity of neuronal types at scale.

Rabies virus-based barcoded neuroanatomy resolved by single-cell RNA and in situ sequencing.

Mapping the connectivity of diverse neuronal types provides the foundation for understanding the structure and function of neural circuits. High-throughput and low-cost neuroanatomical techniques based on RNA barcode sequencing have the potential to map circuits at cellular resolution and a brain-wide scale, but existing Sindbis virus-based techniques can only map long-range projections using anterograde tracing approaches. Rabies virus can complement anterograde tracing approaches by enabling either retrograde labeling of projection neurons or monosynaptic tracing of direct inputs to genetically targeted postsynaptic neurons. However, barcoded rabies virus has so far been only used to map non-neuronal cellular interactions in vivo and synaptic connectivity of cultured neurons. Here we combine barcoded rabies virus with single-cell and in situ sequencing to perform retrograde labeling and transsynaptic labeling in the mouse brain. We sequenced 96 retrogradely labeled cells and 295 transsynaptically labeled cells using single-cell RNA-seq, and 4130 retrogradely labeled cells and 2914 transsynaptically labeled cells in situ. We found that the transcriptomic identities of rabies virus-infected cells can be robustly identified using both single-cell RNA-seq and in situ sequencing. By associating gene expression with connectivity inferred from barcode sequencing, we distinguished long-range projecting cortical cell types from multiple cortical areas and identified cell types with converging or diverging synaptic connectivity. Combining in situ sequencing with barcoded rabies virus complements existing sequencing-based neuroanatomical techniques and provides a potential path for mapping synaptic connectivity of neuronal types at scale.

PID Control of Hybrid DC-DC Converter System in Complex Load with Double Reference Time

Abstract: DC-DC converters are circuits that are widely used in energy distribution systems, in industry and technology applications, as well as in household appliances such as computers and televisions, and in uninterruptible power supplies used to feed all these systems. For the design and optimization of DC-DC converter circuits, it is important to create and analyze mathematical models according to the load it is connected to. Simple load structures and circuit structures have been examined and control units have been designed in studies carried out to date. In this study, while the DC-DC converter with a more complex load structure is discussed, mathematical analysis and PID control of DCDC converters with Buck-Boost feature are performed with the same modulation index in different time periods. In the results obtained, it is shown how to create the mathematical models of a system that provides DC-DC energy conversion with a complex load structure and how to formulate the PID control in a system with this complex load structure.

Current Status, Development, And Application of Optimization Methods for Analog Circuits

The optimization of analog circuits has always relied on the experience and intuition of engineers to find suitable parameters to meet the requirements of the circuit, which is time-consuming and costly. This paper outlines and analyzes the optimization methods for analog circuits in recent years, and draws some summaries that can be used as references for subsequent optimization circuits. The optimization of analog circuits is mainly divided into the optimization of the performance of the hardware in the circuit and the optimization of the circuit structure. Hardware optimization, this paper mainly focuses on the optimization of diodes, transistors, field effect tubes and operational amplifiers, the four main hardware optimizations, from the material, structure, production process and other aspects of the analysis. For the optimization of circuit structure, this paper mainly analyzes from the aspects of algorithms, mathematical models, and the use of integrated methods. The significance of these optimization methods and the outstanding advantages and main application directions of different methods are further explained. The search for optimization methods can reduce the high time cost of analog circuit optimization that is purely dependent on experience and intuition, and is significant in increasing efficiency.

Molecular circuit for exponentiation based on the domain coding strategy.

DNA strand displacement (DSD) is an efficient technology for constructing molecular circuits. However, system computing speed and the scale of logical gate circuits remain a huge challenge. In this paper, a new method of coding DNA domains is proposed to carry out logic computation. The structure of DNA strands is designed regularly, and the rules of domain coding are described. Based on this, multiple-input and one-output logic computing modules are built, which are the basic components forming digital circuits. If the module has n inputs, it can implement 2n logic functions, which reduces the difficulty of designing and simplifies the structure of molecular logic circuits. In order to verify the superiority of this method for developing large-scale complex circuits, the square root and exponentiation molecular circuits are built. Under the same experimental conditions, compared with the dual-track circuits, the simulation results show that the molecular circuits designed based on the domain coding strategy have faster response time, simpler circuit structure, and better parallelism and scalability. The method of forming digital circuits based on domain coding provides a more effective way to realize intricate molecular control systems and promotes the development of DNA computing.

Pseudorange reconstruction for high‐dynamic eLoran signal simulators using B‐spline interpolation

AbstractThe High‐Dynamic enhanced Loran (eLoran) signal simulator must accurately model the motion parameters and dynamic transmission delays of the carriers in the channel. A method was proposed based on B‐Spline interpolation, capable of arbitrary ratio interpolation and multi‐channel simulation. This method can regenerate carrier‐to‐transmitter distances from available discrete motion asynchronous data, it can effectively reproduce more motion details for carrier. The algorithm can be implemented using digital circuits, allowing for real‐time simulation on a hardware platform. The circuit structure is divided into integer and fractional calculations, which can satisfy the interpolation of asynchronous data with arbitrary ratios. Compared with existing methods, the approach simulates the motion parameters with satisfactory accuracy.

A 78 dB 0.417 mW Second-Order NS SAR ADC with Dynamic Amplifier-Assisted Integrator

The noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is an innovative hybrid structure that offers performance advantages. The NS-SAR ADC leverages the SAR ADC as its foundation and combines oversampling technology and noise-shaping technology found in Sigma-Delta ADC. This integration effectively combines the strengths of both structures and enhances overall performance. The ADC features a simple circuit structure, compact chip area, and high energy efficiency, which has positioned it as a prominent research area. In this paper, leveraging the TSMC 65 nm GP process, the NS-SAR ADC is designed with a power supply voltage of 1 V. This design adopts an 8-bit differential capacitor structure, operates at a sampling frequency of 16 MS/s, and achieves an oversampling rate of 16 times the desired performance indicators. Through extensive circuit post simulation verification, the SNR obtained reaches 78 dB, providing an effective bit resolution of 12.7 bits. The core chip area of the ADC measures 366 × 333 μm2, while the power consumption is impressively low at 417 μW and FoMs is 168 dB.

A Star Network of Bipolar Memristive Devices Enables Sensing and Temporal Computing.

Temporal (race) computing schemes rely on temporal memories, where information is represented with the timing of signal edges. Standard digital circuit techniques can be used to capture the relative timing characteristics of signal edges. However, the properties of emerging device technologies could be particularly exploited for more efficient circuit implementations. Specifically, the collective dynamics of networks of memristive devices could be leveraged to facilitate time-domain computations in emerging memristive memories. To this end, this work studies the star interconnect configuration of bipolar memristive devices. Through circuit simulations using a behavioral model of voltage-controlled bipolar memristive devices, we demonstrated the suitability of such circuits in two different contexts, namely sensing and "rank-order" coding. We particularly analyzed the conditions that the employed memristive devices should meet to guarantee the expected operation of the circuit and the possible effects of device variability in the storage and the reproduction of the information in arriving signal edges. The simulation results in LTSpice validate the correct operation and confirm the promising application prospects of such simple circuit structures, which, we show, natively exist in the crossbar geometry. Therefore, the star interconnect configuration could be considered for temporal computations inside resistive memory (ReRAM) arrays.

Capacitorless DC-DC Regulator as a Candidate Topology for Photovoltaic Solar Facilities

Linear-assisted DC/DC converters (or linear-switching hybrid DC/DC converters) consist of a voltage linear regulator (classic NPN or nMOS topologies and LDO) connected in parallel with a switching DC/DC converter. They are a good candidate for energy processing in photovoltaic solar facilities. In order to control these hybrid structures, different strategies exist, allowing fixing the switching frequency as a function of some parameters of the linear regulator. This article compares two control strategies that, although can be applied to the same circuital structure of linear-assisted converter, are sensibly different. The first one, reported in previous literature, cancels completely the average current through the linear regulator in steady state to achieve a reduction of the losses. Thus the efficiency of the whole system increases and almost equals the one of the standalone switching converter. The proposed approach, in spite of a slightly increment of linear regulator’s losses, reduces the output ripple due to the crossover distortion of linear regulator output stage.

The conserved RNA-binding protein Imp is required for the specification and function of olfactory navigation circuitry in Drosophila

Complex behaviors depend on the precise developmental specification of neuronal circuits, but the relationship between genetic programs for neural development, circuit structure, and behavioral output is often unclear. The central complex (CX) is a conserved sensory-motor integration center in insects, which governs many higher-order behaviors and largely derives from a small number of type II neural stem cells (NSCs). Here, we show that Imp, a conserved IGF-II mRNA-binding protein expressed in type II NSCs, plays a role in specifying essential components of CX olfactory navigation circuitry. We show the following: (1) that multiple components of olfactory navigation circuitry arise from type II NSCs. (2) Manipulating Imp expression in type II NSCs alters the number and morphology of many of these circuit elements, with the most potent effects on neurons targeting the ventral layers of the fan-shaped body (FB). (3) Imp regulates the specification of Tachykinin-expressing ventral FB input neurons. (4) Imp is required in type II NSCs for establishing proper morphology of the CX neuropil structures. (5) Loss of Imp in type II NSCs abolishes upwind orientation to attractive odor while leaving locomotion and odor-evoked regulation of movement intact. Taken together, our findings establish that a temporally expressed gene can regulate the expression of a complex behavior by developmentally regulating the specification of multiple circuit components and provides a first step toward a developmental dissection of the CX and its roles in behavior.

Demonstration of a terahertz integrated planar network synthesis filter

At terahertz (THz) frequencies, there are few experimental works that demonstrate the viability of all-pole network synthesis filters to obtain desired frequency characteristics (i.e., Chebyshev, Butterworth, Bessel, etc.) using planar waveguides. This capability has been proven with non-planar waveguides, but has yet to be demonstrated using planar waveguides, which are desirable due to their integration capabilities similar to printed circuit board or monolithic microwave integrated circuit structures. In this paper, we use network synthesis methods from microwave engineering to fabricate three integrated planar low-pass filters for THz applications that have the same cut-off frequency (f c = 0.8 THz) but different orders (N = 3, 4, 5). We measure their response to a THz-bandwidth excitation pulse and find that the experimental results exhibit increasing roll-off rates with increasing filter order without incurring significant pulse distortion, which is aligned with theory.

The optimization and operation of multi-energy-coupled microgrids by the improved fireworks algorithm-shuffled frog-leaping algorithm.

This study aims to address optimization and operational challenges in multi-energy coupled microgrids to enhance system stability and reliability. After analyzing the requirements of such systems within comprehensive energy systems, an improved fireworks algorithm (IFWA) is proposed. This algorithm combines an adaptive resource allocation strategy with a community genetic strategy, automatically adjusting explosion range and spark quantity based on individual optimization status to meet actual needs. Additionally, a multi-objective optimization model considering active power network losses and static voltage is constructed, utilizing the shuffled frog-leaping algorithm (SFLA) to solve constrained multi-objective optimization problems. Through simulation experiments on a typical northern comprehensive energy system, conducted with a scheduling period of T = 24, the feasibility and superiority of IFWA-SFLA are validated. Results indicate that IFWA-SFLA performs well in optimizing microgrid stability, managing electrical energy flow effectively within the microgrid, and reducing voltage fluctuations. Furthermore, the circuit structure and control strategy of microgrid energy storage bidirectional inverters based on IFWA are discussed, along with relevant simulation results.

Control System Analysis of a Linear Rotary Motor with Single Directional Magnetic Circuit Structure

Control System Analysis of a Linear Rotary Motor with Single Directional Magnetic Circuit Structure