Design and optimization of CMOS based 4-bit comparator

Abstract

The paper primarily focuses on optimizing circuit delay and energy consumption, specifically in gate-level circuits. Three methods are employed for circuit optimization. The first method aims to minimize transistor usage to reduce both delay and energy consumption. The second method involves prioritizing logic gates based on underlying hardware, favoring simpler circuit structures whenever possible, given that our design primarily revolves around logic gates. The third method entails adjusting the number of stages to enhance delay optimization. To validate these rules, three distinct circuits were designed to implement a 4-bit absolute value comparator, each corresponding to one of the rules. Through simulation, calculation, and comparison, the best circuit was identified, providing validation for the rules. The second part of the paper shifts its focus towards optimizing delay and energy consumption by adjusting the sizing of logic gates and the supply voltage to achieve optimal overall performance. In conclusion, further research is needed to corroborate these three rules and identify additional rules, laying the foundation for intelligent circuit optimization.