Circuit Structure Research Articles

Acceleration for Efficient Automated Generation of Operational Amplifiers.

Operational amplifiers (Op-Amps) are critical to sensor systems because they enable precise, reliable, and flexible signal processing. Current automated Op-Amp generation methods suffer from extremely low efficiency because the time-consuming SPICE-in-the-loop sizing is normally involved as its inner loop. In this paper, we propose an efficiently automated Op-Amp generation tool using a hybrid sizing method, which combines the merits together from a deterministic optimization algorithm and differential evolution algorithm. Thus, it can not only quickly find a decent local optimum, but also eventually converge to a global optimum. This feature is well fit to be serving as an acute filter in the circuit structure evaluation flow to efficiently eliminate any undesirable circuit structures in advance of detailed sizing. Our experimental results demonstrate its superiority over traditional sizing approaches and show its efficacy in highly boosting the efficiency of automated Op-Amp structure generation.

Accurate and gate-efficient quantum Ansätze for electronic states without adaptive optimization

The ability of quantum computers to overcome the exponential memory scaling of many-body problems is expected to transform quantum chemistry. Quantum algorithms require accurate representations of electronic states on a quantum device, but current approximations struggle to combine chemical accuracy and gate efficiency while preserving physical symmetries, and rely on measurement-intensive adaptive methods that tailor the wave function to each molecule. In this contribution, we present a symmetry-preserving and gate-efficient that provides chemically accurate molecular energies with a well-defined circuit structure. Our approach exploits local qubit connectivity, orbital optimization, and connections with generalized valence bond theory to maximize the accuracy that is obtained with shallow quantum circuits. Numerical simulations for molecules with weak and strong electron correlation, including benzene, water, and the singlet-triplet gap in tetramethyleneethane, demonstrate that chemically accurate energies are achieved with as much as 84% fewer two-qubit gates compared to state-of-the-art adaptive techniques. Published by the American Physical Society 2024

Design of a Wilkinson Power Divider with Harmonic Suppression for Mobile Application

This paper presents a Wilkinson Power Divider (WPD) operating at 6 GHz capable of suppressing unwanted harmonics up to the 3rd harmonic. The design formulas are analysed and presented in detail. Power dividers are widely used in microwave circuit structures. Indeed, this paper outlines the design and simulation of a 1:1 power divider for mobile applications using CST Studio Suite.

Method for Predicting Linear Eddy Current Braking Performance of the High-Speed Maglev Train Based on Magnetic Circuit Structure

On high-speed magnetic levitation (maglev) trains, the linear eddy current brake (LECB) is a key piece of equipment to ensure the safety of train operation. In the event of a sudden failure of the traction motor or the external power grid, braking by the LECB, which comes with the maglev train, is currently the only emergency braking method that can ensure the train can be safely stopped while operating at high speed. The braking performance of eddy current brakes is usually predicted based on symmetrical magnetic equivalent circuits, which usually ignore the interactions between the magnetic circuits. For LECB, such interactions should not be neglected. In this paper, to investigate an accurate and efficient method for predicting the braking performance of LECB for high-speed maglev trains, based on the structural characteristics of LECB and Kirchhoff’s law, a full structural magnetic equivalent circuit model considering the interactions between magnetic circuits is developed, and then combined with the subdomain method, a braking force model, to predict the braking performance of LECB. The performance prediction of LECB with different numbers of magnetic poles is compared with the traditional method using the results of the finite element method and the experimental method as references. The results show that the proposed method is more accurate in predicting the braking performance of LECB and better reflects the physical characteristics of the actual magnetic field.

Endogenous opioids facilitate stress-induced binge eating via an insular cortex-claustrum pathway.

Stress has been shown to promote the development and persistence of binge eating behaviors. However, the neural circuit mechanisms for stress-induced binge-eating behaviors are largely unreported. The endogenous dynorphin (dyn)/kappa opioid receptor (KOR) opioid neuropeptide system has been well established to be a crucial mediator of the anhedonic component of stress. Here, we aimed to dissect the basis of dynorphinergic control of stress-induced binge-like eating behavior. We first established a mouse behavioral model for stress-induced binge-like eating behaviors. We found that mice exposed to stress increased their food intake of familiar palatable food (high fat, high sugar, HPD) compared to non-stressed mice. Following a brain-wide analysis, we isolated robust cFos-positive cells in the Claustrum (CLA), a subcortical structure with highly abundant KOR expression, following stress-induced binge-eating behavior. We report that KOR signaling in CLA is necessary for this elevated stress-induced binge eating behavior using local pharmacology and local deletion of KOR. In vivo calcium recordings using fiber photometry revealed a disinhibition circuit structure in the CLA during the initiation of HPD feeding bouts. We further established the dynamics of endogenous dynorphinergic control of this behavior using a genetically encoded dynorphin biosensor, Klight. Combined with 1-photon single-cell calcium imaging, we report significant heterogeneity with the CLA population during stress-induced binge eating and such behavior attenuates local dynorphin tone. Furthermore, we isolate the anterior Insular cortex (aIC) as the potential source of endogenous dynorphin afferents in the CLA. By characterizing neural circuits and peptidergic mechanisms within the CLA, we uncover a pathway that implicates endogenous opioid regulation stress-induced binge eating.

A Simple Scan Driver Circuit Suitable for Depletion-Mode Metal-Oxide Thin-Film Transistors in Active-Matrix Displays

Metal-oxide (MOx) thin-film transistors (TFTs) require complex circuit structures to cope with their depletion mode characteristics, making them applicable only to large-area active matrix (AM) displays despite their low manufacturing cost and decent performance. In this paper, we report a simple MOx 10T-2C scan driver circuit that overcomes the depletion mode characteristics using a series-connected two transistor (STT) configuration and clock signals with two kinds of low-voltage levels. The proposed circuit has a wide operating range of TFT characteristics, i.e., −2.8 V ≤ VTH ≤ +3.0 V. Through the measurement results of the manufactured sample, it was confirmed that the performance and area of our circuit are suitable for high-resolution mobile displays.

Active Equalization for Lithium-Iron Battery Pack Based on Reduced-Order Solving Strategy for the Hanoi Tower Problem

In order to address the energy imbalance issue of a series-connected lithium-iron battery pack, this paper proposes an active equalization method based on a reduced-order solving strategy for the Hanoi Tower problem. The proposed scheme utilizes a combined structure of a switching-network circuit and a bidirectional Cuk converter and leverages an ultracapacitor cell as the energy-transfer carrier. Simulation and comparison demonstrate that the exchange of unbalanced energy within the battery pack can be achieved. The proposed approach can effectively achieve various balancing modes such as cell-to-cell, cell-to-string, string-to-cell, and string-to-string with a relatively fast balancing speed.

Effect of bias magnetic field on transducer efficiency in electromagnetic ultrasonic non-destructive testing of Rock bolt

Non-destructive testing (NDT) of rock bolt anchoring quality is an important part of engineering quality and safety control, electromagnetic ultrasonic NDT is one of the promising detection methods, and improving the efficiency of ultrasonic transducer by optimizing the bias magnetic field is an important factor to obtain effective information. In this paper, several factors affecting the bias magnetic field are studied, and the work is divided into simulation and demonstration: COMSOL was used to simulate the electromagnetic ultrasonic transducer(EMAT) in order to analyze the influence of the number of magnetic circuit, the thickness of magnet and the thickness of yoke iron on the bias magnetic field. Then, an experimental platform was built, the magnetic circuit structure of the transducer was set with reference to the simulation results, and several important parameters of the bias magnetic field were determined by analyzing the collected signals. The results show that with the increase of the bias magnetic field magnetic circuit structure from independent to ring form, the magnetic field strength of the rock bolt increases, the magnetic field uniformity becomes better, and the efficiency of the transducer is also improved accordingly. In addition, under the same magnetic circuit condition, increasing the thickness of permanent magnet and yoke iron does not increase the magnetic flux density of the rock bolt axis proportionally, and has a limited effect on the efficiency of the transducer. In practical application, the corresponding structure is selected according to the needs, and the better bias magnetic field structure is selected while meeting the efficiency of the transducer.

Research on vibration test method of electric actuator

Abstract The stable, safe, and reliable operation of electric actuator valve systems is of great significance in industrial production. This paper proposes a vibration test method for electric actuators, employing the test to meet the test severity level as the first priority, with random frequency vibration within 10 Hz to 1000 Hz. The vibration acceleration is loaded with a Gaussian distribution, which can be used to simulate the irregular vibration of electric actuators in the actual working conditions of the working environment. The test is divided into up and down vibration (z-axis), left and right vibration (x-axis), and front and rear vibration (y-axis) in three directions independently to verify the electric actuator from the mechanical structure and the circuit structure in order to meet the reliability requirements of the actual production.

46‐2: Reliable Gate Driver for Eye‐Tracking in High PPI VR Display Using LTPS TFTs

This paper demonstrates a novel low‐temperature‐poly‐Si thin film transistor (LTPS TFTs) gate driver with an isolated gate cascading output structure and staggered time node driving method to enhance the driving ability for high PPI VR display. The driver supports Foveated Rendering Display (FRD) mode, which enables eye tracking by exchanging two processes. Compared with conventional ones, the proposed driver shows enhanced driving ability due to the separation of gate output and gate cascading. Besides, the proposed gate driver reduces layout space for high PPI VR display by adopting a single cascade dual driving circuit structure. The proposed circuit still works well when Vth deviates by 3V and Ion decreases to 50%.

Design of a Low Power and Wide Frequency Range Ring VCO

This paper proposes a low-power, wide frequency range ring VCO circuit structure based on the application of switch power supply modulation technology. Circuit simulation is completed based on CMSC 180nm BCD process. Simulation results show that the VCO circuit can work at a power supply voltage of 3-5 V, and it has a relatively wide frequency range. Under a 5V power supply voltage and a control voltage range of 4.2V~2.2V, the output frequency range is 0.4-11.96MHz. Under a 3V power supply voltage and a control voltage of 2.2V~0.2V, the output frequency range is 0.56~12.3MHz. For the VCO circuit, the maximum average working current of the power supply is less than 80uA, and the average current of the power supply is only 35uA under a 5V power supply voltage and a 10MHz working frequency. The VCO circuit meets the requirements of low power consumption. It can be applied to switch power supply chips.

Theoretical principles explain the structure of the insect head direction circuit.

To navigate their environment, insects need to keep track of their orientation. Previous work has shown that insects encode their head direction as a sinusoidal activity pattern around a ring of neurons arranged in an eight-column structure. However, it is unclear whether this sinusoidal encoding of head direction is just an evolutionary coincidence or if it offers a particular functional advantage. To address this question, we establish the basic mathematical requirements for direction encoding and show that it can be performed by many circuits, all with different activity patterns. Among these activity patterns, we prove that the sinusoidal one is the most noise-resilient, but only when coupled with a sinusoidal connectivity pattern between the encoding neurons. We compare this predicted optimal connectivity pattern with anatomical data from the head direction circuits of the locust and the fruit fly, finding that our theory agrees with experimental evidence. Furthermore, we demonstrate that our predicted circuit can emerge using Hebbian plasticity, implying that the neural connectivity does not need to be explicitly encoded in the genetic program of the insect but rather can emerge during development. Finally, we illustrate that in our theory, the consistent presence of the eight-column organisation of head direction circuits across multiple insect species is not a chance artefact but instead can be explained by basic evolutionary principles.

A Ciphertext Reduction Scheme for Garbling an S-Box in an AES Circuit with Minimal Online Time

The secure computation of symmetric encryption schemes using Yao’s garbled circuits, such as AES, allows two parties, where one holds a plaintext block m and the other holds a key k, to compute Enc(k,m) without leaking m and k to one another. Due to its wide application prospects, secure AES computation has received much attention. However, the evaluation of AES circuits using Yao’s garbled circuits incurs substantial communication overhead. To further improve its efficiency, this paper, upon observing the special structures of AES circuits and the symmetries of an S-box, proposes a novel ciphertext reduction scheme for garbling an S-box in the last SubBytes step. Unlike the idea of traditional Yao’s garbled circuits, where the circuit generator uses the input wire labels to encrypt the corresponding output wire labels, our garbling scheme uses the input wire labels of an S-box to encrypt the corresponding “flip bit strings”. This approach leads to a significant performance improvement in our garbling scheme, which necessitates only 28 ciphertexts to garble an S-box and a single invocation of a cryptographic primitive for decryption compared to the best result in previous work that requires 8×28 ciphertexts to garble an S-box and multiple invocations of a cryptographic primitive for decryption. Crucially, the proposed scheme provides a new idea to improve the performance of Yao’s garbled circuits. We analyze the security of the proposed scheme in the semi-honest model and experimentally verify its efficiency.

An area‐effective and low‐power single‐slope ADC for DCG imaging CMOS image sensor

SummaryThis paper introduces an area‐effective and low‐power readout circuit structure tailored for high dynamic range (HDR) CMOS image sensors (CISs) utilizing dual conversion gain (DCG) imaging technology. A switched capacitor amplifier, which is applied at the comparator input port of the column‐parallel single‐slope analog‐to‐digital converter (SS ADC), is proposed to compensate for the charge injection and clock feed‐through introduced when the pixel switches between high conversion gain (HCG) and low conversion gain (LCG) modes. The proposed SS ADC is supplemented by the integration of a configurable counter, and the counter is specifically crafted for performing the A/D conversion of the readout voltage within a DCG pixel. Compared to the conventional DCG readout circuit, the proposed readout circuit use only one ADC for A/D conversion of HCG signals and LCG signals, which greatly reduces the area and power consumption of the readout circuit. Simulation results under 110 nm CMOS technology illustrate that the proposed 10‐bit SS ADC has a DNL of +0.78/−0.91 LSB and an INL of +1.91/−1.69 LSB, with a SNR of 57.2 dB and a SNDR of 55.95 dB, corresponding to an ENOB of 9 bits. The power consumption of the proposed SS ADC is 56.4 μW per column with a conversion time of 12 μs, and the simulation results show that the power consumption is 23.35% lower than the conventional structure and the area is saved by 24.69%.

Simulation and test for the micro-newton electromagnetic calibration force measurement

For micro-Newton (μN) level thrust measurement, achieving highly accurate calibration forces is crucial as an initial step. To provide high-precision and wide-range electromagnetic calibration forces, this study introduces a C-type magnetic circuit structure and a rectangular coil combination method. The magnetic field distribution within the device’s characteristic region was examined using the finite element method, and the impact of the relative positions of the rectangular coil and magnet was explored. Subsequently, calibration experiments were conducted on a specially developed platform. The primary findings are as follows: The electromagnetic force calibration range is from 0.097 to 237.32 μN, with the maximum error between experimental measurement data and simulation results being 1.73%. With a coil current resolution of 10 μA, the measured resolution of the calibration force exceeds 0.1 μN. Within the characteristic region, the magnetic field distribution exhibits high uniformity, with a maximum deviation rate of only 0.7%. This research establishes a technique for micro-Newton level thrust measurement.

A [92.4] FO4(1V), [53.71] Eu(1V) 4-bit absolute-value detector

With the development of modern computers, the integration of chips is getting higher and higher, and as the computing power increases, the energy consumption of chips is also increasing. Therefore, designing and optimizing low-latency and low-energy chips are the goals of many researchers today. At the same time, 4-bit absolute value detector are one of the most basic and important circuits for data storage and processing in chips. This paper designs a 4-bit absolute value detector circuit using Complementary Metal Oxide Semiconductor (CMOS) transistors that can take the absolute value of the input 4-bit signed number and compare it with the threshold value. And it includes the design of its absolute value conversion module and comparator module. By optimizing the circuit structure, the number of logic gates is reduced. By calculating the minimum delay on the critical path, logic gate size and other parameters, the power consumption of the circuit is reduced by adjusting the delay. In conclusion, this paper research can help further optimize the development of chip design industry.

Nr4a1 regulates cell-specific transcriptional programs in inhibitory GABAergic interneurons

The patterns of synaptic connectivity and physiological properties of diverse neuron types are shaped by distinct gene sets. Our study demonstrates that, in the mouse forebrain, the transcriptional profiles of inhibitory GABAergic interneurons are regulated by Nr4a1, an orphan nuclear receptor whose expression is transiently induced by sensory experiences and is required for normal learning. Nr4a1 exerts contrasting effects on the local axonal wiring of parvalbumin- and somatostatin-positive interneurons, which innervate different subcellular domains of their postsynaptic partners. The loss of Nr4a1 activity in these interneurons results in bidirectional, cell-type-specific transcriptional switches across multiple gene families, including those involved in surface adhesion and repulsion. Our findings reveal that combinatorial synaptic organizing codes are surprisingly flexible and highlight a mechanism by which inducible transcription factors can influence neural circuit structure and function.

Efficient design approaches to CMOS full adder circuits

In the field of high-performance chip designs, many applications have the ability to tolerate small errors through the use of approximate full adders. By appropriately reducing the corresponding precision, the performance of hardware implementation can be greatly improved. The adders are commonly applied in digital signal processors (DSP), communication systems, image processing, etc., to quickly complete addition estimation operations. This paper proposes the designs of 8 approximate adders and compares their performance with existing circuit structures. Simulation results demonstrate that the approximate adders proposed in the first group (i.e., LCAFA1∼LCAFA3) achieve an average area reduction of 21.44 % and an average delay reduction of 42.85 %. In the second group, the proposed approximate adders LCAFA4∼LCAFA8 achieve an average power reduction of 28.35 %, an average area reduction of 17.39 %, an average delay reduction of 84.25 %, and an average decrease in the power-area-delay product (PADP) of 68.26 %.

Constructing chaotic oscillators with memory components

Memory components, including memristors, meminductors and memcapacitors, have special nonlinear dynamical properties and thus applicable for constructing a compact chaotic circuit in parallel or in series. By selecting the restriction of a memory component, chaos control can also be achieved using a single circuit parameter. In this work, three different types of circuit structures are designed to implement memory components for chaos generation. With the help of a voltage-control or a current-control memristor, within a series or a parallel structure, a memristive chaotic oscillator with partial control is built based on the variable boostable systems. The two constructed structures are equivalent and can be mutually tuned, achieving partial amplitude control as well as offset boosting. By constructing a magnetic-control meminductor or a charge-control memcapacitor, the equivalent parallel circuit is built with a meminductor, a capacitor and a resistor, corresponding to the series circuit with a memcapacitor, an inductor and a resistor. It can be applied to realizing the hypogenetic chaotic jerk system even with conditional symmetry. All the designed circuits are physically realized based on PCB, proving the effectiveness of memory components for chaos generation.

Analysis, Design and Effectuation of a Tapped Inductor Current Converter with Fractional Output for Current Source Systems

This article proposes a new connection method of tapped inductors that works in the current source, which enables the current-mode power converter circuit to have a new topological relationship. Usually, in a switched-inductor circuit, a stable output multiple is obtained through the connection of the inductor and the switching devices. This is because the tapped point on the inductor varies, and the magnetomotive force (mmf) of inductance is adjusted. Thereby, the output current is controlled by the states of switching devices within a certain range. This optimized circuit structure can adjust the output current according to load changes in practical applications without changing the input power supply. The proposed method has been verified for its feasibility through detailed analysis and hardware work. The principal analysis based on the flux linkage and the PSIM simulation confirms that the theoretical circuit can be implemented. Finally, a hardware circuit is built to obtain real and feasible conclusions, and it is verified that the circuit can achieve a stable output and variable current within a specific range. The proposed work presents an alternative power conversion methodology using the active switching of mmf, and it is a stable and simple power conversion technique.