Circuit Performance Research Articles

Investigation of long channel bulk MOSFETs threshold voltage model down to 10 mK and key analog parameters at 4 K

AbstractThreshold voltage behavior at cryogenic temperatures is dominated by interface traps. This mechanism leads to different trends of the threshold voltage for NMOS and PMOS toward deep cryogenic temperature. This study investigates threshold voltage (Vth) at cryogenic temperatures down to 10 mK for the first time, based on the recently developed physical charge‐based analytical threshold voltage model. To investigate the impact of devices on circuits at low temperatures, crucial MOSFET and analog design parameters, including transconductance (gm), subthreshold swing (SS), linear region current (Ilin) and gm/IDS related parameters are characterized and compared from 300 to 4 K. A Discussion on circuit performance and power consumption has been conducted to provide useful insights for low‐temperature CMOS circuit design.

Effects of fluid dynamics parameters on flow-accelerated corrosion at elbow of carbon steel pipeline

Flow-accelerated corrosion (FAC) has always posed a significant threat to the safe operation of the secondary circuit in nuclear power units. In this study, we investigated typical carbon steel elbow pipe sections susceptible to FAC failure using fluid dynamics software to analyze the hydrodynamic characteristics at varying inlet velocities (2 m s−1, 4 m s−1, and 6 m s−1). The distribution of the FAC rate was monitored in real time using an array electrode. The results revealed that the outermost side of the elbow pipe section was the most susceptible location to FAC. By comparing different fluid dynamic parameters with the FAC rate, we identified radial velocity as an effective parameter for characterizing the FAC rate. Additionally, we established an empirical formula for predicting flow-accelerated corrosion in elbow pipe sections using the least squares method. The implications of this research are pertinent to the design and operation of pipelines in nuclear power plants.

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

How does crosstalk influence the jitter of a clock signal?

The stability and accuracy of the clock signal are crucial for the proper operation of various electronic devices and systems, as they directly impact system performance. In high-speed electronic systems, the clock signal is susceptible to interference by crosstalk. Therefore, evaluating the performance of the clock signal under crosstalk disturbance is important. Jitter, commonly used as an indicator to assess the degree of this interference, plays a significant role in this evaluation. In this paper, a method is proposed for assessing crosstalk-induced jitter (CIJ) based on scattering parameters. To verify the effectiveness of the method, CIJ was measured for clock signals with frequencies of 25, 100, and 156.25MHz. In addition, the experimental results are well in agreement with the theoretical model. Thus, the potential application of this method is to assess the performance of circuits or electronic systems.

Bidirectional DC - DC Converter Topology for Electric Vehicles Using Fuzzy Logic Controller

This project organizes an application of hybrid electric vehicle systems operated with novel designed bidirectional dc-dc converter (BDC) which interfaces a main energy storage (ES1), an auxiliary energy storage (ES2) and dc bus of different voltage levels. Proposed BDC converter can operate both step up and step-down mode. In which step up mode represents low voltage dual source -powering mode and step-down mode represents high voltage dc link energy –regenerating mode, both the modes are operated under the control of bidirectional power flow. This model can independently control power flow between low voltage dual source buck/boost modes. Here in, the circuit configuration, operation, steady-state analysis, and closed-loop control of the proposed BDC are discussed according to its three modes of power transfer. In this project fuzzy logic controller is used and also system results are validating through MATLAB/SIMULINK software. Index Terms—Bidirectional dc/dc converter (BDC), dual battery storage, hybrid electric vehicle, Fuzzy logic controller.

Near-Field Probing of Microwave Oscillators with Josephson Microscopy.

Voltage-controlled oscillators, serving as fundamental components in semiconductor chips, find extensive applications in diverse modules such as phase-locked loops, clock generators, and frequency synthesizers within high-frequency integrated circuits. This study marks the first implementation of superconducting Josephson probe microscopy for near-field microwave detection on multiple voltage-controlled oscillators. Focusing on spectrum tracking, various phenomena, such as stray spectra and frequency drifts, were found under nonsteady operating states. Parasitic electromagnetic fields, originating from power supply lines and frequency divider circuits, were identified as sources of interference between units. The investigation further determined optimal working states by analyzing features of the microwave distributions. Our research not only provides insights into the optimization of circuit design and performance enhancement in oscillators but also emphasizes the significance of nondestructive near-field microwave microscopy as a pivotal tool in characterizing integrated millimeter-wave chips.

Enzyme-driven converter and amplifier for inert double-stranded DNA without sequence restrictions

DNA molecules in life play a crucial role in various fields. However, DNA-based technologies confront significant difficulties in dealing with inert double-stranded DNA (dsDNA) with a blunt end without specific sequences. In this work, we utilized Thermus thermophilus Argonaute (TtAgo) and Vent DNA polymerase to construct an enzyme-driven device to convert and amplify arbitrary blunt-ended dsDNA into single-stranded DNA (ssDNA), thereby adapting to subsequent functional units. Based on the excellent performance of the dsDNA to ssDNA converter and amplifier (DSCA), inert dsDNA could be effectively identified. Additionally, DSCA accomplishes information interception and transmission, addressing the problem of dsDNA input response in DNA circuits and clinical diagnosis. Given these facts, this DSCA is expected to serve as a broad toolbox for the information transformation and amplification of inert dsDNA, prospering DNA circuit operations, and biosensing.

Ultra-Low Power 9T FinFET Based SRAM Cell for IoT Applications

The rapid proliferation of Internet of Things (IoT) devices has escalated the demand for energy-efficient memory solutions. The development of SRAM (Static Random-Access Memory) has gathered significant attention, particularly for low-power applications and portable devices. This research introduces a novel approach to ensure robust performance and operational integrity, all while adhering to stringent power constraints amidst process and temperature fluctuations. This quest for alternative nano-devices has been ignited by the scaling and channel control challenges intrinsic to CMOS technology. Among the array of alternatives, including FinFETs, TFETs, and CNTFETs, FinFETs have emerged as strong contenders. FinFET SRAMs contribute to the ongoing drive for electronic devices to become more compact and energy-efficient. They offer a distinct advantage as a promising CMOS substitute, attributed to their high performance, stability, with low power consumption characteristics at the nanoscale. The study proposes an ultra-low power 9T FinFET based SRAM cell meticulously designed for IoT applications. Leveraging the unique attributes of FinFET based 9T cell, the proposed SRAM cell is tailored to achieving minimal power consumption while maintaining inherent stability. The study assesses the performance of the proposed SRAM cells for power dissipation, stability, speed, and energy efficiency, and compares them with existing SRAM structures. The results are obtained through the Monte Carlo simulation technique, which evaluates circuit performance under specified conditions. The study achieves remarkable efficiency gains with 9T SRAM cells compared to other configurations. Additionally, the reduced read and write access times facilitate expedited data retrieval and storage operations.

Identification of Key Variables in Improving the Performance of Electronic Circuits

Identification of Key Variables in Improving the Performance of Electronic Circuits

Optimization of Graphical Parameter Extraction Algorithm for Chip-Level CMP Prediction Model Based on Effective Planarization Length.

As a planarization technique, chemical mechanical polishing (CMP) continues to suffer from pattern effects that result in large variations in material thickness, which can influence circuit performance and yield. Therefore, tools for predicting post-CMP chip morphology based on the layout-dependent effect (LDE) have become increasingly critical and widely utilized for design verification and manufacturing development. In order to characterize the impact of patterns on polishing, such models often require the extraction of graphic parameters. However, existing extraction algorithms provide a limited description of the interaction effect between layout patterns. To address this problem, we calculate the average density as a density correction and innovatively use a one-dimensional line contact deformation profile as a weighting function. To verify our hypothesis, the density correction method is applied to a density step-height-based high-K metal gate-CMP prediction model. The surface prediction results before and after optimization are compared with the silicon data. The results show a reduction in mean squared error (MSE) of 40.1% and 35.2% in oxide and Al height predictions, respectively, compared with the preoptimization results, confirming that the optimization method can improve the prediction accuracy of the model.

Smart Circuit Design Machine Learning-Driven Optimization for Enhanced Performance in Electronics and Computer Engineering.

In the realm of Electronics and Computer engineering, achieving optimal performance of circuits amidst escalating complexity poses significant challenges. Traditional manual optimization techniques are often inadequate to navigate the intricacies of modern electronic systems. This paper advocates for the adoption of machine learning-driven optimization as a transformative approach to smart circuit design. By leveraging machine learning algorithms, engineers can systematically explore the expansive design space, discern complex relationships between circuit parameters and performance metrics, and ultimately enhance the efficiency and effectiveness of electronic circuits. This paper comprehensively reviews the application of machine learning techniques in circuit design optimization. Supervised learning algorithms such as neural networks, support vector machines, and decision trees enable the modeling of intricate interdependencies within electronic circuits. Unsupervised learning techniques, including clustering and dimensionality reduction, facilitate efficient exploration of the design landscape by identifying patterns and correlations. Additionally, reinforcement learning algorithms offer an autonomous approach to circuit optimization through iterative learning and refinement. Real-world applications of machine learning-driven optimization in electronics and computer engineering span various domains, including power-efficient integrated circuits, signal processing algorithm optimization, and layout optimization for enhanced performance and reliability. Moreover, machine learning techniques play a crucial role in mitigating variability in semiconductor manufacturing processes, ensuring robustness and reliability of electronic systems in the face of uncertainties. Despite the promising potential of machine learning in circuit design optimization, challenges such as dataset acquisition, model interpretability, and scalability to complex circuits persist. Addressing these challenges requires innovative research endeavors, including the development of hybrid optimization techniques and novel hardware architectures. DOI: https://doi.org/10.52783/tjjpt.v45.i02.6339

Design of Capacitive Power Transfer System with Small Coupling Capacitance for Wireless Power Transfer

Wireless power transfer systems play an important role in the application of modern power supply technology. Wireless charging has been widely used in portable devices such as smartphones, laptops, and even some medical devices. Higher system efficiency can be achieved while reducing costs. This article describes the design of a capacitive power transfer (CPT) system using the Class-E amplifier method. When the capacitance of the coupling plate is small, the operation of Class-E amplifiers under Zero-Voltage-Switching (ZVS) conditions is very sensitive to their circuit parameters. By adding an additional capacitor to the Class-E amplifier, the coupling capacitance can be increased, resulting in better circuit performance. The high efficiency of the Class-E amplifier is verified by simulation and experimental results.

Characteristics Analysis of IGZO TFT and Logic Unit in the Temperature Range of 8–475 K

The effect of high- and low-temperature conditions on the performance of IGZO TFT and logic circuits were investigated in this work. In the temperature range of 250−350 K, the performance of the IGZO TFT did not show significant changes and exhibited a certain degree of high- and low-temperature resistance. When the temperature was below 250 K, as the temperature decreased, the threshold voltage (VTH) of the IGZO TFT significantly increased, the field effect mobility (μFE) and the on state current (ION) significantly decreased. This is attributed to the lower excitation degree of charge carriers at extremely low temperatures, resulting in fewer charge carriers transitioning to the conduction or valence bands, and the formation of defects also limits carrier migration. When the temperature exceeded 350 K, as the temperature increased, more electrons could escape from the bandgap trap state and become free charge carriers, and the IGZO layer was thermally excited to produce more oxygen vacancies, resulting in higher μFE and lower VTH. In addition, the drain current noise spectral density of IGZO TFT conformed to the 1/ƒ noise characteristic, and the degradation mechanism of IGZO TFT over a wide temperature range was confirmed based on the changes in noise spectral density at different temperatures. In addition, an inverter logic unit circuit was designed based on IGZO TFT, and the performance changes over a wide temperature range were analyzed. This lays the foundation for IGZO TFT to be applied in integrated circuits with harsh environments.

Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design

CNTFETs are a shows potential choice for traditional CMOS technology due to their potential for lesser power consumption and superior performance. In the present paper, a new 1-bit hybrid full adder has been deliberated and proposed using both pass transistor (PT) and transmission gate logics (TGL), which utilizes a total of 16 transistors. The combination of PT and TGL can lead to improved power efficiency, reduced delay, and enhanced circuit performance in various VLSI applications. For 0.9 V supply voltage at 32-nm CNTFET technology, the power consumption is 0.0748 μW, which is to be an exceptionally low value with a lesser delay of 7.586 Ps and the power-delay-product (PDP) of 0.5674 aJ. The results obtained from this analysis demonstrate the power efficiency, speed, and overall performance of the proposed full adder design. The combination of 32-nm CNTFET technology, deliberate circuit design choices, and the use of specific logic elements (CMOS inverters and strong transmission gates) contributes to the reported characteristics. Using a 0.9 V supply voltage and 32-nm Stanford CNTFET Model technology, the suggested 1-bit adder circuit's concert was investigated using the Mentor Graphics Tool. Finally, using the proposed 1-bit full adder circuit, an N-bit ripple carry adder (N=8, 16 & 32) is implemented and demonstrated. The Simulation results of the 8-bit RCA with a power consumption of 0.373 μW, the delay is 16.852 Ps and the PDP is 6.2857 aJ. These results show that proposed RCA’s have better performance compared to the already reported designs in terms of performance, speed, and power economy.

A novel nanosheet reconfigurable field effect transistor with dual-doped source/drain

—In this paper, a reconfigurable field-effect transistor (RFET) with dual-doped nanosheet architecture and triple independent gates is proposed and studied with the numerical simulations. The proposed RFET can behave as either an n/p-type MOSFET or an n/p-type tunneling-FET (TFET) according to different program biases. A comprehensive study is carried out on the device mechanism and the influence of key device parameters. Various metrics, such as the on-state current (ION), off-state current (IOFF), ION/IOFF, threshold voltage (VT) and sub-threshold swing (SS), are used to evaluate the proposed RFET. This RFET combining the advantages of the conventional MOSFETs (High ION and operation speed) and the new emerging TFETs (Low IOFF, sub-threshold swing and power dissipation) could make the circuit design more flexible and high efficiency, and improve the circuit performance.

Small-Scale Power Plants Based on Organic Rankine cycle (ORC) using Low-Boiling Fluorocarbon Working Fluids when Operating at High Initial Cycle Conditions

The purpose of the work is to develop and analyze the operation of a thermal circuit based on the organic Rankine cycle (ORC) using low-boiling working substances of the fluorocarbon class when operating at high initial cycle parameters. This goal is achieved by energy analysis of single- and multi-stage thermal circuits of power plants with a turbine circuit operating on low-boiling fluorocarbon work-ing substances, such as octafluoropropane C3F8 and decafluorobutane C4F10. It is proposed to integrate the ORC thermal circuit as an extension to a small-capacity gas turbine power plant (GTU), operating on synthesis gas after a biomass gasifier. The most important results of the work are the possibility of implementing a cycle with a low condensation temperature of the medium, which allows, when using low-boiling working fluids, to significantly reduce the temperature of the heat removal process and, consequently, increase the efficiency of the cycle. The possibility of using the listed working substances in power plants with a turbine circuit, which until now have been used mainly as refrigerants for refrig-eration and heat pump systems, has been shown. The significance of the results of the work lies in the fact that, based on the analysis of the energy complex, a circuit solution has been proposed and justified that can increase the energy efficiency of the power supply complex, increasing the volume of generated electrical power and providing a number of technological and environmental advantages.

Real time performance assessment of utility grid interfaced solar photovoltaic plant

Continuous monitoring of large-scale solar photovoltaic (PV) installations is necessary to check the deterioration and monitor the performance of the PV plant. Fault diagnosis is crucial to ensure the PV plant operates safely and reliably. This paper presents a diagnosis methodology based on current-voltage (I-V) and PV characteristics to monitor and assess the behavior of solar PV. In this paper, I-V curve characterization using an I-V curve tracer is used to check the deterioration and diagnosis of the PV panels. The real-time performance of the 50.4 kWp rooftop solar grid interfaced PV plant is investigated and analyzed using I-V and PV curve tracers in real-time conditions. The overall performance of solar PV is assessed on a real-time test system in different scenarios such as variable climatic conditions, partial shading conditions, aging of solar panels, short circuit conditions, and dust decomposition. Furthermore, the performance assessment of solar PV is evaluated using performance indicators such as open circuit voltage index, short circuit current index, fill factor, and performance ratio.

Control of Carbon Dioxide Bivalent Heat Pump on Heating of Buildings

The scheme of a bivalent heat pump (BHP) is considered, using both the heat of the water from the return network and the heat of the outside air as low-potential heat sources (LPH). The aim of the work is to create a BHP circuit that provides functioning at the variable heat load temperature. The goal was achieved by solving the following problems: analysis of methods of synthesis of BHP circuits, analysis of circuit operation under random disturbances and development of the automatic control systems for BHP. The most significant result of the work is: a heat pump circuit that can operate at variable pressures of the evaporator and the gas cooler. The next significant result is, for bivalent heat pumps intended for operation in heat supply systems with qualitative and qualitative-quantitative laws of thermal control, the introduction into the heat pump circuit of a heat exchanger installed in the return water circuit of the secondary building and cooled by outside air, as well as two control valves installed in series between the gas cooler and the evaporator, the first valve installed along the refrigerant flow being controlled by a signal based on the pressure difference between the outlet of the gas cooler and the separation vessel between the evaporator and the gas cooler, and the second by pressure in front of the evaporator. The significance of the obtained results lies in the increase of the COP of the heat pump, due to the increase of heat transfer in the gas cooler circuit. The HHP circuit differs from the known ones in that it uses two control valves and the heat exchanger for additional cooling of the return water of the BHP heated building.

Controllable and reusable seesaw circuit based on nicking endonucleases

Seesaw circuits are essential for molecular computing and biosensing. However, a notable limitation of seesaw circuits lies in the irreversible depletion of components, precluding the attainment of system recovery and rendering nucleic acid circuits non-reusable. We developed a brand-new method for creating controllable and reusable seesaw circuits. By using the nicking endonucleases Nt.BbvCI and Nt.Alwi, we removed “functional components” while keeping the “skeletal components” for recurrent usage. T-inputs were introduced, increasing the signal-to-noise ratio of AND logic from 2.68 to 11.33 and demonstrating compatibility. We identified the logic switching feature and verified that it does not impair circuit performance. We also built intricate logic circuits, such as OR-AND gate, to demonstrate the versatility of our methodology. This controllable reusability extends the applications of nanotechnology and bioengineering, enhancing the practicality and efficiency of these circuits across various domains.

Analysis and Simulation of Current Balancer Circuit for Phase-Gain Correction of Unbalanced Differential Signals

The phase and gain imbalance of a balun output can be adjusted by a differential current balancer (DCB) circuit. The performance of DCB circuit, for correcting the phase (gain) imbalance, is analyzed for a wide range of input signal level, and the accuracy is verified with circuit simulation. To illustrate the phase-error/gain-error (PE/GE) correction, a 30–40[Formula: see text]GHz DCB circuit is designed and simulated in a 180-nm CMOS process. The DCB is examined for input PE, [Formula: see text], of [Formula: see text] and input GE, GA, of [Formula: see text][Formula: see text]dB. Analysis and simulation illustrate an output phase error [Formula: see text] of [Formula: see text] and output gain error [Formula: see text] of [Formula: see text][Formula: see text]dB, over frequency range of 20–50[Formula: see text]GHz. The results of DCB circuit for PE (GE) compensation are compared to that of phase-correction technique (PCT) circuit, illustrating the superior phase (gain) imbalance correction of the DCB circuit with lower NF and DC power consumption.