Circuit Layout Research Articles

A Research of the Integrated Circuit Design and Optimization

With the scientific and technical revolution going on, integrated circuit has been playing a vital role in our daily life ever since. In IC (Integrated circuit) design and manufacturing, layout of the integrated circuit determines its success or failure. However, the constantly decreasing characteristic size and progressive process bring about some new issues. That is why in post-Moore’s Law period, the design and optimization of layouts deserves attention of the whole industry. A properly designed and optimized layout not only results in better performance while using, but also cut out the cost of manufacture. In this paper, the methodology of integrated circuit layout design and optimization are discussed. For design, the author presented the whole flow of how the layout is generated and principles in integrated circuit design. For optimization, two approaches are analyzed. One is shorting out the critical area. Based on critical area theory and methodology of image processing, layouts can be improved in configuration. The method discussed here makes a modification on the previous way to make the optimization more accurate and efficient. The other method is inserting auxiliary polysilicon, which can counteract the impact of channel length change of MOSFETs and focus error as a unavoidable result of the process improvement.

Geometrically asymmetric pressure sensor with precious few electrodes achieves precise detection of both position and strength by machine learning

Wearable devices that can accurately detect the position and strength of applied pressure have been a focus of attention in the field of flexible tactile sensing. However, conventional sensor arrays with multiple units have many challenges in practical applications due to their complex circuit layouts and poor robustness, etc., which could be solved by minimizing the number of connecting electrodes among each unit. Herein, a pressure sensor with geometrically asymmetric structure has been proposed to remove all the connected inner electrodes. The sensor is constructed by three pieces of fabrics, with one insulating fabric sandwiched by two conductive fabrics coated with carbon nanotubes. Notably, the bottom fabric is specially designed in an optimized asymmetric shape with a rectangular hole located off-center of the square, assisting the sensor to generate different resistive and capacitive responses among pre-divided nine areas through only three external electrodes. Compared to conventional resistive sensor arrays, the number of electrodes is reduced by 83.3 %. With the assistance of machine learning, pressure-positioning with an accuracy of more than 98.1 % and precise strength measurements are achieved. Based on this sensor and the trained neural network, a two-level password system is constructed for more reliable role recognition. The asymmetric strategy proposed in this work provides a novel design for realizing precise detection of both position and strength using extremely simplified circuits, which has great potential in the field of wearable electronics.

An analog switch circuit structure suitable for low-distortion transmission

Abstract A MOSFET analog switch circuit structure suitable for low-distortion bidirectional signal transmission is proposed. By introducing a “threshold voltage matching MOSFET” into the MOSFET switch driver circuit structure, the driving voltage corrected by the threshold voltage is generated by the driving circuit, eliminating the problem of poor conduction on-resistance flatness in traditional analog switch circuit structure due to MOSFET second-order effects and non-constant overdrive voltage. The circuit completed schematic and layout design based on the 0.13 μm BCD process. Simulation results show that the switch has bidirectional transmission capability, with a typical on-resistance value of 115 Ω. It achieves less than 5% on-resistance non-flatness under resistive loads ranging from 500 Ω to 1 KΩ, which is more than 50% improvement compared to traditional analog switch structures. Moreover, the on-resistance flatness is insensitive to changes in load and temperature.

The application of deep learning technology in integrated circuit design

This study addresses the intricate challenge of circuit layout optimization central to integrated circuit (IC) design, where the primary goals involve attaining an optimal balance among power consumption, performance metrics, and chip area (collectively known as PPA optimization). The complexity of this task, evolving into a multidimensional problem under multiple constraints, necessitates the exploration of advanced methodologies. In response to these challenges, our research introduces deep learning technology as an innovative strategy to revolutionize circuit layout optimization. Specifically, we employ Convolutional Neural Networks (CNNs) in developing an optimized layout strategy, a performance prediction model, and a system for fault detection and real-time monitoring. These methodologies leverage the capacity of deep learning models to learn from high-dimensional data representations and handle multiple constraints effectively. Extensive case studies and rigorous experimental validations demonstrate the efficacy of our proposed deep learning-driven approaches. The results highlight significant enhancements in optimization efficiency, with an average power consumption reduction of 120% and latency decrease by 1.5%. Furthermore, the predictive capabilities are markedly improved, evidenced by a reduction in the average absolute error for power predictions to 3%. Comparative analyses conclusively illustrate the superiority of deep learning methodologies over conventional techniques across several dimensions. Our findings underscore the potential of deep learning in achieving higher accuracy in predictions, demonstrating stronger generalization abilities, facilitating superior design quality, and ultimately enhancing user satisfaction. These advancements not only validate the applicability of deep learning in IC design optimization but also pave the way for future advancements in addressing the multidimensional challenges inherent to circuit layout optimization.

Analysis of Electrothermal Imbalance of Hard-Switched Parallel SiC MOSFETs through Infrared Thermography

This paper provides an experimental investigation through infrared thermography of the steady-state temperature imbalance arising in parallel SiC MOSFETs. A switched-mode boost power converter based on two arrays of 4 parallel 1.2 kV MOSFETs is selected as a case-study. The analysis aims at proving that a proper device arrangement can minimize the thermal imbalance in the absence of circuit layout optimization.

A hybrid quantum-classical classification model based on branching multi-scale entanglement renormalization ansatz

Tensor networks are emerging architectures for implementing quantum classification models. The branching multi-scale entanglement renormalization ansatz (BMERA) is a tensor network known for its enhanced entanglement properties. This paper introduces a hybrid quantum-classical classification model based on BMERA and explores the correlation between circuit layout, expressiveness, and classification accuracy. Additionally, we present an autodifferentiation method for computing the cost function gradient, which serves as a viable option for other hybrid quantum-classical models. Through numerical experiments, we demonstrate the accuracy and robustness of our classification model in tasks such as image recognition and cluster excitation discrimination, offering a novel approach for designing quantum classification models.

A low-voltage, high-performing CMOS transistor based on multiple- output operation transconductance amplifier for current mode KHN Universal filter applications

This study proposes a current-mode KHN universal filter design that can perform three standard functions simultaneously: low-pass, high-pass, and band-pass. The circuit is built around a multiple-output operation transconductance amplifier (MO-OTA), which allows for electronically adjustable pole frequency and quality factor by modifying input bias currents (IB). The circuit layout is straightforward, with two MO-OTAs and two grounded capacitors, eliminating the need for external resistors and depending entirely on grounded components. Because of its simplicity, the circuit is suited for use in a tiny, efficient design. The proposed circuit's operation was validated using LT-Spice simulations, and the results were in line with theoretical expectations. The circuit used around 298μW of power at ±0.2V power supply voltages. These results demonstrate the circuit's potential for low-power applications, which are crucial in many modern electronic devices. The suggested current-mode KHN universal filter offers a viable option for combining various filter functions in a single circuit with customizable parameters. Its simplicity, efficiency, and performance qualities make it a feasible choice for incorporation into a variety of electronic systems, allowing for more filter design freedom.

PLANARITY AND ITS APPLICATIONS: INVESTIGATING THE BOUNDARIES OF GRAPH EMBEDDINGS

Graph theory plays a critical role in numerous applications, particularly in understanding and analyzing the structural properties of networks. This paper focuses on the concept of planarity in graph theory, exploring how certain graphs can be embedded in a plane without edge crossings. The study investigates the criteria that determine graph planarity, including Kuratowski's and Wagner's theorems, and examines the implications of these concepts in various fields such as network design, circuit layout, and geography. Additionally, the paper delves into advanced techniques for testing planarity and embedding graphs in surfaces with higher genus, thus pushing the boundaries of how graph embeddings can be utilized in both theoretical and practical contexts. Through an in-depth analysis of graph embedding algorithms, real-world applications are discussed to highlight the importance of planarity in optimizing spatial layouts and reducing complexity in network structures. The results of this research demonstrate the vast potential of planar graphs in solving complex problems efficiently.

Investigating Dynamic Behavior in SAG Mill Pebble Recycling Circuits: A Simulation Approach

The dynamics of milling circuits, particularly those involving Semi-Autogenous Grinding (SAG) mills, are not adequately studied, despite their critical importance in mineral processing. This paper aims to investigate the dynamic behavior of an SAG mill pebble recycling circuit under varying feed ore conditions, focusing on both uncontrollable parameters (such as ore hardness) and controllable parameters (including circuit layout and pebble crusher configurations). The study is carried out with Simulink dynamic simulations. Our findings reveal several key insights. Firstly, plant designs based solely on static simulations may not be adequate for large or complex circuits, as they fail to account for the dynamic nature of milling processes. Second, incorporating stockpiles after pebble crushing can effectively mitigate the impact of dynamic fluctuations, leading to more stable circuit performance. Third, different circuit layouts can facilitate easier maintenance and operational flexibility. Notably, finer pebble crushing can enhance circuit throughput by 5% to 10%.

Matching constraint extraction for analog integrated circuits layout via edge classify

Achieving matching constraints between various components is important in analog integrated circuit (IC) layout design, as it can reduce the impact of layout parasitics on the performance of IC. When automating analog integrated circuit layout design, identifying accurate matching constraints is an essential step before placement and routing. The matching relationship between devices strongly depends on circuit's topology and design expertise. This work focuses on differential circuits with various topologies and proposes a supervised learning framework that incorporates symmetry analysis. The heterogeneous multi-relationship graph representation is proposed to capture circuit's topology and extract matching constraints. Additionally, a symmetry analysis algorithm and filtering method based on matching levels are investigated to enhance the model's performance. The experimental results demonstrate that this work maintains a low false alarm rate and outperforms other matching constraint detection algorithms in terms of F1 score and accuracy.

Gate driver, snubber and circuit design considerations for fast‐switching series‐connected SiC MOSFETs

AbstractSeries connection of Silicon Carbide (SiC) Metal‐Oxide‐Semiconductor Field‐Effect Transistors (MOSFETs) is an interesting solution to design switches for voltages that are not yet commercially available or limited for single‐die devices. However, inherent static and dynamic voltage balancing must be achieved. Voltage imbalance is caused by the device parameters spread, whose impact is pronounced in low‐inductive circuit layouts. This study investigates the optimal design and tuning limits of resistor‐capacitor (RC)‐snubber circuits and non‐adaptive, standard, voltage‐source gate drivers for achieving the best balancing in transient and steady‐state voltage distributions among series‐connected discrete SiC MOSFETs operating at speeds up to . It has been shown that a larger parameter mismatch will lead to uneven switching energy losses and larger voltage imbalances. It was also experimentally shown that increasing the gate resistor to slow down the devices will not always improve balancing when their parameter spread is large. Thus, tuning recommendations for the RC‐snubber circuit and gate driver were developed based on these findings.

Millimeter-Wave GaN High-Power Amplifier MMIC Design Guideline Considering a Source via Effect

A millimeter-wave (mmWave) gallium nitride (GaN) high-power amplifier (HPA) monolithic microwave-integrated circuit (MMIC) was implemented, considering a source via effect. In this paper, we introduce guidelines for designing GaN HPA MMICs, from device sizing to meeting high-power specifications, power matching considering source via effects, schematic design of three-stage amplifier structures, and electromagnetic (EM) simulation. Based on the results of load pull simulation and small-signal maximum stable gain (MSG) simulation, the GaN high-electron-mobility transistor (HEMT) size was selected to be 8 × 70 μm. However, since the source via model provided by the foundry was significantly different from the EM results, it was necessary to readjust the power matching considering this. Additionally, when selecting the source via size, the larger the size, the easier the matching, but since the layout of the peripheral bias circuit is not possible, a compromise was required considering the actual layout. To prevent in-band oscillation, an RC parallel circuit was added to the input matching circuit, and low-frequency oscillation was solved by adding a gate resistor on the PCB module. The proposed PA was fabricated with a commercial 0.1 μm GaN HEMT MMIC process. It exhibited 38.56 to 39.71 dBm output power (Pout), 14.2 to 16.7 dB linear gain, and 14.1% to 18.2% power-added efficiency (PAE) in the upper Ka band. The fabricated GaN power amplifier MMIC shows competitive Pout in the upper Ka band above 33 GHz.

Standard cell library design for edge computing chips

Abstract With the rapid development of big data, IoT, and other technologies, edge computing has emerged, and the core of edge computing is the edge computing chip. To meet the rapidly growing data computing speed and data computing volume and taking into account the short design cycle and low cost, this paper proposes a standard cell library for designing edge computing chips based on the PDK of 0.13 μm SOI process. Compared with the existing edge computing chips that operate at 100 MHz, the edge computing chip designed with this cell library can operate at 1 GHz. The design process includes selecting cell types and heights for the cell library, designing and drawing circuit logic and layout, extracting characteristic parameters of the cell library, and verifying the cell functions. The validation results show the designed cell can operate at 1 GHz with low delay. Compared with a commercial device, the designed device has a higher operating frequency and realizes a good balance between area and power consumption, and the standard cell library has a good application prospect.

Bioinspired Quantum Oracle Circuits for Biomolecular Solutions of the Maximum Cut Problem.

Given an undirected, unweighted graph with n vertices and m edges, the maximum cut problem is to find a partition of the n vertices into disjoint subsets V1 and V2 such that the number of edges between them is as large as possible. Classically, it is an NP-complete problem, which has potential applications ranging from circuit layout design, statistical physics, computer vision, machine learning and network science to clustering. In this paper, we propose a biomolecular and a quantum algorithm to solve the maximum cut problem for any graph G. The quantum algorithm is inspired by the biomolecular algorithm and has a quadratic speedup over its classical counterparts, where the temporal and spatial complexities are reduced to, respectively, [Formula: see text] and [Formula: see text]. With respect to oracle-related quantum algorithms for NP-complete problems, we identify our algorithm as optimal. Furthermore, to justify the feasibility of the proposed algorithm, we successfully solve a typical maximum cut problem for a graph with three vertices and two edges by carrying out experiments on IBM's quantum simulator.

Research on Fixed-Slope On-Chip Soft-Start Method Applied to Buck DC–DC Converter

A fixed-slope soft-start method applicable to Buck converters for on-chip integration is proposed to address the issue of varying power stresses (device voltage, current stress) during start-up with different output voltages. The main mechanism involves combining feedback coefficient sampling with a fixed-slope reference voltage to achieve a slow rise in the reference voltage by equating the soft-start charging current to a pulse current through the on-chip integration of a small capacitor. This allows for fixed-slope start-ups for different set output voltages. Spike elimination techniques are employed to address charging current spikes caused by pulse periods, enhancing precise control over the soft-start time. By replacing the traditional resistor divider network with a capacitive divider network in the soft-start method, DC power consumption is minimized. Upon completion of the soft start, a smooth transition to a steady-state operation occurs, with the automatic shutdown of the soft-start module reducing static power consumption. A specific circuit design and layout verification based on 0.18 μm high-voltage BCD technology demonstrates that the proposed method maintains a fixed-slope start-up of approximately 5 mV/μs within the chip’s output range of 0.9 V to 4 V, with a slope control accuracy of up to 98%. The soft-start circuit effectively eliminates surge currents generated during start-up under full load conditions of 3 A and no-load conditions of 0 A, reducing the overall surge current by 44% and enabling a stable voltage rise and the smooth transition to a steady-state operation.

Analysis of the parasitic capacitance effects on the layout of latch-based sense amplifiers for improving SRAM performance

Static random-access memory (SRAM) technology is utilized in designing cache memory to enhance the processing performance of computer systems. The sense amplifier (SA) circuit, a crucial component of memory design, significantly impacts data access time and power consumption. In comparison to conventional differential sense amplifiers (DSA) designs, latch-based sense amplifiers (LSA) used in memory-based computing platforms have specific requirements, including robust noise resistance in harsh working environments and low power consumption, particularly for internet of thing (IoT) embedded computing applications. However, the performance can be degraded due to various factors that arise during the layout, such as conductor resistance or the development of parasitic capacitance. Therefore, this study employs low-voltage 22 nm UMC CMOS technology for LSA design layout and analyzes the factors influencing design performance post-layout process. Layout design optimization techniques are applied to mitigate the impact of parasitic capacitance on important signal lines such as data line/data line bar (DLL/DLLB). Based on the performance analysis results, it is possible to achieve a reduction in power consumption of up to 15% and a 5% decrease in read delay time by implementing circuit layout LSA design optimization techniques.

Parasitic-Based Model for Characterizing False Turn-On and Switching-Based Voltage Oscillation in Hybrid T-Type Converter

High frequency and high voltage switching converters utilizing wide bandgap semiconductors are gaining popularity thanks to their compactness and improved efficiency. However, the faster switching requirements gives rise to new challenges. A key issue is the increased oscillation of the drain–source voltage caused by the switching action of the complementary switch in the same phase or change of state of the other phase switches. The voltage stress caused by these oscillations can damage the switch. Furthermore, the high dv/dt during turning-on of one switch might result in false turn-on of the complementary switch due to the miller effect. In this paper, these issues are investigated in a T-type converter through analytical and experimental analysis. Based on the proposed analytical approach, simple and cost-wise solutions utilizing an optimum design of gate driver circuits and circuit layout modifications can be developed to cope with the aforementioned issues. A comprehensive analytical model of the converter with consideration of parasitic capacitances and inductances is developed. By performing sensitivity analysis on the model, the effect of the parasitic parameters on the drain–source voltage oscillation and gate–source voltage amplitude in case of false turn-on is studied. The validity of the model is then assessed through numerical simulations and experimental results.

A low crosstalk 768-channel of 14-bit analog to digital converters for high resolution array of detectors

This paper presents the design and measurement results of a 768-channel of a 14-bit analog to digital converters. Each sampling channel is equivalent to a pitch of only 8.5 μm with a possible sampling rate from 40 KS/s up to 100 KS/s. Test results show crosstalk of just +/-1 LSB. The circuit architecture and layout structure make it scalable to an exceptionally large format of detectors beyond 1000 channels. The circuit is designed to be used as a side element for multi-channel readout systems or as an IP for transfer to very dense integrated circuits.

Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips

The Long-term reliability of a chip, encompassing factors like bias temperature instability (BTI), plays a substantial role in the chip's operational efficiency and overall lifespan. Most studies primarily center around performance-related aspects like delay and timing impacts, and fewer studies are performed on reliability impacts on the spatial power density and thermal profiles of the chips. In this study, we propose to investigate the BTI impacts on the spatial power density and temperature profiles of VLSI chips for the first time. We assessed the BTI aging impact on the on-chip spatial power density and temperature for two widely used circuit functional blocks (dual port RAM, Discrete Cosine Transform (DCT) block) at T = 130◦C and T = 25◦C to account for the worst-case BTI degradation, using degradation-aware cell libraries for a 10-year aging scenario. Furthermore, we showcased the essential role of BTI aging-aware timing analysis in evaluating the impact of BTI aging on total power, on-chip spatial power density, and thermal maps. Neglecting this aspect can result in a substantial underestimation of the results related to the parameters mentioned above. We developed a power map generation method from the circuit layout and power analysis from EDA tools. We demonstrate that both circuits’ maximum power density reduction is approximately 12 % and 20 %, respectively. Furthermore, to analyze the BTI impact on spatial temperature, we built the heat transfer model using a multiphysics tool to imitate a real chip (Intel i7-8650U) and performed thermal simulations to evaluate the spatial thermal map. The resulting maximum temperature reduction for both these circuits is approximately 10 % and 12 %, respectively, which is quite significant.Our analysis has further unveiled that, in the context of a specific circuit, the position of maximum power density and the occurrence of a hot spot remains consistent over time, unaffected by aging. However, it's important to note that these positions can vary between different circuits, primarily influenced by the workload the circuit is currently handling. Furthermore, our findings demonstrate that the effects of Bias Temperature Instability (BTI) aging are significantly more pronounced when the circuit operates at higher temperatures (T = 130◦C) compared to lower operating temperatures (T = 25◦C).

Development and Validation of a Novel Zero-Dimensional Heat Rejection Model for High-Efficiency Engines

In recent years, the trend towards the performance maximization of modern internal combustion engines has led to the creation of accurate simulation models to optimize the engine design and operating conditions. Temperature management is crucial to achieve the performance goals of an internal combustion engine without affecting the component’s reliability. Formula 1 mandates that only a limited number of experimental tests can be performed, which leads to the necessity of simulators capable of substituting empirical tests. Furthermore, the requirement of adapting the vehicle setup before each race weekend to maximize the performance on each circuit layout necessitates short computational time. To address this, the development of a zero-dimensional model of the thermal flows within an engine is presented in this paper. This model allows to precisely compute the dynamic variations of all the heat flows inside the combustion engine, excluding only the radiative ones and the engine components’ temperatures. The new simulation approach has been developed and validated on a Formula 1 engine and shown to be precise and fast. The results demonstrate the value of the proposed model with an average engine fluid temperature error of less than 1 °C for a computational cost comparable with on-board applications.