Test Circuit Research Articles

Real-Time DC Series Arc Fault Detection Based on Noise Pattern Analysis in Photovoltaic System

This paper presents a method for detecting series arc faults based on noise pattern analysis in photovoltaic systems. The arc detection circuit is required to detect the series arc quickly and not falsely detect the system noise as arc noise. This paper proposes noise pattern analysis to distinguish between system noise and arc noise and prevent false detection. First, periodic feature analysis prevents false detection by periodic noise, such as inverter noise, using the difference in periodic characteristics. Second, zero-range density analysis detects series arc noise using the difference in fluctuation characteristics. An integrated arc fault detection algorithm comprising discrete wavelet transform decomposition, periodic feature analysis, zero-range density, and an iterative loop algorithm is developed. The proposed methods are verified using noise distinction experiments, wherein the injected signal and arc noise are distinguished with high classification precision using the proposed noise pattern analysis method. The developed arc detection algorithm is applied to a real-time series arc detection board based on the TMS320F28335 DSP, and the performance of the series arc detection and false detection prevention is verified using the UL1699B arc detection test circuit and a real PV system.

Arduino based 74-series integrated circuits testing system at gate level

<span lang="EN-US">The goal of this research article is to build and implement a low-cost, user-friendly 74-series logic integrated circuits (ICs) tester that is independent of a computer. Depending on the truth table of the gates and the IC configuration, the logic IC tester will be able to test the operation of the 74 series logic gates (AND, OR, NOR, NAND, XOR) of those ICs. It is feasible to test a range of logic ICs with higher pin widths thanks to the proposed system’s usage of an Arduino Mega platform module as a microcontroller, which provides the ability to connect 54 programmed logic inputs or outputs. The versatility offered by this design and the use of a personal computer allow for the reprograming and updating of the logic IC functional tester. Any 74-series ICs testing outcome will be shown on liquid crystal display (LCD) at the gate level. The logic IC functional tester was successfully constructed and operates flawlessly.</span>

Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration Circuits.

Hafnium-based ferroelectric memories are a promising approach to enhancing integrated circuit performance, offering advantages such as miniaturization, compatibility with CMOS technology, fast read and write speeds, non-volatility, and low power consumption. However, FeRAM (Ferroelectric Random Access Memory) still faces challenges related to endurance and retention susceptibility to process variations. Hence, testing and obtaining the core parameters of ferroelectric capacitors continuously is essential to investigate these phenomena and explore the potential solution. The traditional method for measuring ferroelectric capacitors has limitations in timing generation capability, introduces parasitic capacitance, and lacks accuracy for small-area capacitors. In this study, we analyzed the working principle of ferroelectric capacitors and designed a method to detect the remnant polarization, saturation polarization, and imprint offset of ferroelectric capacitors. Further, we further proposed a circuit implementation method. The proposed test circuit conquers these limitations and enables high-precision testing of ferroelectric capacitors, contributing to developing hafnium-based ferroelectric memories. The circuit includes a flip-readout circuit, a capacitance calibration circuit, and a voltage-to-time converter and time-to-digital converter (VTC&TDC) readout circuit. According to simulation results, the capacitance calibration circuit reduces the deviation of the capacitance by 84%, and the accuracy of the readout circuit is 5.91 bits, with a readout time of 150 ns and a power consumption of 1 mW. This circuit enables low-cost acquisition of array-level small-area ferroelectric capacitance data, which can guide subsequent device optimization and circuit design.

Associations between immune competence phenotype and stress response in sheep

Immune competence in domestic sheep is gaining more attention in genetic selection programs that seek to enhance flock immunity and animal welfare. A goal of many programs is to identify behavioral phenotypes that indicate stress-coping strength, as well as disease resilience. The current study set out to explore the relationship between immune responsiveness, physiological stress, and behavioral response among sheep that had been selected for ‘low’ (LR) or ‘high’ (HR) response to cell-mediated and antibody-mediate reactivity to a clostridial vaccine. Multiparous ewes were placed in four experiments which exposed the animals to various threats including, dog presence, human proximity, visual isolation from flock, and physical restraint. To evaluate the consistency of behavioral phenotypes, all ewes were placed in the test circuit one year later. Basal body temperature (via iButton) and serum cortisol concentrations were collected prior to and after the circuit each year. Immune group (HR vs. LR) was not found to be related to behavioral performance during the dog, human, isolation, or restraint challenge. Immune group categorization was also unrelated to pre- and post-cortisol concentrations, and the change in cortisol concentrations during testing. There was a negative relationship identified between response to visual isolation and change in cortisol response during testing, indicating that sheep which were more active or agitated during visual isolation from the flock experienced less of an increase in serum cortisol levels and were perhaps experiencing a negative, high arousal state compared to less reactive sheep (e.g., freeze behavior) (χ2(4, N=99) = 42.72, P <0.0001). There was also a post hoc, positive relationship identified between weight measurements and immune group, such that individuals with greater body weight were more likely to be in the high immune responsiveness group (P= 0.01). Specifically, for every unit increase in weight, there was a ~49% chance of being categorized in the HR group. This is relevant for selection programs because producers that seek to enhance immune responsiveness and performance may be able to select sheep that carry a greater body mass, and while not found in the present study, could lead to greater flock immunity.

Low Inductive Characterization of Fast-Switching SiC MOSFETs and Active Gate Driver Units

Accurate switching device characterization is necessary for effectively utilizing the technological ad-vantages of Silicon Carbide (SiC) Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) over their Silicon (Si) Insulated-Gate Bipolar Transistor (IGBT) counterparts. With switching times of few nanoseconds, the unprecedented switching speed of SiC semiconductor devices challenges today's converter and characterization setup designs in regard to parasitic layout inductances for optimal conversion and reliable characterization data. Fur-thermore, active gate driving is a key to unlock the potential of SiC MOSFETs, but requires performance assessment prior to integration. This paper presents a low-inductive test platform for flexible and high-accuracy characterization of fast-switching SiC MOSFETs and active gate drivers evalu-ation. The test circuit delivers high quality characterization data that is comparable with a commercial dynamic power device characterizer. In addition to the conventional hard-switching double-pulse tests with a two-level voltage source gate driver, the test circuit offers soft-switching and gate driver evaluation capability in addition. This test platform is a valuable tool for obtaining reliable characterization data to develop more accurate SiC MOSFET simulation models, and evaluate the combination of gate driver and MOSFET prior to the prototyping phase of a converter.

Simulation And Design of a Vertical Gallium Nitride JFET with Dual Lateral Heterojunction Channels

A novel vertical gallium nitride (GaN) junction field-effect transistor (JFET) is reported in this article. Through the setup of dual lateral heterojunction channels in the body, the current density is high while the p-type gallium nitride growth area can be adjusted to easily achieve enhanced mode. Based on the structure parameter settings in this article, through the device simulation software TCAD, and under the condition of selecting the appropriate p-type GaN growth region, the threshold voltage of the device is 1.1 V, the source output current density can reach 7.2 kA/cm2, the breakdown voltage is about 750 V, and the on-resistance is 0.52 mΩ·cm2. Finally, the test circuit is built, and the switching characteristics of the device proposed in this paper are simulated under the consideration of parasitic inductance.

AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA

With the inherent algorithmic error resilience of conventional neural networks (CNN) and the worst-case design methodologies of current electronic design automation tools, overclocking-based timing speculation is a promising technique to improve the performance of CNN accelerators on FPGA by removing unnecessary timing margins. To avoid potential timing errors, timing delay measurement should be used during overclocking. However, current approaches are not yet good at measuring paths with more intense variability factors such as jitter, and lack an automated process for testing circuit delays. In this paper, we first propose 2-dimension multi-frame fusion to deal with the sampling jitter, then present a timing delay measurement-based automatic overclocking system (AOS) running on heterogeneous FPGA for high-performance CNN accelerators. On the FPGA side, AOS is composed of timing delay monitors (TDM) that can measure all types of timing paths, a TDM controller that converts the sampled values of TDMs into timing delay in terms of the ratio of path delay to the clock period. On the CPU side, AOS converts the path delay from clock period ratio to absolute delay value and decides the frequency of the accelerator in the next iteration. We demonstrate AOS with a SkyNet accelerator on the Xilinx ZCU104 board and achieve 657FPS at 436MHz without accuracy degradation, which is 1.41× performance compared to the baseline.

Development of an in-vitro model for extracorporeal blood pumps to study the effects of artificial pulsatility on human blood.

The application of extracorporeal circulation (ECC) systems is known to be associated with several implications regarding hemolysis, inflammation, and coagulation. In the last years, systems with pulsatile blood flow are increasingly used with the intention to improve hemodynamics in reperfusion. However, their implications on the aforementioned aspects remain largely unknown. To investigate the effects of pulsatility, this ex-vivo study was initiated. Test circuits (primed with human whole blood) were set up in accordance with the recommendations of international standards for in-vitro evaluation of new components and systems of ECC. Diagonal pumps were either set up with non-pulsatile (n = 5, NPG) or pulsatile (n = 5, PG) pump settings and evaluated for 6 h. All analyses were conducted with human whole blood. Blood samples were repeatedly drawn from the test circuits and analyzed regarding free hemoglobin, interleukin 8 (IL-8), platelet aggregation and acquired von Willebrand syndrome (AVWS). After 1 h of circulation, a significant coagulation impairment (impaired platelet function and AVWS) was observed in both groups. After 6 h of circulation, increased IL-8 concentrations were measured in both groups (NPG: 0.05 ± 0.03 pg./mL, PG: 0.03 ± 0.01 pg./mL, p = 0.48). Pulsatile pump flow resulted in significantly increased hemolysis after 6 h of circulation (NPG: 37.3 ± 12.4 mg/100 L; PG: 59.6 ± 14.5 mg/100 L; p < 0.05). Our results indicate that the coagulative impairment takes place in the early phase of ECC. Pulsatility did not affect the occurrence of AVWS ex-vivo. Prolonged durations of pulsatile pump flow led to increased hemolysis and therefore, its prolonged use should be employed cautiously in clinical practice with appropriate monitoring.

Application of adaptive improved DE algorithm based on multi-angle search rotation crossover strategy in multi-circuit testing optimization

Abstract This study based on the standard differential evolution (DE) algorithm was carried out to address the issues of control parameter imprinting, mutation process, and crossover process in the standard DE algorithm as well as the issue of multidimensional circuit testing optimization. A rotation control vector was introduced to expand the search range in the poor strategy to the circumference range of the individual and the parent target individual, and a rotation crossover operator and a binomial poor operator were combined. Finally, an improved adaptive DE algorithm based on a multi-angle search rotation crossover strategy was obtained. The research will improve the DE algorithm to optimize the testing of multidimensional circuits. It can be noted that the improved average precision value is 0.9919 when comparing the precision recall curves of the DE algorithm before and after the change, demonstrating a significant improvement in accuracy and stability. The fitness difference of the 30-dimensional problem is discovered to be between 0.25 × 103 and 0.5 × 103 by comparing the box graphs of the 30-dimensional problem with that of the 50-dimensional problem. On the 50-dimensional problem, when calculating the F4–F10 function, the fitness difference of the improved DE algorithm is 0.2 × 104–0.4 × 104. In summary, the improved DE algorithm proposed in this study compensates for the shortcomings of traditional algorithms in complex problem calculations and has also achieved significant optimization results in multidimensional circuit testing.

Short complete diagnostic tests for circuits with two additional inputs in some basis

Abstract We prove that any Boolean function in n variables can be modeled by a testable Boolean circuit with two additional inputs in the basis “conjunction, oblique conjunction, disjunction, negation” so that the circuit admits a complete diagnostic test of the length at most 2n + 3 with respect to stuck-at faults of the type 1 at gate outputs.

INFLUENCE OF THE SYNTHETIC INERTIA REGULATOR ON FREQUENCY CHANGES OF ELECTRIC POWER SYSTEMS IN TRANSIENT MODES

The article is devoted to the use of wind power plants as sources of synthetic inertia in order to increase the stability margins and damping frequency fluctuations. The purpose of this study is to establish the possibility of using the synthetic inertia controller of wind turbines to reduce the amplitudes of frequency fluctuations in transient conditions. One consequence of integrating a large number of wind farms is to reduce the amount of kinetic energy (inertia) available to operate the system. If the system inertia becomes too low, it can compromise frequency stability when large generating units fail. The smaller the moment of inertia in the system, the greater the frequency fluctuations occur after the active power balance is disturbed. A regulator of synthetic inertia of a wind power plant has been obtained, which makes it possible to reduce frequency dips during transient conditions. Recommendations are made regarding the choice of gain factors for the inertia controller. A control model for wind turbines with a synthetic inertia controller is presented. On the example of a test circuit of an electric power system, modeling of disturbances in the form of a load surge and a short circuit was carried out. As a result, the characteristics of the change in the frequency of the electric power system in the absence and presence of a wind power plant are given.

Modular multilevel converter‐based voltage source converter high‐voltage direct current valve operating test circuit

AbstractIt is very important to obtain high reliability in the high‐voltage direct current (HVDC) system operation because of extremely high and huge power capacity. To guarantee the reliability IEC‐62501 standard requires valve test for the voltage source converter (VSC) HVDC system. This paper proposes a test circuit for modular multilevel converter (MMC)‐based HVDC valve. The proposed scheme has good features of adequate test current generation, considerably reduced power supply voltage, simplified test circuit topology, etc., compared to the conventional test circuits. The validity of the proposed scheme is verified through experimental results.

A Novel Pulse Compression Diode for Picosecond Pulse Generation

A novel pulse compression diode capable of generating high-voltage, picosecond pulses is introduced. The design concept and technical means of the novel diode based on semi-insulating gallium arsenide (SI-GaAs) materials are described, followed by the presentation of its static characteristics with three unique operating states. Typical output rise time for the novel diode with self-breakdown is limited to a few nanoseconds (1–2 ns). The basic physical mechanism affecting the fast conduction of the device is then analyzed, and the electrode structure is optimized as a consequence. Finally, a test circuit with a MOSFET as a preswitch is used as an example to verify the compression characteristics of the modified device. The experimental results show that the pulse front is sharpened from 32 ns to 853 ps and the full-width at half-maximum (FWHM) is sharpened from 120 to 2.1 ns by the pulse compression diode without extra triggering. Lifetime measurement experiments were conducted at a pulse repetition frequency of 100 Hz, revealing no instances of switch failures or malfunctions. The novel pulse compression diode has great potential for various applications, including in national defense, industrial, and medical sectors, due to its fast response, long lifetime, high reliability, and ease of series–parallel connection.

An Accurate Method for Measuring the Low-Temperature Coefficient of Resistors

The temperature coefficient of resistors is one of the key parameters to characterize the reliability of resistors. In precision circuit design, it is necessary to test and screen the key resistors and use the resistors with matching temperature coefficient values to ensure the accuracy and stability of circuit output. In this paper, aiming at how to accurately test the temperature coefficient value of low-temperature coefficient resistors, an indirect test method is proposed. The study adds a reference resistor into the test loop and tests the voltage values at both ends of the reference resistor. The tested resistor when the forward and reverse voltage sources are applied. The accurate resistance values of the tested resistor at different temperatures are obtained by calculation to calculate the temperature coefficient value of the resistor. The method can effectively reduce the measurement uncertainty of the test instrument and the potential thermoelectric influence generated in the test circuit. The measured results show that the measurement method proposed in this paper can obtain a more accurate and reliable resistor temperature coefficient.

Two Circuits for Directing and Controlling Ballistic Fluxons

Reversible logic schemes using flux solitons (fluxons) on long Josephson junctions (LJJs) have recently been proposed. The attraction of the fluxon is that it propagates ballistically along an LJJ until it encounters a change in the character of the LJJ, often a designed circuit element. Logic gates involve fluxons interacting with circuit elements and with other fluxons. However, testing of ballistic fluxon circuits requires other circuits outside the logic family to direct and control fluxon motion. We discuss two such <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">non-reversible</i> fluxon control circuits. First, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">polarity filter gate</i> is a simple non-reversible gate that allows one polarity of fluxon to pass, while reflecting the other polarity. In the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</i> state both polarities reflect. Second, the polarity separator generalizes on the polarity filter concept and allows separation of the two fluxon polarities into different LJJs. We discuss simulations of these structures and possible applications.

A Unified Capacitor Stress Emulation Method for High-Power Converter Applications

This paper proposes a unified capacitors stress emulation method, which has two unique test capabilities: 1) concurrent electrical stress emulation to AC capacitors and DC capacitors; 2) different electrical stress levels (including different ripple current, ripple voltage, and DC voltage) can be individually controlled for the testing samples. It preserves the advantages of a recently reported method with a minimum required power supply and is robust to testing sample degradation. This method is suitable for application-oriented stress emulation testing with different types of DC / AC capacitors and multiple electrical stresses in high power converter systems. The circuit architecture and testing ability of this method are presented. Moreover, analytical models are derived to size the key components to realize various testing requirements. Proof-of-concept experimental results are presented to verify the feasibility of the proposed test method.

Demonstration and Comparison of On-Chip High-Frequency Test Methods for RSFQ Circuits

On-chip high-frequency test for Rapid Single Flux Quantum (RSFQ) circuits without external high-frequency equipment is very attractive and promising. The test method based on Shift Register (SR) is widely used for long time. Recently, we have proposed two test methods based on Pseudo Random Binary Sequence (PRBS) generator. In this paper, a Full Adder (FA) is taken as an example of circuit under test and the design methodology of the above approaches is presented. For FA with the traditional and two proposed approaches, the high-frequency test circuits are fabricated and tested. We demonstrate the successful measurement of the three circuits with the maximum operating frequency of the full adder at 23.3 GHz, 26.2 GHz and 27.4 GHz respectively. Based on the experimental results, the clock frequency measurement in the proposed two PRBS based test systems is more accurate and time-saving, which is advantageous for high-frequency RSFQ circuits measurement.

Demonstration of Interface Circuits for Adiabatic Quantum-Flux-Parametron Cell Library Using an Eight-Metal Layer Superconductor Process

In this paper, we designed and demonstrated interface circuits between AQFP (adiabatic quantum-flux-parametron) and RSFQ (rapid single-flux-quantum) circuits according to the established AQFP and RSFQ cell libraries using the MIT LL SFQ5ee process. The principles of these interfaces are based on ones that were previously designed and demonstrated using a four-metal-layer superconductor process. The AQFP-to-RSFQ interface is based on an RSFQ comparator, where an output current from an AQFP buffer is converted to an SFQ pulse output. The RSFQ-to-AQFP interface is based on an RSFQ D flip-flop, where the internal state of the D flip-flop is read out by an AQFP buffer. Thanks to the eight-metal-layer process, the interfaces can be designed with reduced circuit area compared to original designs with the four-metal-layer process. We designed, fabricated, and tested an AQFP-RSFQ hybrid multiplexer test circuit as an example of utilization of the interfaces, which results in correct operation with reasonably wide bias margins in low-frequency tests.

Hsiao Codes Properties in Discrete Devices Technical Diagnostics Systems

The error detection features by modified Hamming codes — codes with odd column weights, or Hsiao codes — are analyzed. The error detection properties of Hsiao codes are considered separately for data symbols, as well as for all code word symbols. It is shown that Hsiao codes detect any errors with odd multiplicities and errors with multiplicities d &lt; 4. The Hsiao codes error detection performance is compared with the error detection performance by classic Hamming codes. The experiments results showing the Hsiao codes high efficiency in organizing the calculation testing at the automation device outputs are given. Hsiao codes can be very effectively used in solving problems of automation devices synthesis with the malfunctions and errors detection in calculations, including the devices synthesis with controllable structures and with concurrent calculation testing circuits.

Simulation Tool for Assessing Driving Strategies for Electric Racing Vehicles

This article deals with the development of a simulation tool for evaluating the energy consumption of an electric racing vehicle. The tool was carried out in the Matlab/Simulink environment and is based on the equations that govern the dynamics of the vehicle. All the systems of an electric vehicle were modelled: motor, battery, controller, bodywork, etc., as well as the characteristics of the competition circuit. The tool allows us to choose the input variable of the simulation between motor torque, motor voltage, battery power or vehicle speed and provides the values of all relevant physical variables to evaluate the performance of the vehicle. To evaluate the tool, a test was carried out with a real vehicle on a test circuit and both were modelled. The simulation results were compared with the experimental data obtained in the real test and it was verified that the simulation tool provides results that are very close to the real ones. In order to show the performance of the tool, simulations of different driving strategies were carried out and the results of energy consumption in each of them were obtained, allowing us to choose which of them is the most efficient.