Circuit For Capacitive Sensors Research Articles

A CMOS front-end circuit for capacitive sensors with zero adjustment

A front-end circuit with measurement zero adjustment was designed using 180nm CMOS technology for capacitive sensors. A series-switched capacitor composed of capacitor under test and MOSFETs is controlled by a clock signal to convert capacitance to current. The minimum output current at fixed capacitance can be adjusted by applying different voltage to realize zero adjustment. The test shows that the output current has a monotonic linear relationship with the measured capacitance, with capacitance detection range reaches 50pF-3000pF and an output current range of 0.59mA-22.2mA. The maximum span of multiple measurements was lower than 8.37uA. The stable time is less than 23ms and sensitivity is 19.8uA/pF. This circuit is suitable for long-distance and wide-range capacitance detections.

Direct Interface Circuit for Capacitive Sensors Affected by Parasitic Series Resistances

This article presents a novel circuit to directly interface a capacitive sensor affected by parasitic series resistances to a digital processor (DP). The presence of such resistances distorts the estimation of the capacitance to be measured. Current measurement procedures for these sensors, such as impedance-frequency characteristics, are complex and require significant hardware resources, power consumption, and time. To eliminate these drawbacks, a new circuit based on the so-called direct interface circuits (DICs) is introduced, which performs the digital reading of the sensors taking advantage of the presence of DPs in many applications. The hardware requirements in the new design are minimal: just two resistors and an operational amplifier in addition to the DP. The circuit requires only two time measurements to estimate sensor capacitance. These are obtained during a single capacitor charging-discharging process, simultaneously reducing power consumption and measurement time. The circuit has been implemented using a field-programmable gate array (FPGA), as the DP, in a general-purpose board to evaluate its performance. Although it is not an application-specific design, the circuit shows a maximum systematic error of 0.37% for capacitances in the 100 pF–96 nF range with parasitic series resistances up to 1200 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> . The maximum measurement time for this range is just 4.5 ms.

A Dual-Slope-Based Capacitance-to-Time Signal Conditioning Circuit for Leaky Capacitive Sensors

A robust signal conditioning circuit for capacitive sensors, based on the dual-slope and phase-sensitive-detection technique, is presented in this article. The circuit is designed to measure the capacitance of the leaky capacitive sensors. The phase-sensitive-detection technique mitigates the effect of the shunting conductance. In addition, the circuit is designed in such a way that the error due to the parasitic/stray capacitance on the measurement of the sensor capacitance is negligible. Furthermore, an autotuning frequency-independent quadrature phase-shifter circuit is designed for an accurate 90° phase generation. A prototype of the circuit is built and tested. The experimental results show that the designed circuit can measure the sensor capacitance in the range from 65 to 528 pF with accuracy within ±1%. The robustness of the proposed circuit is tested against the variation in the amplitude and frequency of input sinusoidal excitation signal. The results confirm that the proposed circuit is well suited for sensors, such as capacitive humidity sensors, water level detection sensors, and fingerprint sensors.

Precision Improvement of Power-Efficient Capacitive Senor Readout Circuit Using Multi-Nested Clocks

This paper proposes a clock strategy to improve the precision of power-efficient readout circuit for capacitive sensor. To achieve high power efficiency, capacitive sensor such as MEMS accelerometer is designed with open-loop architecture rather than close-loop one. In the open-loop architecture, the capacitance variation of sensing element is limited to femto-farad level in order to overcome nonlinearity problem. However, due to this limitation, the signal charge from sensing element is weak and the interference charge due to coupling capacitance between clock wires and sensing electrodes becomes a significant issue. Therefore, split clock bus is employed to meet this challenge, but the split clock bus introduces the timing mismatch which causes the charge injection sensitive to fabrication process and circuit operating voltage. As a result, the input offset, the variation of the offset and the nonlinearity of readout circuit will increase, and this will lead to reduction of precision. In this work, a clock scheme named “multi-nested clocks” is proposed to address the charge injection problem. The multi-nested clocks are demonstrated in a readout circuit fabricated using a $0.18-\mu \text{m}$ BCD process. The measurement results show that compared to the readout circuit using traditional clock, the readout circuit using the multi-nested clocks significantly reduces the equivalent input offset from 1.66fF to 0.25fF, the offset variation from 1.4fF to 0.2fF and the nonlinearity from 5.5% to 0.9%.

Parasitic consideration for differential capacitive sensor

Parasitic integration for a single supply differential capacitive sensing technique is presented in this paper. In real capacitive sensor measurement, parasitic impedance exists in its measurement. This paper objective is to study the effect of capacitive and resistive parasitic to the capacitive sensor circuit. The differential capacitive sensor circuit derivation theory is elaborated first. Then, comparison is made using simulation. Test was carried out using frequency from 40 kHz up to 400 kHz. Result is presented and have shown good linearity of 0.99984 at 300 kHz, R-squared value. This capacitive sensor is expected to be used for energy harvesting application.

A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors

A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch, a symmetrical readout circuit is realized. The linear input range is increased, and the systematic offsets of two input op-amps are cancelled. The common-mode noise and even-order distortion are also rejected. A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps, and a Verilog-A-based varactor is used to model the real variable sensing capacitor. Simulation results show that the output voltage of this proposed readout circuit responds correctly, while the under-test capacitance changes with a frequency of 1 kHz. A metal-insulator-metal capacitor array is designed on chip for measurement, and the measurement results show that this circuit achieves sensitivity of 370 mV/pF, linearity error below 1% and power consumption as low as 2.5 mW. This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.

A Delta–Sigma Interface Circuit for Capacitive Sensors With an Automatically Calibrated Zero Point

We present a low-complexity interface circuit for capacitive sensors that are integrated into sensor microsystems. To reduce hardware cost while keeping high resolution, a first-order delta-sigma modulator (DSM), which balances the charge from the capacitive difference between sense and reference capacitors with the charge from a fixed-quantity capacitor, is employed. A charge-mode digital-to-analog converter and a successive approximation register are utilized to automatically calibrate the zero point of the interface circuit, which may shift further than a dynamic range. A prototype circuit fabricated in a 0.35-μm CMOS process has an active area of 0.048 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Its DSM operates at a sampling frequency of 1 MS/s with an oversampling ratio of 128. Experiments show that this circuit can read a capacitive difference from -0.5 to +0.5 pF with a 0.49-fF resolution. A capacitive offset that causes the zero point to shift can be canceled in the range from -2 to 2 pF with a 31.25-fF resolution. Measured power consumption was 1.44 mW at a 3.3-V supply.

Current-Mode Capacitive Sensor Interface Circuit With Single-Ended to Differential Output Capability

This paper presents a current-mode interface circuit for capacitive sensors, with the main features being its ability to produce a differential output from a single-ended sensor (using a fixed reference capacitor) and its simplicity in realization. These advantages make it a potential candidate for applications where differential sensors are not available and where a simple design is required. The principle is, however, easily applicable to differential sensors as well. The interface concept can be realized in different ways; however, to present a proof of concept on silicon, a prototype has been fabricated and tested in a commercially available 0.8-mum CMOS process. The circuit has been designed using common analog building blocks such as a fully differential operational transconductance amplifier (OTA), a high-output-resistance wide-swing current source, and a single clock phase. The estimated linearity error was 0.2% relative to full-scale swing with a simple two-point calibration. The circuit consumes 145 muA from a 5-V power supply.

Analysis of a Direct Interface Circuit for Capacitive Sensors

We present the theoretical analysis and performance results of a direct microcontroller unit (MCU) interface circuit for capacitive sensors based on the charge-transfer method, when stray capacitances are considered. The interface circuit can implement two alternative two-point calibration techniques that reduce the effects of stray capacitance, temperature, and MCU parameters that depend on the power supply voltage. The best measurement deviation achieved from 0degC to 50degC and for power supply voltage from 4.0 to 5 V is below 0.01 full-scale range (FSR) for the two subranges from 10 to 100 pF and from 100 pF to 1 nF and 0.08 FSR for the subrange from 2 to 10 pF.

Features and Design Constraints for an Optimized SC Front-End Circuit for Capacitive Sensors With a Wide Dynamic Range

This paper presents optimization criteria for an integrated switched-capacitor front-end circuit for capacitive sensors with a wide dynamic range. The principle of the interface is based on the use of a relaxation oscillator. A negative-feedback circuit controls the charge-transfer speed to prevent the overload of the input amplifier for large input signals which thus enables a wide dynamic range of capacitor values. Moreover, it has been shown that the use of negative feedback can also result in much better noise performance. However, for the interface to function properly, there is a serious limitation for the value of a specific parasitic capacitance. Therefore, a method which extends the acceptable range of this parasitic capacitance is proposed. A novel method of linearity measurement which takes the influence of PCB parasitic capacitances into account, is also presented. The circuit has been designed and implemented in 0.7 mum standard CMOS technology. The supply voltage is 5 V and the measured value for the supply current is about 1.4 mA. Experimental results show that for the capacitor range of 1 pF to 300 pF, application of negative feedback yields a linearity of about 50 x10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> (14 bits) with a 16-bit resolution for a measurement time of 100 ms. Tests have been performed over the temperature range from to .

A novel interface circuit for grounded capacitive sensors with feedforward-based active shielding

This paper proposes and analyses a novel interface circuit for capacitive sensors in which one of the electrodes is grounded. The novel design makes a charge-balanced relaxation oscillator (applied so far to floating capacitive sensors) suited for the measurement of grounded capacitive sensors and applies advanced measurement techniques, such as auto-calibration and chopping. Furthermore, these techniques are combined with feedforward-based active shielding instead of the usual feedback-based one, thus avoiding instability problems. A prototype of the novel interface circuit has been implemented with discrete components and tested for sensor capacitances between 27 pF and 330 pF and for different lengths of the interconnecting cable. The nonlinearity error amounts to less than 0.1% FSS for a 10 m cable.

SC front-end with wide dynamic range

A novel front-end circuit for capacitive sensors and switched-capacitor (SC) circuits is presented. In this circuit charge is transferred to an input integrator circuit in a controlled way to prevent overload of the input amplifier. Application of this technique extends the linear range for large input signals.

A study of a high-resolution linear circuit for capacitive sensors

A circuit for capacitance measurements is described. The circuit permits offset capacitance compensation using a dc voltage. The electronic circuitry with its testing is described. The output voltage is a linear function of the capacitance measured. Experimental data show good agreement with values predicted by the linear formula. Experiments show it is possible to measure capacitance changes with a resolution of a few femtofarads (fF).

An integrated interfacing circuit for capacitive sensors

An integrated interfacing circuit for capacitive sensors