Circuit Emulation Services Research Articles

Forecasting changes of frame alignment loss probability in convergent networks

The paper provides a developed method that allows to predict a change in the frame alignment loss probability when using the unstructured circuit emulation services in mobile backhaul networks based on the bit-error monitoring. This method allows to determine the moments of exceeding the threshold value by frame alignment loss probability for any technically possible number of TDM cycles, encapsulated in an Ethernet frame. The fragments of dependences of the frame alignment loss probability on the bit error value with different values of the number of TDM cycles, encapsulated in an Ethernet frame, produced using the developed model were shown. It was shown that large threshold values of frame alignment loss probability correspond to the large values of the number of TDM cycles, encapsulated in an Ethernet frame. With the increase in the number of TDM cycles, encapsulated in an Ethernet frame, the probability that frame alignment loss probability exceeds its threshold value grows, which is undesirable. The developed method allows to decide on the possibility to increase the communication channel utilization by increasing the number of TDM cycles, encapsulated in an Ethernet frame, based on data of forecasting changes in the frame alignment loss probability.

Toward Wireless Backhaul Using Circuit Emulation Over Optical Packet-Switched Metro WDM Ring Network

Optical WDM metro-ring networks have been considered to be promising solutions for wireless backhaul. In this paper, we propose an integrated traffic control scheme (ITCS), which facilitates circuit emulation service (CES) for wireless backhaul over a previously proposed experimental optical packet-switched WDM metro-ring network, HOPSMAN. The ITCS seamlessly integrates variable-bit-rate (VBR) CES wireless with connection-less best-effort data, satisfying stringent QoS requirements and retaining maximal network throughput. The ITCS ensures efficient setup of CES connections by employing a simple mean-rate-based distributed admission control followed by a novel slot-marking reservation. The total connection setup delay is comprised of the setup queueing delay and slot-marking delay. While the slot-marking delay is nearly a ring time, the mean setup queueing delay is formally computed through an accurate approximation based on an M/G/m queueing analysis. We show simulation results to demonstrate that the ITCS accommodates remarkably high CES traffic loads while satisfying a wide range of delay requirements for wireless backhaul. Taking the background best-effort traffic into account, ITCS achieves exceedingly low delay, jitter, and delay bound for CES under various traffic loads and burstiness.

Analysis and optimization of parameters of circuit emulation service in mobile networks

The article shows how the quantity of encapsulated TDM frames affects performance of a frame aligner in the case of CESoETH implementation in Mobile Backhaul network. Influence on the frame aligner performance is considered in terms of alignment loss probability and frame alignment recovery time. The article recommends the optimum value of encapsulated TDM frames considering minimization of alignment loss probability and frame alignment recovery time. The article proposes a model that considers to kinds of risks to the frame aligner performance. The proposed model considers risk caused by bit errors in frame alignment sequence and risk caused by frame losses. Both risks are considered in order to estimate how the quantity of encapsulated TDM frames affects performance of a frame aligner in the case of structure-agnostic CESoETH

Deploying Circuit Emulation Services (CES) Over EPON Using Preemptive Priority Medium Access Controller

Circuit Emulation Services (CES) technology has emerged as an option to mitigate traditional Time Division Multiplexing (TDM) circuits supporting legacy applications across managed packet networks and the Ethernet Passive Optical Network (EPON) is becoming a major technology for pervasive access. The primary benefits of CES over EPON (CESoEPON) are the low cost and simplicity of deployment to support all types of legacy TDM applications across EPONs. Thus, the QoS-guarantee for highly delay-sensitive services on EPONs could be enhanced. This paper investigates a preemptive priority transmission technique that works on MAC and PHY layer of downstream EPONs. The proposed novel scheme effectively reduces the frame queuing delay as well as jitter, so as to enhance precise time synchronization in EPONs. Through simulation experiments, we show that the proposed scheme achieves superior and precise QoS control compared to existing non-preemptive priority methods. A feasible implementation of the proposed solution is also addressed. Finally, we present a general conclusion of the paper as well as address the pros and cons for practical deployment in future works.

Metropolitan optical packet bus-based networks: Packet bursting and emulation of TDM services

The volume of network traffic, notably of data traffic, grows continuously and tremendously during recent years with the appearance of new value-added services such as video on demand, interactive video conferencing, peer to peer data sharing, etc. Faced with this challenge, traditional circuit-switched networks become inappropriate and costly. On the other side, optical packet-switched networks, which support best data traffic thanks to their high flexibility, capacity, and cost-efficiency, appear the most appropriate candidate. To optimise the transmission efficiency of packets in optical networks, a new technology, Modified Packet Bursting (MPB), has been studied in the framework of a metropolitan optical packet bus-based network. Also, in order not to degrade the quality of classical circuit-switched Time Division Multiplexing (TDM) services, which still stay the major revenues of telecom operators today, Circuit Emulation Service (CES) on packet-switched networks has been investigated by main standard organizations. This paper presents the performance analysis of the above two technologies applied to a metropolitan optical packet bus-based network. It specially demonstrates the improvement of CES performance thanks to MPB features.

Research on the Encapsulations Issues of Circuit Emulation Service for T-MPLS Network

该文基于ITU-T所制定的传送多协议标记交换标准，对客户端承载基于电路交换类型的业务进行了深入研究，比较了不同长度的电路业务分组对该业务延时和抖动的影响，并提出了一种动态改变电路业务封装包长的方案。该方案根据业务接收端数据的时延和方差统计情况，来计算一定范围内合适的电路业务净荷长度并反馈给源端的业务适配模块进行调整。为分析该方案的有效性，利用OPNET仿真软件搭建平台进行仿真。结果表明，该方案与固定封装包长方案相比在业务抖动特性和传输效率上具有明显的优势，能很好地适应电路业务的承载要求。

Analysis of a clock‐recovery technique for circuit emulation services over packet networks

AbstractOne important requirement of circuit emulation services (CES) over packet networks is clock synchronization and timing distribution among the nodes. CES depends on reliable and high‐quality timing for operations. In the time division multiplexing (TDM) world, whether plesiochronous digital hierarchy (PDH), synchronous digital hierarchy (SDH) or synchronous optical network (SONET) based, timing and synchronization is inherent in the design of the network. However, when timing critical services such PDH and SDH/SONET are carried over packet network (e.g. IP, Ethernet, etc.), the timing element is lost and has to be carried across the packet network by other means. A well‐known and widely implemented technique for clock recovery in CES is one that is based on packet inter‐arrival time (sometimes called time difference of arrival) averaging. The technique is very simple to implement but provides good performance only when packet losses and packet delay variation (PDV) are very low and well controlled. This technique has been extensively analysed through simulations but has not been fully characterized analytically with correlated traffic in the literature. In this paper, we provide a full analytical examination of this well‐known clock recovery technique. We analyse the effects of correlation of the delay variation in the traffic stream on the quality of the clock recovered by a receiver. We prove analytically that, for a general input process, high correlation of the delay variation produces a large variance of the recovered clock. Copyright © 2007 John Wiley & Sons, Ltd.

Clock synchronization for packet networks using a weighted least‐squares error filtering technique and enabling circuit emulation service

AbstractCircuit emulation service (CES) allows time‐division multiplexing (TDM) services (T1/E1 and T3/E3 circuits) to be transparently extended across a packet network. With circuit emulation over IP, for instance, TDM data received from an external device at the edge of an IP network is converted to IP packets, sent through the IP network, passed out of the IP network to its destination, and reassembled into TDM bit stream. Clock synchronization is very important for CES. This paper presents a clock synchronization scheme based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behaviour of clock synchronization errors between a transmitter and a receiver. In the clock synchronization scheme, the transmitter periodically sends explicit time indications or timestamps to a receiver to enable the receiver to synchronize its local clock to the transmitter's clock. A phase‐locked loop (PLL) at the receiver processes the transmitted timestamps to generate timing signal for the receiver. The PLL has a simple implementation and provides both fast responsiveness (i.e. fast acquisition of transmitter frequency at a receiver) and significant jitter reduction in the locked state. Copyright © 2006 John Wiley & Sons, Ltd.

Adaptive Clock Recovery Method Utilizing Proportional-Integral-Derivative (PID) Control for Circuit Emulation

This paper describes a novel adaptive clock recovery method that uses proportional-integral-derivative (PID) control. The adaptive clock method is a clock recovery technique that synchronizes connected terminals via packet networks, and will be indispensable for circuit emulation services in the next generation Ethernet. Our adaptive clock method simultaneously achieves a short starting-time, accuracy, stable recovery clock frequency, and few buffer delays using the PID control technique. We explain the numerical simulations, experimental results, and circuit designs.

Clock recovery based on packet inter-arrival time averaging

Accurate source clock recovery is an important element of circuit emulation services (CES) over packet networks. A well-known and widely implemented technique for clock recovery in CES is the one that is based on packet inter-arrival time (sometimes called time difference of arrival (TDOA)) averaging. The technique is very simple to implement but provides good performance only when packet losses and packet delay variation (PDV) are very low and well controlled. This technique has not been fully characterized analytically in the literature. In this paper, we provide a full analytical examination of this well-known clock recovery technique. We analyze the effects of correlation of the PDV experienced by the constant bit rate (CBR) traffic stream on the quality of the clock recovered by a receiver. We prove analytically that, for a general input process, high correlation of the PDV produces a large variance of the recovered clock. The paper also describes simple all-digital implementations of the clock recovery scheme using standard digitally controlled oscillators (DCOs).

Carrying E1 circuits over IP

One of the serious problems currently besetting telecommunications carriers lies in the increasing age of their 'outside plant' and infrastructure. Because of fierce competition in the form of alternative suppliers who use an IP-based infrastructure to deliver innovative services, there is a very compelling reason for the world's carriers to follow suit and migrate to IP-based networks. Perceived advantages of a packet network include lower capital expenditures and operating expenses, as well as the opportunity to deliver new revenue streams. Voice services have a champion in voice-over-Internet protocol (VoIP), but how do carriers deal with all those other time division multiplex (TDM) based services which still generate lots of cash for them? One technology is circuit emulation services over packet (CESoP), which has broad capabilities for carrying all Layer 2 traffic over a packet switched network (PSN), while, at the same time, faithfully replicating the original TDM service. CESoP has the fundamental advantage of making a PSN transparent to the end user, who need never know their traffic is now traversing a new PSN. We can see that CESoP technology can complement VoIP as an important interworking function and has a role in helping carriers achieve a smooth transition between old and new networking infrastructures.

Blocking Probability Analysis for Packet Circuit Emulation Services

Standardization of pseudo-wire and circuit emulation services on IP packet networks is underway. The ability to quickly find circuits in networks supporting circuit emulation is directly computed using blocking probability analysis. When all of the sequenced flows have the same maximum packet size, i.e., they are homogeneous, blocking probabilities are computed using Erlang's B formula. This paper describes analysis tools for the heterogeneous case and introduces the concept of steady-state fragmentation blocking probability, which controls the size of state transition diagrams used in the analysis. Simulation results using these tools are presented.

Circuit emulation services over Ethernet—Part 1: Clock synchronization using timestamps

AbstractDue to Ethernet's ubiquity, simplicity, scalability and cost effectiveness there is significant customer demand for Ethernet‐based access and transport in the metropolitan network. Many service providers have recognized this need and are currently establishing Ethernet‐based services to meet this demand. The migration to all‐Ethernet access will not be instantaneous since many customers currently have legacy TDM access interfaces on their routers and PBX equipment. Circuit Emulation Services (CES) over Ethernet provides TDM circuit emulation to support TDM traffic such as T1/E1, T3/E3, OC3/12, etc. This two‐part paper presents the application of CES over Ethernet as well as a new technology that addresses the issues associated with clock recovery and synchronization in an Ethernet network with its inherent network jitter. Part 1 describes a clock synchronization technique where a transmitter periodically sends explicit time indications or timestamps to a receiver to enable the receiver to synchronize its local clock to the transmitter's clock. Copyright © 2004 John Wiley & Sons, Ltd.

Circuit emulation services over Ethernet—Part 2: Prototype and experimental results

AbstractThis paper describes a prototype implementation and experimental results for unstructured circuit emulation service (UCES) of T3 data stream over Ethernet. As explained in Part 1 of this paper,1 packet‐switched networks such as Ethernet are not designed to transport TDM data and so have no inherent clock distribution and synchronization mechanisms. Thus, to allow the frequency of the source TDM stream to be regenerated at the receiver, the prototype employed the clock synchronization scheme described in Part 1 of this paper. Our experiments showed that the recovered clock conforms to ITU‐T G.824 requirements2 even for networks that introduce high jitter and packet loss. Copyright © 2004 John Wiley & Sons, Ltd.

Design of ATM circuit emulation service terminal adapter

The asynchronous transfer mode (ATM) Circuit Emulation Service (CES) terminal adapter (TA) is designed for transporting the DS1/E1 tributary in an ATM network. The DS1/E1 tributary are segmented and reassembled by an ATM adaptation layer 1 (AAL1) segmentation and re-assembly (SAR) field programmable gate array (FPGA) in the low-speed circuit board. Synchronous residual time stamp (SRTS) is used to recover the source clock at the receive end. The high-speed board provides a physical layer and ATM layer functions. A cell multiplexer/demultiplexer FPGA, is designed to route cells to each service low-speed boards. The prototype CES-TA is connected to ATM switches and tested for its performance.