Circuit Decomposition Research Articles

Magnetic Circuit Decomposition Model and Novel Inner-Turn Fault Protection Scheme for Shunt Reactor with Auxiliary Windings

Magnetic Circuit Decomposition Model and Novel Inner-Turn Fault Protection Scheme for Shunt Reactor with Auxiliary Windings

Causal and compositional structure of unitary transformations

The causal structure of a unitary transformation is the set of relations of possible influence between any input subsystem and any output subsystem. We study whether such causal structure can be understood in terms of compositional structure of the unitary. Given a quantum circuit with no path from input systemAto output systemB, systemAcannot influence systemB. Conversely, given a unitaryUwith a no-influence relation from inputAto outputB, it follows from [B. Schumacher and M. D. Westmoreland, Quantum Information Processing 4 no. 1, (Feb, 2005)] that there exists a circuit decomposition ofUwith no path fromAtoB. However, as we argue, there are unitaries for which there does not exist a circuit decomposition that makes all causal constraints evidentsimultaneously. To address this, we introduce a new formalism of `extended circuit diagrams', which goes beyond what is expressible with quantum circuits, with the core new feature being the ability to represent direct sum structures in addition to sequential and tensor product composition. Acausally faithfulextended circuit decomposition, representing a unitaryU, is then one for which there is a path from an inputAto an outputBif and only if there actually is influence fromAtoBinU. We derive causally faithful extended circuit decompositions for a large class of unitaries, where in each case, the decomposition is implied by the unitary's respective causal structure. We hypothesize that every finite-dimensional unitary transformation has a causally faithful extended circuit decomposition.

Experimental implementation of non-Clifford interleaved randomized benchmarking with a controlled- S gate

Hardware efficient transpilation of quantum circuits to a quantum devices native gateset is essential for the execution of quantum algorithms on noisy quantum computers. Typical quantum devices utilize a gateset with a single two-qubit Clifford entangling gate per pair of coupled qubits, however, in some applications access to a non-Clifford two-qubit gate can result in more optimal circuit decompositions and also allows more flexibility in optimizing over noise. We demonstrate calibration of a low error non-Clifford Controlled-$\frac{\pi}{2}$ phase (CS) gate on a cloud based IBM Quantum computing using the Qiskit Pulse framework. To measure the gate error of the calibrated CS gate we perform non-Clifford CNOT-Dihedral interleaved randomized benchmarking. We are able to obtain a gate error of $5.9(7) \times 10^{-3}$ at a gate length 263 ns, which is close to the coherence limit of the associated qubits, and lower error than the backends standard calibrated CNOT gate.

Discrete-time quantum walk on circular graph: Simulations and effect of gate depth and errors

We investigate the counterparts of random walks in universal quantum computing and their implementation using standard quantum circuits. Quantum walks have been recently well investigated for traversing graphs with certain oracles. We focus our study on traversing a 1D graph, namely a circle, and show how to implement a discrete-time quantum walk in quantum circuits built with universal CNOT and single qubit gates. We review elementary quantum gates and circuit decomposition techniques and propose a generalized version of all CNOT-based circuits of the quantum walk. We simulated these circuits on five different qubits IBM-Q quantum devices. This quantum computer has nonperfect gates based on superconducting qubits, and, therefore, we analyzed the impact of the CNOT errors and CNOT-depth on the fidelity of the circuit.

NSGA-II Based Thermal-Aware Mixed Polarity Dual Reed–Muller Network Synthesis Using Parallel Tabular Technique

Proposed work presents an OR-XNOR-based thermal-aware synthesis approach to reduce peak temperature by eliminating local hotspots within a densely packed integrated circuit. Tremendous increase in package density at sub-nanometer technology leads to high power-density that generates high temperature and creates hotspots. A nonexhaustive meta-heuristic algorithm named nondominated sorting genetic algorithm-II (NSGA-II) has been employed for selecting suitable input polarity of mixed polarity dual Reed–Muller (MPDRM) expansion function to reduce the power-density. A parallel tabular technique is used for input polarity conversion from Product-of-Sum (POS) to MPDRM function. Without performance degradation, the proposed MPDRM approach shows more than 50% improvement in the area and power savings and around 6% peak temperature reduction for the MCNC benchmark circuits than that of earlier literature at the logic level. Algorithmic optimized circuit decompositions are implemented in physical design domain using CADENCE INNOVUS and HotSpot tool and silicon area, power consumption and absolute temperature are reported to validate the proposed technique.

A model for finding transition-minors

The well known cycle double cover conjecture in graph theory is strongly related to the compatible circuit decomposition problem. A recent result by Fleischner et al. (2018) gives a sufficient condition for the existence of a compatible circuit decomposition in a transitioned 2-connected Eulerian graph, which is based on an extension of the definition of K5-minors to transitioned graphs. Graphs satisfying this condition are called SUD-K5-minor-free graphs. In this work we formulate a generalization of this property by replacing the K5 by a 4-regular transitioned graph H, which is part of the input. Furthermore, we consider the decision problem of checking for two given graphs if the extended property holds. We prove that this problem is NP-complete and fixed parameter tractable with the size of H as parameter. We then formulate an equivalent problem, present a mathematical model for it, and prove its correctness. This mathematical model is then translated into a mixed integer linear program (MIP) for solving it in practice. Computational results show that the MIP formulation can be solved for small instances in reasonable time. In our computations we found snarks with perfect matchings whose contraction leads to SUD-K5-minor-free graphs that contain K5-minors. Furthermore, we verified that there exists a perfect pseudo-matching whose contraction leads to a SUD-K5-minor-free graph for all snarks with up to 22 vertices.

Single-step implementation of high-fidelity n -bit Toffoli gates

The family of $n$-bit Toffoli gates, with the two-bit Toffoli gate as the figurehead, are of great interest in quantum information as they can be used as universal gates and in quantum error correction, among other things. We present a single-step implementation of arbitrary $n$-bit Toffoli gates (up to a local change of basis), based on resonantly driving a single qubit that has a strong Ising coupling to $n$ other qubits. The setup in the two-qubit case turns out to be identical to the universal Barenco gate. The gate time and error are, in theory, independent of the number of control qubits, scaling better than conventional circuit decompositions. We note that our assumptions, namely strongly coupling $n+1$ qubits and a driving frequency that scales with $n$, may break down for large systems. Still, our protocol could enhance the capabilities of intermediate scale quantum computers, and we discuss the prospects of implementing our protocol on trapped ions, Rydberg atoms, and on superconducting circuits. Simulations of the latter platform show that the Toffoli gate with two control bits attains fidelities of above 0.98 even in the presence of decoherence. We also show how similar ideas can be used to make a series of controlled-\textsc{not}-gates in a single step. We show how these can speed up the implementation of quantum error correcting codes and we simulate the encoding steps of the three-qubit bit-flip code and the seven-qubit Steane code.

A Decomposition Workflow for Integrated Circuit Verification and Validation

This paper reviews a developed integrated circuit (IC) decomposition workflow that can be leveraged for extracting design files and performing advanced verification and validation techniques on fabricated chips. In this work, a commercial 130-nm microcontroller is delayered and imaged to recreate the full design stack-up. Using MicroNet’s Pix2Net, the features for each layer are extracted allowing a GDSII file to be generated and design netlists for target components to be recovered. The full decomposition process is executed on both the read only memory (ROM) array and universal serial communications interface (USCI) of the microcontroller to recover the layout GDSII and circuit netlist. A single-precision floating point unit (FPU) test article is used to incorporate a spectrum of error types into the design layout, thus creating a set of test articles with obfuscated errors. Once the netlists for each of the modified designs are extracted, formal verification techniques are applied to each netlist, thus illuminating the errors originally inserted into the layout. The extracted netlists are then converted into register transfer level (RTL) representations and simulated with the original design verification testbench.

Spin-Torque-Based Quantum Fourier Transform

Quantum computing (QC) provides an efficient platform to solve complex problems such as number factoring and searching. The quantum Fourier transform (QFT) is an integral part of quantum algorithms for integer number factoring, phase estimation, discrete algorithms, interchange of position and momentum states, quantum key distribution protocol, multiparty quantum telecommunication, and quantum arithmetic. The theoretical and experimental implementations of QFT on various platforms have been proposed by researchers. Spin-torque-based qubit(s) manipulation is one of the encouraging solid-state device technologies. However, to date, QFT is not realized by spin-torque-based QC architecture. In this article, the spin-torque-based architecture has been modeled with the help of optimized decomposition of quantum circuits for the QFT. Moreover, an optimal-depth Clifford + T gates set-based quantum circuit is utilized to implement the QFT. The performance analysis in terms of fidelity (>99%), magnitude, and phase difference of respective density matrices for different forms of three-qubit QFT provides a novel way of its physical realization to address the complex problems.

Analytical Equivalent Circuit Extraction Procedure for Broadband Scalable Modeling of Three-Port Center-Tapped Symmetric On-Chip Inductors

This paper presents a new, almost fully analytical methodology for component value extraction of a double- ${\pi }$ equivalent circuit model for three-port on-chip inductors from a given S-parameter dataset. The compact model provides an accurate fit over a wide frequency range from dc to beyond the self-resonance frequency (SRF) to a tabular input ${S}$ -parameter model describing a symmetric center-tapped on-chip inductor. The input dataset may be obtained from a measurement or from an electromagnetic field solver simulation. Using a passive broadband equivalent circuit instead of the original ${S}$ -parameters’ description is advantageous for circuit design, as it facilitates the convergence of transient simulations. The proposed approach carefully considers center-tap parasitics. Hence, the obtained equivalent circuit model fits the input inductor characteristics accurately not only for differential excitation but also in the common-mode and single-ended operation. Due to the fact that the proposed extraction approach is based on physical assumptions and analytical circuit decomposition, the obtained component values are physically meaningful and relate to geometry. Thus, this approach is suitable for the generation of scalable compact models, which can be used to speed-up inductor optimization during the RF circuit design. The proposed methodology has been verified on a three-port inductor realized in a 28-nm CMOS technology and measured up to 60 GHz. The extracted equivalent circuit model exhibits an accurate fit to the measured data over the entire frequency range in all operation modes. Finally, field-solver models are used to verify the scalability.

Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip

A layout synthesis design flow for implementing designs on reconfigurable systems-on-chip is developed by the Institute for Design Problems in Microelectronics of Russian Academy of Sciences, in cooperation with JSC “NIIME” for special-purpose circuits produced at PJSC “Mikron”. The developed methodology includes new techniques to solve layout synthesis problems at different design flow stages, including the initial circuit decomposition, placement of logical elements, and the interconnections routing. Presented design flow makes it possible to accelerate the development of large IP blocks for reconfigurable systems-on-chip with multiple types of switching elements and system-on-chip components.

Cycle covers (III) – Compatible circuit decomposition and K5-transition minor

Let G be a 2-connected eulerian graph. For each vertex v∈V(G), let T(v) be the set of edge-disjoint edge-pairs of E(v), and, T=⋃v∈V(G)T(v). A circuit decomposition C of G is compatible with T if |E(C)∩P|≤1 for every member C∈C and every P∈T. Fleischner (1990's) wondered implicitly whether if(G,T)does not have a compatible circuit decomposition then(G,T)must have an undecomposableK5-transition-minor or its generalized transition-minor. This long-standing open problem was partially verified for various graph-minor-free families of graphs, for example, it was solved by Fleischner for planar graphs (Fleischner (1980) [7]) and solved by Fan and Zhang for K5-minor-free graphs (Fan and Zhang (2000) [6]). This transition-minor-free conjecture is now completely solved in this paper. And, as a by-product and a necessary stepping-stone, we characterize the structure of sup-undecomposable K5-minor-free graphs (G,T) in which every compatible circuit decomposition consists of a pair of Hamiltonian circuits. This result plays an important role in the proof of the main theorem and also generalizes an earlier result by Lai and Zhang (Lai and Zhang (2001) [13]).

Optimal Boolean Logic Quantum Circuit Decomposition for Spin-Torque-Based <inline-formula> <tex-math notation="LaTeX">$\boldsymbol{n}$ </tex-math> </inline-formula>-Qubit Architecture

The semiconductor industry is facing a twofold challenge at sub-nanometer level; first, the high power dissipation in irreversible computing architectures due to information loss and second, inability to handle large data due to sequential information processing. These issues create obstacles in producing the presumed low-power complex computing outcomes. The heat dissipation can be reduced by utilizing the complementary metal–oxide–semiconductor-based reversible computing architectures. However, these architectures fail to enhance the performance owing to inability to process large data. Quantum computing (QC) can circumvent these problems due to its fundamental ineffaceable characteristics of quantum mechanics-based reversible computing and parallelism. Spin-torque-based physical realization is the most suitable platform for reversible computing due to the electron spin analogous to the qubit. However, optimal quantum circuits are required to physically realize the complex Boolean logic due to spin-qubit decoherence and reduce the number of transistor switching activities for the spin generation and injection required for the spin-qubit rotation. Therefore, in this paper, optimal quantum circuit decompositions are presented with the help of developed elementary quantum library { $R_{y}^{(\theta)}$ , $R_{z}^{(\theta)}$ , $\sqrt {\text {SWAP}}$ } for the spin-torque-based QC architecture. The reversible Boolean logic performance is analyzed and compared for the conventional, reduced, and optimal decompositions on the first- and second-order transmission coefficient matrix-based spin-torque QC architecture. The results encourage to set a path toward QC-based reconfigurable complex computing systems in near future.

An efficient quantum compiler that reduces T count

Before executing a quantum algorithm, one must first decompose the algorithm into machine-level instructions compatible with the architecture of the quantum computer, a process known as quantum compiling. There are many different quantum circuit decompositions for the same algorithm but it is desirable to compile leaner circuits. A fundamentally important cost metric is the T count—the number of T gates in a circuit. For the single qubit case, optimal compiling is essentially a solved problem. However, multi-qubit compiling is a harder problem with optimal algorithms requiring classical runtime exponential in the number of qubits. Here, we present and compare several efficient quantum compilers for multi-qubit Clifford + T circuits. We implemented our compilers in C++ and benchmarked them on random circuits, from which we determine that our TODD compiler yields the lowest T counts on average. We also benchmarked TODD on a library of reversible logic circuits that appear in quantum algorithms and found that it reduced the T count for 97% of the circuits with an average T-count saving of 20% when compared against the best of all previous circuit decompositions.

Circuit Decompositions and Shortest Circuit Coverings of Hypergraphs

It is one of fundamental theorems in graph theory that every even graph has a circuit decomposition. This classical result for ordinary graphs is extended in this paper for uniform bridgeless hypergraphs if the degree of every vertex is even. One of major open problems for shortest circuit cover was a conjecture proposed by Itai and Rodeh (Automata, Languages and Programming, Lecture Notes in Computer Science, vol. 62, pp. 289–299. Springer, Berlin, 1978) that every bridgeless graph G has a circuit cover of total length at most $$|E|+|V|-1$$ . This conjecture was solved by Fan (J Combin Theory Ser B 74:353–367, 1998) for ordinary graphs, and is extended in this paper for bridgeless hypergraphs.

Response features and circuit decomposition for accelerated EM‐driven design of compact impedance matching transformers

ABSTRACTIn this letter, a procedure for low‐cost simulation‐driven design optimization of compact impedance matching transformers is presented. The proposed methodology exploits a bottom‐up design with the design requirements for the entire transformer circuit being translated into specifications for its building blocks, here, compact microstrip resonant cells. These elementary cells are optimized using response features which permits considerable numerical savings compared to conventional approach. Subsequently, the entire circuit is fine‐tuned using local response surface approximation models and response correction methods. A three‐section 50‐to‐100 Ω transformer is designed for demonstration purposes. Its optimized design is obtained at the computational cost corresponding to only 31 evaluations of the high‐fidelity electromagnetic transformer model, despite large number of geometry parameters to be adjusted (here, 15). © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2130–2133, 2016

Implementation of the quantum Fourier transform on a hybrid qubit–qutrit NMR quantum emulator

The quantum Fourier transform (QFT) is a key ingredient of several quantum algorithms and a qudit-specific implementation of the QFT is hence an important step toward the realization of qudit-based quantum computers. This work develops a circuit decomposition of the QFT for hybrid qudits based on generalized Hadamard and generalized controlled-phase gates, which can be implemented using selective rotations in NMR. We experimentally implement the hybrid qudit QFT on an NMR quantum emulator, which uses four qubits to emulate a single qutrit coupled to two qubits.

Efficient synthesis of probabilistic quantum circuits with fallback

Recently it has been shown that Repeat-Until-Success (RUS) circuits can approximate a given single-qubit unitary with an expected number of $T$ gates of about $1/3$ of what is required by optimal, deterministic, ancilla-free decompositions over the Clifford+$T$ gate set. In this work, we introduce a more general and conceptually simpler circuit decomposition method that allows for synthesis into protocols that probabilistically implement quantum circuits over several universal gate sets including, but not restricted to, the Clifford+$T$ gate set. The protocol, which we call Probabilistic Quantum Circuits with Fallback (PQF), implements a walk on a discrete Markov chain in which the target unitary is an absorbing state and in which transitions are induced by multi-qubit unitaries followed by measurements. In contrast to RUS protocols, the presented PQF protocols terminate after a finite number of steps. Specifically, we apply our method to the Clifford+$T$, Clifford+$V$, and Clifford+$\pi/12$ gate sets to achieve decompositions with expected gate counts of $\log_b(1/\varepsilon)+O(\log(\log(1/\varepsilon)))$, where $b$ is a quantity related to the expansion property of the underlying universal gate set.

Analysis of the trade-off between spatial and temporal resources for measurement-based quantum computation

In measurement-based quantum computation (MBQC), elementary quantum operations can be more parallelized than the quantum circuit model by employing a larger Hilbert space of graph states used as the resource. Thus MBQC can be regarded as a method of quantum computation where the temporal resource described by the depth of quantum operations can be reduced compared to the quantum circuit model by using the extra spatial resource described by graph states. To analyze the trade-off relationship of the spatial and temporal resources, we consider a method to obtain quantum circuit decompositions of general unitary transformations represented by MBQC on graph states with a certain underlying geometry called generalized flow. We present a method to translate any MBQC with generalized flow into quantum circuits without extra spatial resource. We also show an explicit way to unravel acausal gates that appear in the quantum circuit decomposition derived by a translation method presented in [V. Danos and E. Kashefi, Phys. Rev. A {\bf 74}, 052310 (2006)] and that represent an effect of the reduction of the temporal resource in MBQC. Finally, by considering a way to deterministically simulate these acausal gates, we investigate a general framework to analyze the trade-off between the spacial and temporal resources for quantum computation.

Efficient synthesis of universal repeat-until-success quantum circuits.

Recently it was shown that the resources required to implement unitary operations on a quantum computer can be reduced by using probabilistic quantum circuits called repeat-until-success (RUS) circuits. However, the previously best-known algorithm to synthesize a RUS circuit for a given target unitary requires exponential classical runtime. We present a probabilistically polynomial-time algorithm to synthesize a RUS circuit to approximate any given single-qubit unitary to precision ϵ over the Clifford+T basis. Surprisingly, the T count of the synthesized RUS circuit surpasses the theoretical lower bound of 3 log_{2}(1/ϵ) that holds for purely unitary single-qubit circuit decomposition. By taking advantage of measurement and an ancilla qubit, RUS circuits achieve an expected T count of 1.15 log_{2}(1/ϵ) for single-qubit z rotations. Our method leverages the fact that the set of unitaries implementable by RUS protocols has a higher density in the space of all unitaries compared to the density of purely unitary implementations.