Circuit Cost Research Articles

Efficient and cost-effective maximum power point tracking technique for solar photovoltaic systems with Li-ion battery charging

This paper presents an effective approach to achieve maximum power point tracking (MPPT) in photovoltaic (PV) systems for battery charging using a single-sensor incremental conductance (InC) method. The objective is to optimize the MPPT process while minimizing the number of sensors required. The suggested technique leverages the relationship between the PV module's output voltage and the duty cycle to automatically adjust and reach the MPP, resulting in optimal power generation. By eliminating the PV current sensor from the control circuit, the developed method reduces both the cost and size of the MPPT circuit. Compared to the conventional InC method, the developed approach demonstrates improved response speed and accuracy in steady-state operation, along with the ability to damp oscillations near the MPP. Extensive simulations using MATLAB/Simulink validate the performance of the developed technique across various environmental conditions. The results highlight the recommended method's realistic and effective MPP tracking capabilities, achieving higher efficiency (99.12 %) compared to the classical method (97.8 %) under high irradiance levels.

Energy Aware Technology Mapping of Genetic Logic Circuits.

Energy and its dissipation are fundamental to all living systems, including cells. Insufficient abundance of energy carriers─as caused by the additional burden of artificial genetic circuits─shifts a cell's priority to survival, also impairing the functionality of the genetic circuit. Moreover, recent works have shown the importance of energy expenditure in information transmission. Despite living organisms being non-equilibrium systems, non-equilibrium models capable of accounting for energy dissipation and non-equilibrium response curves are not yet employed in genetic design automation (GDA) software. To this end, we introduce Energy Aware Technology Mapping, the automated design of genetic logic circuits with respect to energy efficiency and functionality. The basis for this is an energy aware non-equilibrium steady state model of gene expression, capturing characteristics like energy dissipation─which we link to the entropy production rate─and transcriptional bursting, relevant to eukaryotes as well as prokaryotes. Our evaluation shows that a genetic logic circuit's functional performance and energy efficiency are disjoint optimization goals. For our benchmark, energy efficiency improves by 37.2% on average when comparing to functionally optimized variants. We discover a linear increase in energy expenditure and overall protein expression with the circuit size, where Energy Aware Technology Mapping allows for designing genetic logic circuits with the energetic costs of circuits that are one to two gates smaller. Structural variants improve this further, while results show the Pareto dominance among structures of a single Boolean function. By incorporating energy demand into the design, Energy Aware Technology Mapping enables energy efficiency by design. This extends current GDA tools and complements approaches coping with burden in vivo.

CMOS-Compatible High-Performance Silicon Nanowire Array Natural Light Electronic Detection System.

In this article, we propose a novel natural light detector based on high-performance silicon nanowire (SiNW) arrays. We achieved a highly controllable and low-cost fabrication of SiNW natural light detectors by using only a conventional micromachined CMOS process. The high activity of SiNWs leads to the poor long-term stability of the SiNW device, and for this reason, we have designed a fully wrapped structure for SiNWs. SiNWs are wrapped in transparent silicon nitride and silicon oxide films, which greatly improves the long-term stability of the detector; at the same time, this structure protects the SiNWs from breakage. In addition, the SiNW arrays are regularly distributed on the top of the detector, which can quickly respond to natural light. The response time of the detector is about 0.015 s. Under the illumination of 1 W·m-2 light intensity, multiple SiNWs were detected together. The signal strength of the detector reached 1.82 μA, the signal-to-noise ratio was 47.6 dB, and the power consumption was only 0.91 μW. The high-intensity and highly reliable initial signal reduces the cost and complexity of the backend signal processing circuit. A low-cost and high-performance STM32 microcontroller can realize the signal processing task. Therefore, we built a high-performance SiNW natural optoelectronic detection system based on an STM32 microcontroller, which achieved the real-time detection of natural light intensity, with an accuracy of ±0.1 W·m-2. These excellent test performances indicate that the SiNW array natural light detector in this article meey the requirements of practicality and has broad potential for application.

An efficient new design of nano-scale comparator circuits using quantum-dot technology

Traditional semiconductor-based technology has recently faced many issues, such as physical scalability constraints and short-channel properties. Much research on nano-scale designs has resulted in these flaws. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology solution for solving CMOS-related issues. The 4-dot squared cell is identified as the main feature of this technology. Also, a comparator is an essential electronic device that compares 2 voltages or currents. It is frequently employed to confirm whether an input has achieved a predefined value or not. So, the design of the QCA-based comparator is one of the interesting lines in recent studies. However, cell and area consumption limits the circuit design in the most relevant research. As a result, two efficient comparator circuits based on the inherent rules of quantum dots have been presented in this work. The proposed 1-bit design employs 35 quantum cells in a 0.04 μm2 compact layout space. Also, the proposed 2-bit design uses 173 cells in a 0.19 μm2 compact layout area. These circuits, which are built across three layers of 90-degree cells, remove the need for coplanar crossovers, ensuring accessible inputs and outputs. The presented 1-bit comparator circuit uses 3 majority gates with three inputs. The first output signal in 1-bit comparator is generated after 0.75 clock phases and in 2-bit design after 1.25 clock phases. QCADesigner-E evaluated the suggested circuits' practical accuracy, cost, and power. The results showed that the proposed designs are extremely efficient in cell and area consumption compared to the state-of-the-art designs.

Integration of Distributed Generations and electric vehicles in the distribution system

Power quality challenges are a major problem these days because of the significant increase in load demand and the existence of various reasons for disruptions in the distribution system. A voltage sag or a decrease in the magnitude of the line voltage can be brought on by rapid fluctuations in load or distribution system issues. Enhancing the grid current profile, reducing grid voltage sag, and improving other performances can all be achieved through the combination of electric vehicles with distribution generation systems. In this paper, the integration of Distributed Generation with Electric Vehicles in the distribution system has been done to enhance system performances such as true power loss index, imaginary power loss index, voltage deviation index, short circuit current index, cost function, and environmental impact reduction index for 16 bus distribution system in constant impedance, constant current, and constant power load models, or ZIP load models through proper location, sizing, coordinated controlling, and types of Distributed Generation and Electric Vehicle pairs for both charging and discharging modes by adopting Hybrid Genetic Algorithm - Monte Carlo Simulation optimization methodologies. This study's primary goal is to determine the optimal distribution generation and electric vehicle pairing to improve the aforementioned parameters, which will assist researchers in their future planning. Researchers, industry professionals, scientists, and individuals working with Distributed Generation and Electric vehicles in the smart grid will find this statement to be of great use.

Variable-Frequency Control for Totem-Pole Bridgeless Power Factor Correction Converter to Achieve Zero-Voltage Switching Without Zero-Crossing Detection Circuits

The totem-pole bridgeless power factor correction (PFC) converter, known for its advantages including simple topology, capability for zero-voltage switching (ZVS), and low common mode interference, presents an opportunity to enhance the efficiency and environmental friendliness of power systems. However, these converters have issues such as ZVS, requiring zero-crossing detection (ZCD) under circuits’ critical continuous mode (CRM) or additional auxiliary resonant circuits, resulting in increased circuit costs and control complexity. Therefore, this paper proposes a variable switching frequency digital control method to achieve ZVS under a wide operating range without ZCD circuits. At the same time, under the premise of ZVS, an interleaved parallel scheme is adopted to further minimize the current ripple and enhance the quality of the current waveform. Finally, an experimental 2 kW two-phase interleaved totem-pole bridgeless PFC converter prototype is designed to verify that the proposed method is correct and effective. The experimental prototype can reach an efficiency of 97.78%.

Analysis of External Trip Attraction for Proving Ground at ITS

The development of research in the automotive field is characterized by an increasing number of automotive competitions involving college students. The results of this research have been tested around the campus environment without specialized testing facilities such as a Proving Ground, thus prompting ITS to initiated to build a Proving Ground. The construction of a Proving Ground at ITS will also be utilized as a go-kart activity. The purpose of this research is to develop a trip attraction model and to determine the factors that influence trip atrraction decisions to the Proving Ground to be built at ITS. The method used is Multiple Linier Regression Analysis. The independent variables used in this research are Circuit Length (X1), Travel Distance (X2), Travel Time (X3) and Cost (X4). And the independent variables used to determine the gokart sport are Travel Distance (X1), Travel Time (X2) and Cost (X3). Meanwhile, the dependent variable is the trip attraction to visit the ITS Proving ground, which can be used as an exercise for automotive researchers or visitor to gokart sports. The results of the regression equation model of trip attraction to the Proving Ground are Y = 36,589 + 6,412 X1 - 0,584 X3. In this study, the most influential variables are Circuit Length and Travel Time with R² value in the calculation obtained at 0,297. Furthermore, the results of the regression equation model of trip attraction for gokart sport visitors are Y = 20,569 – 0,08X1 – 0,011X2 – 0,00009X3. In this study, the most influential variables are Travel Distance and Travel Time with the R² value in the calculation obtained at 0,161.

Improved dual-threshold quantum image segmentation algorithm and simulation* *This work was supported by National Natural Science Foundation of China (No.61772295), Key Projects of Chongqing Natural Science Foundation Innovation Development Joint Fund (CSTB2023NSCQ-LZX0139), Open Fund of Advanced Cryptography and System Security Key Laboratory of Sichuan Province (Grant No. SKLACSS-202208) and Technology Research Program of Chongqing Municipal Education Commission (Grant no. KJZD-M202000501).

Quantum image segmentation algorithm is crucial for quantum image processing. In this paper, a dual-threshold quantum image segmentation algorithm is designed and simulated in IBM Quantum Experience (IBM Q) platform, which can segment a complex image into three parts using fewer quantum bits. In our algorithm, given a high threshold and a low threshold, grayscale values larger than the high threshold are set to the high threshold and grayscale values smaller than the low threshold are set to the low threshold, with no change for the part between the two thresholds. Then we use a low-cost quantum comparator and design a complete and scalable quantum image segmentation circuit. Analysis of the circuit cost shows that the quantum gates required for the circuit are only related to the grayscale range q and are independent of the image size. The feasibility of the algorithm and the correctness of the quantum circuit are verified by simulation in IBM Q platform, and finally the MSE, PSNR AND SSIM value of the image is analyzed to prove the effectiveness of the segmentation algorithm.

Maximizing quantum-computing expressive power through randomized circuits

In the noisy intermediate-scale quantum era, variational quantum algorithms (VQAs) have emerged as a promising avenue to obtain quantum advantage. However, the success of VQAs depends on the expressive power of parametrized quantum circuits, which is constrained by the limited gate number and the presence of barren plateaus. In this paper, we propose and numerically demonstrate an approach for VQAs, utilizing randomized quantum circuits to generate the variational wave function. We parametrize the distribution function of these random circuits using artificial neural networks and optimize it to find the solution. This random-circuit approach presents a trade-off between maximizing the expressive power of the variational wave function and minimizing the associated time cost, specifically the sampling cost of quantum circuits. Given a fixed gate number, we can systematically increase the expressive power by extending the quantum-computing time. With a sufficiently large permissible time cost, the variational wave function can approximate any quantum state with arbitrary accuracy. Furthermore, we establish explicit relationships between expressive power, time cost, and gate number for variational quantum eigensolvers. These results highlight the promising potential of the random-circuit approach in achieving a high expressive power in quantum computing. Published by the American Physical Society 2024

A novel feature selection method based on quantum support vector machine

Feature selection is critical in machine learning to reduce dimensionality and improve model accuracy and efficiency. The exponential growth in feature space dimensionality for modern datasets directly results in ambiguous samples and redundant features, which can severely degrade classification accuracy. Quantum machine learning offers potential advantages for addressing this challenge. In this paper, we propose a novel method, quantum support vector machine feature selection (QSVMF), integrating quantum support vector machines with multi-objective genetic algorithm. QSVMF optimizes multiple simultaneous objectives: maximizing classification accuracy, minimizing selected features and quantum circuit costs, and reducing feature covariance. We apply QSVMF for feature selection on a breast cancer dataset, comparing the performance of QSVMF against classical approaches with the selected features. Experimental results show that QSVMF achieves superior performance. Furthermore, the Pareto front solutions of QSVMF enable analysis of accuracy versus feature set size trade-offs, identifying extremely sparse yet accurate feature subsets. We contextualize the biological relevance of the selected features in terms of known breast cancer biomarkers. This work highlights the potential of quantum-based feature selection to enhance machine learning efficiency and performance on complex real-world data.

Point Calculation Detection System Based on In Suit Convolution Transistor for Clinical Diagnosis of Heart Disease

AbstractElectrocardiograph signals reflect the current state of the heart and have great significance to the clinical diagnosis of the heart. Convolutional neural networks perform excellently in electrocardiograph pattern recognition. However, CNNs processing ECG signals need to convert them from 1D to 2D, leading to additional circuit and time costs in hardware. Here, a convolution organic transistor (COT) is proposed for monitoring the ECG with CNNs. Based on the surface electric field effect and trap effect, COT can directly process 1D ECG data without complex preprocessing. It can complete the convolution calculation of ECG signals ≈20 000 times per second in theory and reduce the number of devices by 83% compared to conventional arrays. Further, actual ECG signals are measured and input into the COT, which can initially recognize the type of ECG abnormality. Finally, a point calculation detection system is established with 96.2% recognition accuracy in the five‐heartbeat classification task by combining the 1D CNN.

Compact Instruction Set Extensions for Dilithium

Post-quantum cryptography is considered to provide security against both traditional and quantum computer attacks. Dilithium is a digital signature algorithm that derives its security from the challenge of finding short vectors in lattices. It has been selected as one of the standardizations in the NIST post-quantum cryptography project. Hardware-software co-design is a commonly adopted implementation strategy to address various implementation challenges, including limited resources, high performance, and flexibility requirements. In this study, we investigate using compact instruction set extensions (ISEs) for Dilithium, aiming to improve software efficiency with low hardware overheads. To begin with, we propose tightly coupled accelerators that are deeply integrated into the RISC-V processor. These accelerators target the most computationally demanding components in resource-constrained processors, such as polynomial generation, Number Theoretic Transform (NTT), and modular arithmetic. Next, we design a set of custom instructions that seamlessly integrate with the RISC-V base instruction formats, completing the accelerators in a compact manner. Subsequently, we implement our ISEs in a chip design for the Hummingbird E203 core and conduct performance benchmarks for Dilithium utilizing these ISEs. Additionally, we evaluate the resource consumption of the ISEs on FPGA and ASIC technologies. Compared to the reference software implementation on the RISC-V core, our co-design demonstrates a remarkable speedup factor ranging from 6.95 to 9.96. This significant improvement in performance is achieved by incorporating additional hardware resources, specifically, a 35% increase in LUTs, a 14% increase in FFs, 7 additional DSPs, and no additional RAM. Furthermore, compared to the state-of-the-art approach, our work achieves faster speed performance with a reduced circuit cost. Specifically, the usage of additional LUTs, FFs, and RAMs is reduced by 47.53%, 50.43%, and 100%, respectively. On ASIC technology, our approach demonstrates 12, 412 cell counts. Our co-design provides a better tradeoff implementation on speed performance and circuit overheads.

Quantum Simulation of the First-Quantized Pauli-Fierz Hamiltonian

We provide an explicit recursive divide-and-conquer approach for simulating quantum dynamics and derive a discrete first-quantized nonrelativistic QED Hamiltonian based on the many-particle Pauli-Fierz Hamiltonian. We apply this recursive divide-and-conquer algorithm to this Hamiltonian and compare it to a concrete simulation algorithm that uses qubitization. Our divide-and-conquer algorithm, using lowest-order Trotterization, scales for fixed grid spacing as O~(ΛN2η2t2/ϵ) for grid size N, η particles, simulation time t, field cutoff Λ, and error ϵ. Our qubitization algorithm scales as O~(N(η+N)(η+Λ2)tlog(1/ϵ)). This shows that even a naive partitioning and low-order splitting formula can yield, through our divide-and-conquer formalism, superior scaling to qubitization for large Λ. We compare the relative costs of these two algorithms on systems that are relevant for applications such as the spontaneous emission of photons and the photoionization of electrons. We observe that for different parameter regimes, one method can be favored over the other. Finally, we give new algorithmic and circuit-level techniques for gate optimization, including a new way of implementing a group of multicontrolled-X gates that can be used for better analysis of circuit cost. Published by the American Physical Society 2024

Lowering the cost of quantum comparator circuits

Quantum comparators hold substantial significance in the scientific community as fundamental components in a wide array of algorithms. In this research, we present an innovative approach where we explore the realm of comparator circuits, specifically focussing on three distinct circuit designs present in the literature. These circuits are notable for their use of T-gates, which have gained significant attention in circuit design due to their ability to enable the utilisation of error-correcting codes. However, it is important to note that T-gates come at a considerable computational cost. One of the key contributions of our work is the optimisation of the quantum gates used within these circuits. We articulate the proposed circuits employing Clifford+T gates, facilitating error correction code implementation. Additionally, we minimise T-gate usage, thereby reducing computational costs and fortifying circuit robustness against errors and environmental disturbances-essential for mitigating the effects of internal and external noise. Our methodology employs a bottom-up examination of comparator circuits, initiating with a detailed study of their gates. Subsequently, we systematically dissect the functions of these gates, thereby advancing towards a comprehensive understanding of the circuit’s overall functionality. This meticulous examination forms the foundation of our research, enabling us to identify areas where optimisations can be made to improve their performance.

An efficient and closed-loop approach to convert silicon tetrachloride to silicon nanospheres anode materials via hydrogen thermal plasma

Solar energy is growing due to global “carbon peak and neutrality” targets. Silicon tetrachloride (SiCl4) is mass-produced from polycrystalline silicon (p-Si), an important solar material. Therefore, an efficient and cost-effective process is needed to transform this byproduct into a higher-value product. In this work, we present a new approach utilizing hydrogen thermal plasma (H-plasma) to directly convert SiCl4 into silicon nanospheres (Si NSs) and analyzed the reaction process by optical emission spectroscopy diagnostic. The Si NSs produced possess a spherical shape, with a smooth surface and a compact interior. With a diameter of ∼90 nm, Si NSs exhibits exceptional electrochemical performance when used as anode materials. Significantly, H-plasma is expected to be combined with the current tail gas recovery system of the p-Si industry to form a closed circuit, increasing yield and lowering costs. Our work demonstrates economically viable and widespread nano-silicon fabrication for sustainable energy solutions.

Miura origami based reconfigurable polarization converter for multifunctional control of electromagnetic waves

Polarization is one of the basic characteristics of electromagnetic (EM) waves, and its flexible control is very important in many practical applications. At present, most of the multifunction polarization metasurfaces are electrically tunable based on PIN and varactor diodes, which are easy to operate and have strong real-time performance. However, there are still some problems in them, such as few degrees of freedom of planar structure control, complex circuit, bulky sample, and high cost. In view of these shortcomings, this paper proposes a Miura origami based reconfigurable polarization conversion metasurface for multifunctional control of EM waves. The interaction between the electric dipoles is changed by adjusting the folding angle θ, thereby tuning the operating frequency of the polarization conversion and the polarization state of the reflected wave. This mechanical control method brings more degrees of freedom to manipulate EM waves. And the processed sample is with lightweight and low cost. To verify the performance of the proposed origami polarization converter, a Miura origami structure loaded with metal split rings is designed and fabricated. The operating frequency of the structure can be tuned in different folding states. In addition, by controlling the folding angle θ, linear-to-linear and linear-to-circular polarization converters can be realized at different folding states. The proposed Miura origami polarization conversion metasurface provides a new idea for reconfigurable linear polarization conversion and multifunctional devices.

Notice of Violation of IEEE Publication Principles: Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate

Notice of Violation of IEEE Publication Principles “Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate” by Suhaib Ahmed and Syed Farah Naz in IEEE Transactions on Circuits and Systems II: Express Briefs After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE’s Publication Principles. This paper contains significant portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. “Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata” By Haotian Chen, Hongjun Lv, Zhang Zhang, Xin Cheng and Guangjun Xie in Journal of Circuits, Systems, and Computers, Vol. 28, No. 8, 2017 The advantages such as high operating frequency (in the range of few THz), low power dissipation, small size and high density in the nano regime has led to the application of Quantum dot Cellular Automata (QCA) in designing various digital circuits. In this brief, an ultra-efficient two input XOR gate design in QCA is proposed. It is a single layer design consisting of only 9 cells with no crossover and operating on cell to cell interaction. The functionality of the proposed gate has been verified at both physical and simulation level. In addition to this, fault tolerance to single cell missing defect, single cell addition defect and single cell displacement defect of the proposed XOR gate has also been presented. Based on the performance evaluation, it is seen that the proposed XOR gate has least cell count, least area and least latency which in turn leads to least circuit cost. Also, the proposed design dissipates least energy. The applicability of proposed XOR gate has also been investigated by designing various cost efficient digital circuits such as full adder, parity checker, etc.

InGaAs/AlInAsSb avalanche photodiodes with low noise and strong temperature stability

High-sensitivity avalanche photodiodes (APDs) are used to amplify weak optical signals in a wide range of applications, including telecommunications, data centers, spectroscopy, imaging, light detection and ranging, medical diagnostics, and quantum applications. This paper reports antimony-based separate absorption, charge, and multiplication structure APDs on InP substrates. Al0.7In0.3As0.79Sb0.21 is used for the multiplier region, and InGaAs is used as the absorber. The excess noise is comparable to that of silicon APDs; the k-value is more than one order of magnitude lower than that of APDs that use InP or InAlAs for the gain region. The external quantum efficiency without an anti-reflection coating at 1550 nm is 57%. The gradient of the temperature coefficient of avalanche breakdown voltage is 6.7 mV/K/μm, which is less than one-sixth that of InP APDs, presenting the potential to reduce the cost and complexity of receiver circuits. Semi-insulating InP substrates make high-speed operation practical for widely reported AlxIn1−xAsySb1−y-based APDs.

Extendable Multiport High Step-Up DC–DC Converter for Photovoltaic-Battery Systems With Reduced Voltage Stress on Switches/Diodes

In the standalone photovoltaic (PV)-battery power system, a multiport converter is more desirable than several single-input converters as it has advantages of the simpler circuit, higher efficiency, and lower cost. In this paper, a novel structure based on a non-isolated high step-up multi-port converter (MPC) is proposed. The proposed MPC has the capability of providing high voltage gain and low normalized peak inverse voltage (NPIV) across semiconductor devices. Maximum power point tracking (MPPT) algorithm can be applied for each PV input source, which is an effective method to prevent mismatches among PV modules. Different from the existing extendable MPCs, the proposed MPC can extend both unidirectional input ports and bidirectional ports to involve more types of renewable energy sources and energy storage devices. Continuous input currents and modularity are the other profits of the proposed MPC. Various operating modes, steady-state analysis, and design considerations have been discussed. Comparison results verify the above advantage of the proposed MPC. Finally, a 240W laboratory prototype is designed to validate the performance of the proposed MPC.

Consumer Electronics Product Manufacturing Time Reduction and Optimization Using AI-Based PCB and VLSI Circuit Designing

Circuit design plays an essential role in all consumer electronics products. Printed circuit board (PCB) and very-largescale integration (VLSI) circuit designing requires optimization of the electronic components placement and wire routing to connect the components. Currently, circuit routing processes have been performed manually by experts, which greatly increases the cost of human resources and time. Such heuristic circuit designs are not optimized and may have errors, which is why automated circuit routing algorithms are important. However, it is difficult to obtain an optimal solution in circuit routing as it is an NPhard problem. In addition, poor circuit routing increases the wire length of the circuit, which causes an increase in circuit cost and weight as well as performance degradation. In order to achieve routing optimization, many technologies have been proposed, in which some have applied artificial intelligence (AI) to improve the overall performance and reduce the designing time. Accordingly, in this paper, routing problems in PCB and VLSI are explained, and proposed technologies to solve these routing problems are introduced. Especially, a detailed investigation and analysis of AI technologies grafted into circuit routing algorithms are explained, and the considerations for AI-based routing algorithms are presented.