Circuit Board Assembly Research Articles

Effects of component placement on solder joint through-life reliability

Solder joint fatigue is a major concern in circuit board assemblies. A batch of FR4 test boards with different component layouts was assembled. These test boards were then put into an environmental chamber and subjected to thermal cycling. During the test, the samples were removed from the chamber at given intervals and examined by acoustic micro imaging. The solder joint reliability from origin to failure was obtained by processing these acoustic micro imaging data. The impact of different floor plans and component layouts on solder joint reliability were analysed. Remarkably, the results show that the floor plan and component layout have significant influence on solder joint reliability. Components placed in a mirrored configuration in a circuit board assembly have lower reliability than non-overlapping configurations and single-sided assembly. Finally, a stress-based finite element model with two simulation scenarios was carried out to correlate reliability findings with real experimental results.

Modeling of Errors Counting System for PCB Soldered in the Wave Soldering Technology

PartnerTech provides printed circuit board (PCB) assembly on request. Wired elements are assembled in through-hole technology and soldered on the wave soldering machine. The PCB with inserted elements is passed across the pumped wave of melted solder. Typically this process is accompanied by some class of defects like cracks, cavities, wrong solder thickness and poor conductor. In PartnerTech Ltd. another type of defects was observed: dispersion of small droplets of solder around holes. Quality assurance department plans to optimize the process in order to reduce the number of defects. In the first stage, it was necessary to develop a methodology for counting defects. This paper presents experimental design and analysis related to this project.

A Computable Model for PCB Assembly Optimization Based on Polychromatic Sets

A modeling methodology is presented for printed circuit board(PCB) assembly optimization based on polychromatic sets(PS) theory. A computable model framework with hierarchical structure includes three layers, which are set layer(SL), logic layer(LL) and numerical layer(NL). Based on the hierarchical model and the mapping relationship among each layer, a computable model is formulated to describe the PCB assembly optimization problem in multiple PCB assembly tasks and multiple machines. The computable model not only involves various computation parameters, complicate constraint relationships such as process constraints, resource constraints and so on in PCB assembly optimization, but also describes the shortage of component, machine failure, order change and other uncertain factors. The optimization problems of PCB assembly in low-volume environment and multiple tasks can be solved efficiently.

Selection of the optimal configuration for a flexible surface mount assembly system based on the interrelationships among the flexibility elements

Flexibility has been widely recognized as a key competitive factor for manufacturing firms coping with the increasingly turbulent manufacturing environment today. Establishing a flexible surface mount assembly (SMA) system is critical for organizations to achieve a cost-effective assembly and gain competitive advantages in the printed circuit board (PCB) assembly industry. To find a practicable operating strategy, a multi-criteria decision-making framework that combines the analytic network process (ANP) with the consistent fuzzy preference relations (CFPR) is proposed to explore the interrelationships among the six dimensions and twenty-one criteria of manufacturing flexibility and resolve the uncertainty and divergence between decision-makers with the least amount of pairwise comparisons. Based on the results of prior analysis, an optimum configuration of a flexible SMA system is suggested for the capacity investment intended by a Taiwan electronics manufacturing service (EMS) provider to quickly respond to dynamic production requirements.

The Disassembly Process and Apparatus of Waste Printed Circuit Board Assembly for Reusing the Components

Printed Circuit Board Assembly (PCBA), is an important basic part of Electric and Electronic Equipment, which has lots of high-value components and toxic substances. Normally, when Electric and Electronic Equipment (EEE) is scraped, some components on waste PCBA still keep good performances. Therefore, it is feasible and economical to environment-friendly reuse the high-value components on waste PCBA. In order to guarantee the quality of the disassembled components, the components reuse-oriented disassembly process is proposed, in which the mechanical and physical characteristics of solder and the joint type of PCBA are considered comprehensively. In the process, through the analysis and measurement of the temperature distribution of PCBA, the optimized heating mode and heating temperature curve can be drawn up for the different joint type of PCBA. For getting the disassembly mode of PCBA, the disassembly force and separating displacement of components on PCBA are defined and the disassembly energy models for different kinds of components are set up. On the basis of the heating mode, heating temperature curve and disassembly energy, two kinds of disassembly apparatus and a performance testing procedure for certain kinds of old components are developed. In the end the components reuse-oriented disassembly process parameters are optimized to get a high separation ratio and reuse ration of components with orthogonal test.

Random vibration reliability of BGA lead-free solder joint

Solder joint fatigue failure under vibration loading has been a great concern in microelectronic industry. High-cycle fatigue failure of lead-free solder joints has not been adequately addressed, especially under random vibration loading. This study aims to understand the lead-free solder joint behavior of BGA packages under different random vibration loadings. At first, non-contact TV Laser holography technology was adopted to conduct experimental modal analysis of the test vehicle (printed circuit board assembly) in order to understand its dynamic characteristics. Then, its first order natural frequency was used as the center frequency and narrow-band random vibration fatigue tests with different kinds of acceleration power spectral density (PSD) amplitudes were respectively carried out. Electrical continuity through each BGA package is monitored during the vibration event in order to detect the failure of package-to-board interconnects. The typical dynamic voltage histories of failed solder joints were obtained simultaneously. Thirdly, failed solder joints were cross-sectioned and metallurgical analysis was applied to investigate the failure mechanisms of BGA lead-free solder joints under random vibration loading. The results show that the failure mechanisms of BGA lead-free solder joint vary as the acceleration PSD amplitude increases. Solder joint failure locations are changed from the solder bump body of the PCB side to the solder ball neck, finally to the Ni/intermetallic compound (IMC) interface of the package side. The corresponding failure modes are also converted from ductile fracture to brittle fracture with the increase of vibration intensity.

Influence of sodium chloride and weak organic acids (flux residues) on electrochemical migration of tin on surface mount chip components

The electrolytic properties of sodium chloride and no-clean solder flux residue, and their effects on electrochemical migration and dendrite growth on surface mount chip capacitors were investigated. The leakage current dependency on concentration of contaminants was measured by a solution conductivity method and compared with current measurements using DC voltage. The effect of electrolyte concentration and potential bias on the probability of electrochemical migration was investigated using a water droplet method on chip capacitors. The results from leakage current and conductivity measurement showed a difference which is caused by polarization effects, and demonstrated existing issues when indexing contamination levels on printed circuit board assemblies using a standardised solvent extract method. The experimental results showed that dendrite growth was dependent on the type and amount of contamination. The probability of migration becomes less dependent on the amount of contamination for sodium chloride at high concentrations. However, for organic acids from flux residues the migration probability shows an abrupt decrease with increasing concentration, which is attributed to a pH change in the condensed electrolyte phase.

Effect of solder flux residue on the performance of silicone conformal coatings on printed circuit board assemblies

Conformal coatings are applied on printed circuit board assemblies (PCBAs) in order to protect the assembly from environmental influence and silicone-based coating is commonly used. A systematic study on the performance of silicone conformal coating in connection with process-related contaminants is the focus of this paper. Different test substrates such as plain laminate surface and a test PCBA with and without conformal coatings were exposed to high humid environment at ambient temperature and the performance of the coating was evaluated using various parameters such as increase in leakage current across the components, morphology of the coating, and analysis of dendrite formation due to electrochemical migration under the coating. The morphology of the coating before and after exposure was investigated using scanning electron microscopy, and energy dispersive X-ray spectroscopy. Results show that the presence of flux residues greatly influences the electrical functionality of the components and also degrades the performance of the coatings compared to the clean substrates.

Failure mechanism of solder bubbles in PCB vias during high‐temperature assembly

PurposePb‐free soldering challenged printed circuit board (PCB) assembly with high temperature. The purpose of this paper is to explain the failure mechanism of printed circuit board (PCB) assembly with solder bubbles of vias to avoid the problems of via‐drilling defects and solder joint failure.Design/methodology/approachThe failure of PCB vias with solder bubbles was investigated through cross sections and SEM microstructure inspection, TMA measurement, moisture absorption analysis and DSC measurement. The moisture absorption and CTE of FR4 laminate matched with manufacturing requirement to avoid the effects of solder bubbles. The effects of via drilling with a dull drill bit were compared to that with a new drill bit.FindingsThe moisture absorbed inside holes of via plating layers could be exposed to induce solder bubbles during Pb‐free soldering assembly and dull drill bits should be prevented during the drilling process to avoid the no‐bearing drilling effects.Originality/valueThe failure of PCB vias is not only involved in the voiding in solder joints but manufacturing processes of PCB. The paper designs an approach to analyse the properties of PCB materials and the drilling effects of vias to find out the mechanism resulting in solder bubbles of vias. The problem of drill bits should be considered to prevent the moisture absorbed in drilling vias with defects.

An MILP model and clustering heuristics for LED assembly optimisation on high-speed hybrid pick-and-place machines

This paper deals with a scheduling optimisation problem arising in printed circuit board (PCB) assembly. In one class of PCB assembly, light-emitting diodes are to be assembled into the placement locations on PCBs by a machine with multiple pick-and-place heads. The scheduling optimisation problem is to determine the assembly sequence of placement locations and the assignment of pick-and-place heads for locations so as to minimise the assembly time. We formulate it as a mixed integer linear programming model. To solve the problem efficiently, we classify the PCBs into two types. For the first type of PCBs, on which the locations are linearly arranged, a constructive heuristic is proposed based on the analysis of the best next location after a location is assembled. For the second type of PCBs, on which the locations are circularly arranged, a heuristic based on clustering strategy and path relinking method is proposed. Computational experiments show that the solutions obtained by the two heuristics make 2.32 and 6.82% improvements averagely for the PCBs with linearly and circularly arranged locations, respectively, as compared to the solutions used in real production, and they are also better than those obtained by a hybrid genetic algorithm.

New operators on triangular intuitionistic fuzzy numbers and their applications in system fault analysis

Triangular intuitionistic fuzzy numbers (TIFNs) are one of the extensions of intuitionistic fuzzy sets and triangular fuzzy numbers, and they have been applied to fault-tree analysis in many studies. The arithmetic operations and logic operations of TIFNs have been addressed in relevant studies. However, the arithmetic operations of TIFNs in these studies all have defects. Based on information from the existing studies, this paper proposes new arithmetic operations and logic operators for TIFNs and applies them to fault analysis of a printed circuit board assembly system. The proposed operations are then compared to the existing ones to confirm their feasibility and rationality.

Advanced Methodologies for Developing Improved Potted Smart Munitions for High-G Applications

Potted electronics are becoming more common in precision-guided smart munitions designs due to the requirements for miniaturization and structural-robustness. In most of these applications, the potted electronics are inactive for most of their lifetime and may be stored without environmental (temperature and humidity) controls for up to 20 yr. The uncontrolled environment for smart munitions however makes the thermal management task especially difficult due to the coefficient of thermal expansion (CTE) mismatch that can exist between the potting material and the electronic components. In this paper, we will do the following: (1) present a methodology being developed for reducing the thermal stresses to the potted electronics used in uncontrolled environments by encapsulating the circuit board assembly (CBA) with a thin polymer layer which has been precisely formed to conform to the imprecisely shaped, as-populated, CBA. The protective polymer layer will be both flexible and soft enough to protect the CBA components from damage caused by thermal expansion mismatches, but not degrade the structural support that the potting provides during high-g force projectile launches, (2) discuss how the protective polymer layer methodology can also be used to lessen in-circuit board crosstalk, improve shielding from external RF interference, control tin-whisker growth, and enhance moisture barrier properties and thermal management for CBAs, and (3) demonstrate how to improve the smart munitions survivability under extreme high-g applications through the use of syntactic foams and material characterization before and after accelerated temperature-cycling and thermal-aging tests.

Solder Paste Scooping Detection by Multilevel Visual Inspection of Printed Circuit Boards

In this paper, we introduce an automated Bayesian visual inspection framework for printed circuit board (PCB) assemblies, which is able to simultaneously deal with various shaped circuit elements (CEs) on multiple scales. We propose a novel hierarchical multi-marked point process model for this purpose and demonstrate its efficiency on the task of solder paste scooping detection and scoop area estimation, which are important factors regarding the strength of the joints. A global optimization process attempts to find the optimal configuration of circuit entities, considering the observed image data, prior knowledge, and interactions between the neighboring CEs. The computational requirements are kept tractable by a data-driven stochastic entity generation scheme. The proposed method is evaluated on real PCB data sets containing 125 images with more than 10 000 splice entities.

Application of Sequence-Dependent Traveling Salesman Problem in Printed Circuit Board Assembly

Optimization issues regarding the automated assembly of printed circuit boards attracted the interest of researchers for several decades. This is because even small gains in assembly time result in very important benefits in mass production. In this paper, the focus is on a particular placement machine type that has a rotational turret and a stationary component magazine. So far, this type of machine received little attention among the researchers. In this paper, the feeder configuration, placement sequencing, and assembly time minimization problems are formulated explicitly and completely (without simplifying assumptions) using nonlinear integer programming. In addition, the placement sequencing problem is shown to be a recently introduced new generalization of the traveling salesman problem (the sequence-dependent traveling salesman). These formulations show the complexity of the problems and the need for effective heuristic designs for solving them. We propose three heuristics that improve previously suggested solution methods and give comparable results when compared to simulated annealing that is a widely accepted good performing metaheuristic on combinatorial optimization problems. The heuristics are experimentally shown to improve previous methods significantly in assembly time that implies a huge economic benefit. The heuristics proposed could also be applied to other placement machines with similar operation principles.

Efficient multi-level modeling technique for determining effective board drop reliability of PCB assembly

In this paper, we develop a new and computationally efficient multi-level approach to investigate board level drop reliability of printed circuit board (PCB) assembly. The approach is composed of two levels of finite element (FE) simulations: solder joint level and board level. Initially, static simulations of the solder joint level were used to obtain the homogenized property of the solder-underfill interconnection. This was followed by explicit FE simulations of the board assembly. The results of the proposed multi-level approach were compared with commonly adopted FE analysis and good correspondence is revealed between the two. Through drop test simulations that involved fifteen Integrated Circuit (IC) packages, as per the standard JESD22-B111 of Joint Electron Device Engineering Council (JEDEC), the critical board locations and interconnection in each location were identified and analyzed. The results reveal that peak stresses occur at the corner of the central package. They also show that the interconnection stresses result mainly from the dynamic bending of the PCB.

Detection of capacitor electrolyte residues with FTIR in failure analysis

Detecting leakage from liquid aluminum electrolytic capacitors is not easy. Typically there is very little evidence of leakage because the electrolyte is volatile and leaves behind only trace residues. Liquid aluminum electrolytic capacitors are known to cause catastrophic failures where there is complete loss of functionality due to a short or open circuit. In the study presented in this paper, printed circuit board assemblies from a test and measurement system used in a clean room environment failed. Two units failed, causing burning in a particular area on the printed circuit board assembly. The failure area included several surface mount liquid aluminum electrolytic capacitors, and several others were mounted very close to the burnt region. A study was initiated to evaluate the cause of failure. Careful optical inspection revealed some residues on the outer side of the rubber seals of two of the electrolytic capacitors. Through using Fourier transform infrared analysis and a process of experimentation and analysis, it was determined that the residues were produced by liquid electrolyte that leaked out of the capacitor at some point in the field. The leaked electrolyte that came out of the capacitor was believed to be the cause of failure that led to the burning of the printed circuit board assembly.

Design for Solder Joint Fatigue Life of BGA Package Subject to Mechanical Environment

There has been a dramatic proliferation of research concerned with thermal stress in electronic package for the last three decades. Moreover, reviewing the mechanical bending during printed circuit board (PCB) assembly has become important in the reliability assessment of modern electronic systems. The primary research demonstrates that the assessment approach can be applied successfully to the design model of a ball grid array (BGA) package with a more complete and accurate assessment model for solder joint fatigue life under mechanical bending. Previous research has focused mostly on the thermal analysis in electronic packages; however, most modern portable electronic products used in mobile devices, personal digital assistants, and aircraft have to endure extreme environments that involve not only thermal but also mechanical bending conditions. Initially, mechanical bending tests were conducted to demonstrate the reliability of the electronic packaging during the manufacturing and shipping process. Currently, the microelectronic packaging faces mechanical bending when everyone uses his or her Smartphones. The mechanical bending occurs when the user touches the screen on the Smartphone. Therefore, interest in the mechanical bending of BGA packaging has increased with the uptake in mobile device use. In this research, the analytical solution and finite element analysis (FEA) are both presented to investigate the solder joint fatigue life. The analytical solution is presented for a PCB assembly subjected to mechanical bending by taking the axial stress, shear stress, and moment of the solder joints with discontinuity function into account. A FEM is proposed to analyze the solder joint fatigue life and to investigate the reliability of solder joints in BGA packaging subjected to mechanical bending.

基于蚁群算法的PCB组装过程优化<br>PCB Assembly Optimization Based on Ant Colony Algorithm

在转塔式贴片机的印制电路板(PCB)组装过程中，元件贴装顺序和装载有不同类型元件的供料器在供料架上的布置是影响转塔式贴片机贴装时间的主要因素。在分析实际工程应用的基础上，建立了转塔式贴片机上PCB组装的集成优化模型，对蚁群算法进行了改进，提出了相互通信的最大–最小蚂蚁算法，用两种不同职能的蚂蚁相互协作，以元件组装顺序来驱动供料器布置，引导蚂蚁实现元件贴装顺序的优化，而执行蚂蚁根据引导蚂蚁选择元件的结果来实现供料器布置优化。算法可对元件贴装顺序和供料器的布置进行同时优化，从而提高转塔式贴片机上PCB组装的效率。最后通过实例验证了算法的有效性。 The component placement sequence and feeder arrangement are the critical factors determining assembly time of chip shooter (CS) machine. In addition, the different size of component and different arrangement strategy affect the feeder arrangement and component placement sequence. Based on the engineering analysis, an integrated optimization model of printed circuit board (PCB) assembly for CS machine is established. According to the parallel placement character of CS machine, “Max-Min Ant Colony Algorithm with Communication function” is designed based on traditional Ant Colony Algorithm. The idea that two ants with different duties collaborate to solve the optimization problem is presented. Guide ants optimize placement sequence while executant ants optimize feeder arrangement according to the components placement sequence. The component placement sequence and feeder arrangement are optimized simultaneously.

Key Technology of Disassembling Waste Printed Circuit Board Assembly for Components Reuse

Waste printed circuit board assembly(PCBA),which has lots of high-value components and toxic substances,is a key unit in the disposal of waste electric and electronic equipment(WEEE).Up to now material recycling is still the main disposal method of waste PCBA.Studies show that the components still keep good condition when PCBA retired.In order to guarantee the reusability of the disassembled components,the components reuse-oriented disassembly technology is studied,in which the key technologies of heating and disassembly are discussed in detail.The key heating technology is researched for the different joint type of PCBA,the temperature distribution of surface mount devices(SMD) major PCBA is studied quantitatively.For getting the suitable disassembly mode of PCBA,the disassembly acceleration and separating displacement of components on PCB are defined and the disassembly energy models for different kinds of components are set up.On the basis of the heating and disassembly technology,two kinds of disassembly apparatus are developed for through-hole devices(THD) major PCBA and SMD major PCBA respectively.Also,the performance testing technology of certain kinds of disassembled components,such as SMD,THD,resistor and capacitance,is proposed.In the end the disassembly parameters are optimized to achieve high the separation ratio and reuse ration of components with orthogonal experiment.

Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.