Circuit Blocks Research Articles

A gate tunable transmon qubit in planar Ge

Gate-tunable transmons (gatemons) employing semiconductor Josephson junctions have recently emerged as building blocks for hybrid quantum circuits. In this study, we present a gatemon fabricated in planar Germanium. We induce superconductivity in a two-dimensional hole gas by evaporating aluminum atop a thin spacer, which separates the superconductor from the Ge quantum well. The Josephson junction is then integrated into an Xmon circuit and capacitively coupled to a transmission line resonator. We showcase the qubit tunability in a broad frequency range with resonator and two-tone spectroscopy. Time-domain characterizations reveal energy relaxation and coherence times up to 75 ns. Our results, combined with the recent advances in the spin qubit field, pave the way towards novel hybrid and protected qubits in a group IV, CMOS-compatible material.

Quad-functioning parity layout for nanocomputing: A QCA design

Quantum dot cellular automata (QCA) is considered an alternative to conventional technologies like CMOS (Complementary Metal-Oxide-Semiconductor) technology due to its potential for lower power consumption, higher speed, and increased device density. QCA introduces a novel approach to designing nano communication circuits and systems. Nano communications data mistakes are detected via parity generators and checkers. The parity bit of each data block ensures that the number of 1′s is either even or odd. Consequently, the system requires four circuits: an even parity generator, an odd parity generator, an even parity checker, and an odd parity checker. The whole system requires more space and cell complexity. In this work, we propose a QCA architecture that serves as a generator for both even and odd parities, as well as a checker for both even and odd parities. It is a quad-functioning circuit that performs four distinct operations within a single design, utilizing 118 QCA cells and occupying an area of 0.17 μm2. The recommended approach uses an efficient XOR gate, resulting in improvements across several performance metrics. QCAPro calculates energy dissipation and design parameters. The recommended QCA circuit outperformed similar QCA circuits in size, complexity, and energy dissipation. The circuit's design cost functions are also low. There has been a 17% reduction in latency and an 86% improvement in QCA-specific costs when compared to the optimal existing design. Moreover, it necessitates a 40% reduction in majority gate usage. The proposed design may compete effectively with other equivalent higher-order circuit designs by reducing the need for multiple blocks in conventional circuits to execute the same task. This architecture holds potential benefits for nano processors and nano communication networks.

Perancangan Sistem Kunci Otomatis Berbasis Qr Code Menggunakan Sensor Gm66

The security system plays an important role for the comfort of human life today. Moreover, in the development of the times which are increasing day by day. In the world of technology, many things are implemented in security systems to increase consumer confidence. One of the main factors of the security system is theft by breaking into the building door. This security problem can be overcome by utilizing existing technology, for example with a QR Code. The design of this device will be carried out using two paths, namely hardware design and software design. This is done so that the design of this automatic lock system can work in accordance with the design which includes a circuit block diagram and circuit realization with the working principles of each circuit that has been designed. From some of the results of testing QR Code-based automatic door locks using the GM66 sensor which can be seen from several tables of test results, it can be concluded that the tool can work properly.

Pairing cellular and synaptic dynamics into building blocks of rhythmic neural circuits. A tutorial.

In this study we focus on two subnetworks common in the circuitry of swim central pattern generators (CPGs) in the sea slugs, Melibe leonina and Dendronotus iris and show that they are independently capable of stably producing emergent network bursting. This observation raises the question of whether the coordination of redundant bursting mechanisms plays a role in the generation of rhythm and its regulation in the given swim CPGs. To address this question, we investigate two pairwise rhythm-generating networks and examine the properties of their fundamental components: cellular and synaptic, which are crucial for proper network assembly and its stable function. We perform a slow-fast decomposition analysis of cellular dynamics and highlight its significant bifurcations occurring in isolated and coupled neurons. A novel model for slow synapses with high filtering efficiency and temporal delay is also introduced and examined. Our findings demonstrate the existence of two modes of oscillation in bicellular rhythm-generating networks with network hysteresis: i) a half-center oscillator and ii) an excitatory-inhibitory pair. These 2-cell networks offer potential as common building blocks combined in modular organization of larger neural circuits preserving robust network hysteresis.

Ultra-Efficient Low-Power Retinal Nano Electronic Circuit for Edge Enhancement and Detection Using 7 nm FinFET Technology

Ultra-Efficient Low-Power Retinal Nano Electronic Circuit for Edge Enhancement and Detection Using 7 nm FinFET Technology

Ultrahigh extinction ratio and a low power silicon thermo-optic switch.

The silicon thermo-optic switch (TOS) is one of the most fundamental and crucial blocks in large-scale silicon photonic integrated circuits (PICs). An energy-efficient silicon TOS with ultrahigh extinction ratio can effectively mitigate cross talk and reduce power consumption in optical systems. In this Letter, we demonstrate a silicon TOS based on cascading Mach-Zehnder interferometers (MZIs) with spiral thermo-optic phase shifters. The experimental results show that an ultrahigh extinction ratio of 58.8 dB is obtained, and the switching power consumption is as low as 2.32 mW/π without silicon air trench. The rise time and fall time of the silicon TOS are about 10.8 and 11.2 µs, respectively. Particularly, the figure of merit (FOM) has been improved compared with previously reported silicon TOS. The proposed silicon TOS may find potential applications in optical switch arrays, on-chip optical delay lines, etc.

N‐Type Organic Mixed Ionic‐Electronic Conductors for Organic Electrochemical Transistors

n‐Type organic electrochemical transistors (OECTs) are fundamental building blocks of biosensors and complementary circuits along with p‐type. Yet, their development has been lagging behind their p‐type counterparts since first emergence in 2016. The key component of an OECT is the channel material, which is an organic mixed ionic‐electronic conductor (OMIEC), that dictates the function and performance of the OECT via interactions with electrolyte ions. OMIECs of OECTs are benchmarked by the product of charge‐carrier mobility (μ) and volumetric capacitance (C*), μC*. Significant progress is made for the development of novel n‐type OMIECs, with best μC* now reaching 180 F cm−1 V−1 s−1. This review elucidates such material development progress of n‐type OMIECs with emphases on the underlying molecular design strategies and structure‐property relationships. Furthermore, the operational stability of channel materials and the applications of n‐type OECTs are also discussed to offer readers a comprehensive view of the field. Finally, current limitations are discussed along with outlook.

Integration mixer: An efficient mixed neural network for memory dynamic stability analysis in high dimensional variation space

In low-power designs, the SRAM performance suffers from the process variation. Statistical analysis for the yield of circuit block (e.g., static random-access memory) is extremely time-consuming due to the expensive simulations since the variation space is high-dimensional. In this paper, we construct a mixed neural network to substitute the simulation. We present Mixer. It mainly contains two types of layers: one with regularized sub-radial basis function networks (sub-RBFs) applied independently to extract the effects on circuit performance of the subsets of input process variables, and the other one with multi-layer perceptron (MLP) applied to learn the connection of these extracted effects. When trained with small datasets of high dimension generated from 28 nm memory circuits, our Mixer shows competitive accuracy and efficiency compared with other state-of-the-art models.*

Low-power and area-efficient memristor based non-volatile D latch and flip-flop: Design and analysis.

In recent years, non-volatile memory elements have become highly appealing for memory applications to implement a new class of storage memory that could replace flash memories in sequential logic applications, with features such as compactness, low power, fast processing speed, high endurance, and retention. The memristor is one such non-volatile element that fits the fundamental blocks of sequential logic circuits, the latch and flip-flop; hence, in this article, a non-volatile latch architecture using memristor ratioed logic (MRL) inverter and CMOS components is focused, with an additional memristor as a memory element. A Verilog-A model was used to create the memristor element. The simulation findings validated the compact, low-voltage, and reliable design of the latch design. We evolved in technology enough to create a master-slave flip-flop and arrange it to function as a counter and a shift register. Power, number of elements, cell size, energy, programming time, and robustness are compared to comparable non-volatile topologies. The proposed non-volatile latch proves non-volatility and can store data with a 24% reduction in power consumption and a near 10% reduction in area.

Design and analysis of 4-bit absolute-value comparator in 65nm technology using hybrid TG/CMOS

Comparators are an important part of the calculator architecture, and rapid advances in semiconductor and electronics technology have placed higher demands on their performance. Optimization of digital systems involves several levels in order to make improvements in their power consumption, delay, and other parameters. This paper designs a low-power, high speed, and area efficient 4-bit absolute-value comparator, which utilizes a static Complementary Metal-Oxide-Semiconductor (CMOS) and Transmission Gate (TG) hybrid structure. The design optimizes the system at the level of separate circuit blocks, logic gates and transistors. The logic functions are realized by means of transcoding and magnitude Comparison, and the input signals are all driven by two-stage inverters. MUX and XOR with excellent performance of TG structure are implemented using simulation and analysis. In this paper, the transistor sizes and supply voltages of each logic gate are calculated and optimized using MATLAB by applying logic effort theory. The design uses a 65nm technology, and transient simulation of the overall system in Cadence successfully realizes its logic functions with 0.83ns delay and 49.6uw power consumption, proving the effectiveness of the design. This study based on theoretical calculations and simulations is a good reference for the design and theoretical study of very large-scale integrated circuits (VLSI).

A 0.67 μV-IIRN super-T Ω-Z IN 17.5 μW/Ch Active Electrode With In-Channel Boosted CMRR for Distributed EEG Monitoring.

We present the design, development, and experimental characterization of an active electrode (AE) IC for wearable ambulatory EEG recording. The proposed architecture features in-AE double common-mode (CM) rejection, making the recording's CMRR independent of typically-significant AE-to-AE gain variations. Thanks to being DC coupled and needless of chopper stabilization for flicker noise suppression, the architecture yields a super-T Ω input impedance. Such a large input impedance makes the AE's CMRR practically immune to electrode-skin interface impedance variations across different recording channels, a critical feature for dry-electrode ambulatory systems. Signal quantization and serialization are also performed in-AE, which enables a distributed system in which all AEs use a single data bus for data/command communication to the backend module, thus significantly improving the system's scalability. Additionally, the presented AE hosts auxiliary modules for (i) detection of an unstable electrode-skin connection through continuous interface impedance monitoring, (ii) dynamic measurement and adjustment of input DC level, and (iii) a CM feedback loop for further CMRR enhancement. The article also presents the development of printed (extrusion) tattoo electrodes and their experimental characterization results with the proposed AE architecture. Besides bio-compatibility, low-cost, pattern flexibility, and quick fabrication process, the printed electrodes offer a very stable electrode-skin connection, conform to scalp shape, and exhibit consistent performance under various bending curvatures. Analog circuit blocks of the presented AE architecture are designed and fabricated using a standard 180 nm CMOS technology, and the [Formula: see text] IC is integrated with off-chip low-power digital modules on a PCB to form the AE. Our measurement results show a CMRR of 82.2 dB (at 60 Hz), amplification voltage gain of 52.8 dB, a bandwidth of 0.2-400 Hz, ±500 mV input DC offset tolerance, An input impedance [Formula: see text], and 0.67 μV RMS integrated input referred noise (0.5-100 Hz), while consuming 17.5 μW per channel. All auxiliary modules are tested experimentally, and the entire system is validated in-vivo, for both ECG and EEG recording.

Breast Cancer Diagnosis with Machine Learning Using Feed-Forward Multilayer Perceptron Analog Artificial Neural Network

An analog network classifier based on a multiplier and non-linear functions is presented in this paper, executing binary classification on breast cancer cells, and categorizing biopsies as benign or malignant tumors. An off-chip learning on-chip inference methodology is proposed for implementing a feed-forward analog artificial neural network based on fundamental design analog block circuits, realized with the aid of 90 nm CMOS technology. These circuits are meticulously designed and fine-tuned at the transistor scale to meet design criteria while minimizing power consumption. Through Spice simulations, the basic analog blocks were developed, leading to the specification of the full-chip hardware neural network. The Monte Carlo analysis of the final circuit reveals that the network achieves 96.85% accuracy and 0.9309 MCC on the Wisconsin breast cancer dataset, with a power consumption of 31.95 μW, and power supply rail of ±900 mV per analog circuit component and computational unit. The model effectively captures data patterns, providing stable, reliable, and robust predictions.

Modeling “Wrong Side” Failures Caused by Geomagnetically Induced Currents in Electrified Railway Signaling Systems in the UK

AbstractThe majority of studies into space weather impacts on ground‐based systems focus on power supply networks and oil and gas pipelines. The effects on railway signaling infrastructure remain a sparsely covered aspect even though these systems are known to have experienced adverse effects in the past as a result of geomagnetic activity. This study extends recent modeling of geomagnetic effects on DC signaling for AC‐electrified railways in the UK that analyzed “right side” failures in which green signals are turned to red. The extended model reported here allows the study of “wrong side” failures where red signals are turned green: a failure mode that is potentially more dangerous. Railway lines using track circuit signaling, like those modeled in this study, are separated into a number of individual blocks. This study shows that a relay is most susceptible to “wrong side” failure when a train is at the end of a track circuit block. Assuming that each train is positioned at the end of the block it is occupying, the results show that the geoelectric field threshold at which “wrong side” failures can occur is lower than for “right side” failures. This misoperation field level occurs on a timescale of once every 10 or 20 years. We also show that the estimated electric field caused by a 1‐in‐100 years event could cause a significant number of “wrong side” failures at multiple points along the railway lines studied, although this depends on the number of trains on the line at that time.

Energy-efficient design techniques for LUT based adaptive digital pre-distorters

Energy-efficient design techniques for an adaptive Look-Up Table (LUT) based Digital Predistortion (DPD) system are presented. The proposed methods are simplification of the adaptation function, reduction of the memory hardware complexity and bypassing of the equalizer circuit. The equalizer circuit block is critical while the adaptation loop is enabled but need for this block while the loop is disabled is explored to reduce power dissipation. Three adaptation functions that require less complex hardware are presented. The system is modeled with Matlab-Simulink, then implemented using an FPGA and 130 nm ST-Silicon On Insulator (SOI) process. More than 33% of power saving is obtained by applying the proposed techniques and further power reductions are also possible by configuring the system.

RANCANG BANGUN PERANGKAT KERAS SISTEM SMART LAMPU PENERANGAN JALAN UMUM BERBASIS INTERNET OF THINGS GUNA MENDUKUNG IMPLEMENTASI SMART CITY

Public Street Lighting (PJU) is a lighting system designed to provide street lighting at night with the aim of increasing comfort for pedestrians and motorists passing through. However, the obstacles faced regarding PJU lights at this time are that when carrying out monitoring and control officers are still checking and visiting the location of every whereabouts of PJU lights. So that to make it easier for officers to manage PJU lights in this study, they will conduct discussions related to the design and development of hardware that is applied to PJU lights. The methods used in the development of this system are design, development, and testing. To build hardware using components such as ESP32 as a microcontroller, PZEM004Tv30 sensor, DHT22 sensor, IC RTC DS3231, Relay 30 A, IC LM2596 5V, IC AMS1117 3.3V, GSM SIM808 Module and LDR sensor, while for implementing the protocol using the MQTT protocol and Antares as the MQTT platform. The results of tests carried out on each circuit block in hardware such as the DHT22 sensor have an accuracy range of ~0.1 – 0.2, the PZEM004Tv30 sensor has an accuracy range of ~0.3 – 0.5, Regulator IC LM2596 5V and AMS1117 3.3V each has an appropriate output voltage of ~5V and ~3.3V, and the CH340C IC Driver IC can work and read properly.

VLSI design and FPGA implementation of state-of-charge and state-of-health estimation for electric vehicle battery management systems

State of charge (SOC) and state of health (SOH) estimation is an important function in electric-vehicle (EV) battery-management systems (BMSs). SOC and SOH are the principal parameters for judging a battery’s state and critical for ensuring its safety and performance. In a conventional EV BMS, SOC and SOH estimation is performed on the master. However, owing to the increasing number of battery cells and computational cost of estimation algorithms, hardware-oriented processing for each single-battery module on the slave is being researched to reduce the master’s burden. Accordingly, this paper describes the hardware-optimized algorithm, VLSI design, and field-programmable gate array (FPGA) implementation verification results of an application-specific integrated circuit in a slave module to estimate SOC and SOH for multiple cells. We introduce an SOC and SOH estimation algorithm with 70% complexity reduction within a 2% error margin based on each cell’s voltage, current, and temperature and design a hardware block and logic circuit to implement the algorithm. An FPGA was utilized to verify the designed logic circuit, revealing a performance time of 0.65μs at 100 MHz. Finally, an FPGA testbed connected to a real battery and analog-front-end board was built to check the real-time performance through a graphical user interface.

Modal Theory and Approach for Accurate Characterization of Common-Mode Chokes

This work presents a method for characterization of common mode chokes, aimed at constructing accurate virtual prototypes of electromagnetic interference filters. This method is based on a general modal analysis that identifies the natural modes of a symmetric four-ports network in a power line. Natural modes excited in the setups defined in the CISPR-17 norm to characterize filtering devices are determined. From this analysis, two simple measurement setups particularly suitable for characterizing common mode chokes are identified, and a decision-making algorithm is presented to determine the parameters of a configurable circuit model of the common mode choke. This circuit model is especially devised so that each one of its different circuit blocks can be associated with a single modal response of the common mode choke. This, along with the use of physical criteria to define the basic schematic of each circuit block, ensures the simplicity, accuracy, and generality of the final circuit model. Characterization of many commercial common mode chokes with different core materials and winding configurations has been carried out to demonstrate that this circuit model is able to accurately account for the actual response of different types of common mode chokes in a wide frequency range.

Implementation of OTA in 90nm Technology with Bandgap Reference Application

Operational Transconductance Amplifier (OTA) is the basic building block of Analog circuit with linear input/output characteristics. Because it associates closely linked parameters like noise and settling performance, the current design methodologies for two-stage OTAs frequently result in sub-optimal solutions. The study discusses the implementation of an Operational transconductance amplifier (OTA) with a bandgap reference (BGR) circuit and its importance in providing a stable and accurate reference voltage for various analog and digital circuits. The combination of OTA and BGR provides a stable and accurate reference voltage that can be used in various analog and digital circuits. OTAs are used to drive high capacitive loads. To scale the dimensions of Complementary Metal Oxide Semiconductor (CMOS) technology requires proportional scaling, also taking supply voltage into consideration. In addition to the simplicity and strong performance that the Band Gap Reference (BGR) achieves as a load for the OTA circuit, the architecture of OTA with BGR as load is easily adaptable to attain high accuracy. Because the performance of the used amplifier has a significant impact on the OTA’s performance, consideration must be given to the design and its architecture. Therefore, it is essential to carry out a comparison analysis in order to get the optimal results of the outputs of OTA having BGR as the load.

Hardware Engineering of Hazardous Gas and Alcoholic Substances Detector in Meat Using Microcontroller and Gas Sensor

Meat may provide not only essential nutritional content but also possible harmful effects on human bodies. Unsafe consumption of meat potentially triggers colorectal cancer risks. Grilling is the most popular way to consume meat. However, meat grilling triggers the formation of hazardous chemical substances such as poisonous Polycyclic Aromatic Hydrocarbons (PAHs). This study conducted experiments using hardware engineering with microcontrollers and different gas sensors, aiming to identify gas substances produced by meat during grilling. The hardware prototype for the test simulation tool was assembled with integrated block systems and circuits. Evaluations were conducted on the direct grilling of three different types of meat. The data results were then utilized to analyze gas substances produced by meat during direct grilling. Based on the results, only five of the seven MQ-type gas sensors used in the research reacted to gas substances produced by all types of meat: LPG, alcohol, carbon monoxide, methane, and carbon dioxide, which were successfully detected in meat during grilling. Our research contributes to discovering a potential prevalence of increased alcoholic content in meat that has been grilled for five minutes. This finding is especially crucial for Muslims since it is highly correlated with halal certification of meat consumption. According to the results, Muslims should wait at least seven minutes or more after direct grilling to let the alcoholic content in meat thoroughly decrease so that it can be safely certified as halal to be consumed according to Islamic laws. Doi: 10.28991/HIJ-2023-04-03-01 Full Text: PDF

Substrate-Integrated Hybrid Metallo-Dielectric Waveguide Architecture for Millimeter-Wave and Terahertz Applications

In millimeter-wave (mmW) and terahertz (THz) applications, the transmission behavior along circuit structures and components, such as radiation and leakage losses, is critical for their overall performances. It is imperative to develop low-loss interconnect and transmission techniques that should be used for the construction of building circuit blocks and elements. In this work, a hybrid metallo-dielectric (MD) waveguide architecture is proposed and studied for the first time. The scheme is made of mixed substrate-integrated dielectric waveguide (SIDW) and substrate-integrated nonradiative dielectric (SINRD) waveguide, which are deployed for the design of specific building parts in consideration of respective transmission properties of the two waveguides. A back-to-back WR3-band prototype based on this hybrid scheme is investigated theoretically and validated experimentally. The hybrid MD waveguide architecture with SINRD is found to outperform the hybrid MD waveguide architecture with substrate-integrated waveguide (SIW) in terms of transmission performance and manufacturing complexity because of the advantageous features of metallized-via-free structure. The presented hybrid MD waveguide architecture shows its potential for developing low-loss highly integrated mmW and THz circuits and systems.