Chip Temperature Research Articles

In51Bi32.5Sn16.5@SiO2 microcapsules-based composite phase change materials with high thermal conductivity and heat storage density for electronics thermal management

Combining phase change microcapsules and various matrix materials can construct novel composite phase change materials (CPCMs). These composite materials hold immense potential for electronics thermal management, owing to their adjustable heat storage capacity and stable shape. Most previous studies focus on enhancing the thermal conductivity of CPCMs by adding thermally conductive fillers or modifying the microcapsule shells. Nevertheless, achieving both high thermal conductivity and heat storage density simultaneously remains a challenge. In this paper, low melting point alloy (In51Bi32.5Sn16.5) was introduced as core material of the microcapsule to enhance the thermal conductivity, due to its significantly higher thermal conductivity compared to commonly used organic or inorganic phase change materials (PCMs). In51Bi32.5Sn16.5@SiO2 microcapsule was synthesized through the sol-gel polymerization method. Furtherly, a form-stable CPCMs consisting of the microcapsules and silicone rubber (SR) matrix were prepared for electronics thermal management. The In51Bi32.5Sn16.5@SiO2 microcapsules exhibit an impressive thermal conductivity of 13.49 Wm−1 K−1, acting as a dual-functional filler for thermal storage and thermal conduction enhancement. Hence, the CPCMs possess a significantly enhanced thermal conductivity of 0.45 Wm−1 K−1, representing a remarkable improvement of 350 % compared to that of pure SR. In addition, the phase change heat storage density of the CPCMs was as high as 71.73 J/cm3. Notable, the prepared CPCMs demonstrate exceptional heat dissipation performance, resulting in a remarkable 23 °C reduction in chip temperature when applied for thermal management. This study offers a novel perspective on the preparation of microcapsule-based CPCMs for electronics thermal management.

Architectural and Technological Approaches for Efficient Energy Management in Multicore Processors

Benchmarks play an essential role in the performance evaluation of novel research concepts. Their effectiveness diminishes if they fail to exploit the available hardware of the evaluated microprocessor or, more broadly, if they are not consistent in comparing various systems. An empirical analysis of the consecrated Splash-2 benchmarks suite vs. the latest version Splash-4 was performed. It was shown that on a 64-core configuration, half of the simulated benchmarks reach temperatures well beyond the critical threshold of 105 °C, emphasizing the necessity of a multi-objective evaluation from at least the following perspectives: energy consumption, performance, chip temperature, and integration area. During the analysis, it was observed that the cores spend a large amount of time in the idle state, around 45% on average in some configurations. This can be exploited by implementing a predictive dynamic voltage and frequency scaling (DVFS) technique called the Simple Core State Predictor (SCSP) to enhance the Intel Nehalem architecture and to simulate it using Sniper. The aim was to decrease the overall energy consumption by reducing power consumption at core level while maintaining the same performance. More than that, the SCSP technique, which operates with core-level abstract information, was applied in parallel with a Value Predictor (VP) or a Dynamic Instruction Reuse (DIR) technique, which rely on instruction-level information. Using the SCSP alone, a 9.95% reduction in power consumption and an energy reduction of 10.54% were achieved, maintaining the performance. By combining the SCSP with the VP technique, a performance increase of 8.87% was obtained while reducing power and energy consumption by 3.13% and 8.48%, respectively.

Effect of PCM-filled hallow fin heat sink for cooling of electronic components — a numerical approach for thermal management perspective

This paper aims at the PCM-based heat sink for electronic cooling. In the present analysis, paraffin wax-based phase change material (PCM), in 3-fin and 4-fin hollow heat sinks with the proper volume of PCM in the temperature of the electronic components can be controlled. The PCM-filled heat sinks are placed on top of the high heat-generating integrated circuit (IC) components. The aim is to reduce the maximum temperature of the electronic components and keep them below their critical temperature, hence increasing the life of the IC chips. A correlation is put forward for dimensionless temperature ([Formula: see text]) in terms of heat flux ([Formula: see text]), volume content ([Formula: see text]) and size of the IC chips ([Formula: see text]). It has been found that there will be a 4–[Formula: see text]C drop in temperature when compared to solid fins heat sinks. It is confirmed that the temperature of the IC chip is a strong function of heat flux, size and volume content of PCM.

Influence of milling parameters on the microstructural evolution mechanism of 7075-T6 aluminum alloy

This study evaluates the influence of milling parameters on the milling process and microstructural changes in 7075-T6 aluminum alloy using experimental and simulation methods. Key findings include a direct correlation between milling parameters and higher chip temperatures, particularly influenced by milling speed which at its third level can cause temperature elevations up to 36 °C, ordered by impact as ap > f > v.Increasing milling depth markedly affects grain recrystallization, especially near the tool's trailing face (P3), leading to a 45.8% reduction in dynamic recrystallization, whereas lower depths expedite this process. Additionally, grain size and number at the leading face (P1) are also depth-dependent, with larger grains diminishing in volume yet increasing in quantity as depth increases. Enhanced milling speeds up to 500 mm/min significantly refine grains to near 1 μm at P1, with an 80.7% rise in recrystallization numbers, while at P3, grain size initially contracts then enlarges at 416 mm/min. Feed rate primarily impacts the quantity of recrystallized grains at the tool tip (P2), with a notable 60.4% increment and a swift transition from larger to smaller grains. Both P1 and P2 experience about a 20% reduction in grain growth due to feed rate, with more pronounced effects at P1 and the fragmentation of larger boundary grains into smaller, irregular shapes.

An experimental investigation and multiphysics simulation of thermoelectric temperature controller for AWG chips

The refractive index of silicon-based waveguide materials is highly sensitive to temperature and stress, and the effective refractive index of the waveguide varies with temperature changes. Thus, it is critical to reduce the temperature dependence of Arrayed Waveguide Grating (AWG) devices and to precisely control the center wavelength of AWGs. In this study, the thermoelectric cooler (TEC) was designed and fabricated to control the temperature of the thermal AWG chip, which did not require any material replacement or reprocessing of the AWG chip. Different magnitudes and polarities of voltage are applied to the TEC to regulate its operational state (heating or cooling). A multiphysics simulation model of a thermal AWG device is established and validated through transient and steady-state experiments. This study investigated the influence of different conditions (input voltage, environmental temperature) on the temperature and maximum stress of the AWG chip. A conformal TEC was designed and its performance was compared with that of the square TEC. The energy consumption of the conformal TEC was also tested and analyzed. The results show that in a 25 °C ambient environment, the TEC can control the temperature of the AWG chip in the range of 1.5–78.3 °C, significantly expanding the current operational temperature range of 65.0–85.0 °C when using Positive Temperature Coefficient (PTC) heaters. Under the same conditions, when using the conformal TEC as the temperature control device, the temperature gradient on the AWG chip is reduced by 1.37 °C during cooling and 2.80 °C during heating. The maximum stress value in the core layer is always lower, with a maximum reduction of 3.61 MPa. TEC can set the ideal operating temperature of the AWG chip according to the actual operating environment of the product, which reduces the energy consumption of TEC. A comparison is made between the average power consumption of the conformal TEC and the PTC heater under two operating conditions: a 25 °C constant-temperature environment and a natural environment. The average power consumption can be reduced by up to 97.87 % and 93.02 %, respectively. This study holds significant guidance for solving the temperature dependence problem of AWG devices and the application of thermoelectric coolers in the field of optical communication.

Power-cycling degradation monitoring of an IGBT module with VCE(sat) measurement in continuous operation of a chopper circuit

This paper presents a power-cycling degradation monitoring method of an IGBT module with a VCE(sat) sensing circuit and junction temperature prediction by a three-dimensional structure model. A chopper circuit was introduced to provide a continuous-current-conducting operation of the IGBT module. The VCE(sat) sensing circuit with a low-cost IoT platform “Leafony” was utilized to monitor the junction temperature of an IGBT chip, which transferred the measured signal as digital data, and thus obtained a higher noise immunity than an analog-based circuit. The junction temperature of IGBT chip in the power module was analyzed from the dissipated power of IGBT and the transient thermal impedance between the chips and the ambient. This analysis is effective not only to observe the degradation but also to estimate the thermal resistance. Comparing the temperature profile between experiment and prediction provides health condition of the IGBT model.Predicted thermal profiles agreed with measured ones with 10 % increase of thermal resistance, which was degraded by a power cycle tester. From these results, the proposed monitoring method is effective to detect the progress of power cycle degradation.

Simulation on an Advanced Double-Sided Cooling Flip-Chip Packaging with Diamond Material for Gallium Oxide Devices.

Gallium oxide (Ga2O3) devices have shown remarkable potential for high-voltage, high-power, and low-loss power applications. However, thermal management of packaging for Ga2O3 devices becomes challenging due to the significant self-heating effect. In this paper, an advanced double-sided cooling flip-chip packaging structure for Ga2O3 devices was proposed and the overall packaging of Ga2O3 chips was researched by simulation in detail. The advanced double-sided cooling flip-chip packaging structure was formed by adding a layer of diamond material on top of the device based on the single-sided flip-chip structure. With a power density of 3.2 W/mm, it was observed that the maximum temperature of the Ga2O3 chip with the advanced double-sided cooling flip-chip packaging structure was 103 °C. Compared with traditional wire bonding packaging and single-sided cooling flip-chip packaging, the maximum temperature was reduced by about 12 °C and 7 °C, respectively. When the maximum temperature of the chip was controlled at 200 °C, the Ga2O3 chip with double-sided cooling packaging could reach a power density of 6.8 W/mm. Finally, by equipping the top of the package with additional water-cooling equipment, the maximum temperature was reduced to 186 °C. These findings highlight the effectiveness of the proposed flip-chip design with double-sided cooling in enhancing the heat dissipation capability of Ga2O3 chips, suggesting promising prospects for this advanced packaging structure.

OPTIMIZATION OF MICRO HEAT SINK WITH REPETITIVE PATTERN OF OBSTACLES FOR ELECTRONIC COOLING APPLICATIONS

Micro heat sinks (MHS) are becoming integral part of microelectronics nowadays because of their ability to cool the tiny components which generate high heat flux. In this study, an electronic chip with a high heat flux of 100 W/cm<sup>2</sup> is cooled with the help of an MHS device which has repetitive patterns of obstacles of various shapes in the flow of cooling medium. Numerical modelling of all MHSs were performed using a computational fluid dynamics (CFD) solver and the pattern, which gives better thermohydraulic performance, was selected for optimization. A parametric study was performed with various obstacle sizes, distances between obstacles, and flow rates of cooling medium for maximum temperature of chip and pressure drop. Regression analysis was carried out with response surface method (RSM) between these three design variables and two objective functions, viz. thermal resistance (R<sub>th</sub>) and pumping power (P<sub>p</sub>). A multi-objective optimization of the MHS was performed using genetic algorithm (GA) and Pareto-optimal solutions were obtained. An optimal design was fabricated and the cooling experiment was carried out under optimal flow conditions. The repetitive pattern of obstacles increases the conjugate heat transfer area and helps in improving thermal performance.

A Comparison of Chip Temperature Acquisition Technologies of IGBT Power Modules

A Comparison of Chip Temperature Acquisition Technologies of IGBT Power Modules

Multiphysics Simulation of a Novel Self-Adaptive Chip Cooling with a Temperature-Regulated Metal Pillar Array in Microfluidic Channels

Conventional liquid cooling techniques may provide effective chip cooling but at the expense of high pumping power consumption. Considering that there is dynamic heat load in practice, a self-adaptive cooling technique is desired to reduce operational costs while preserving inherent cooling effectiveness. In this work, a novel self-adaptive cooling strategy is presented to balance the thermal and flow efficiency in accordance with the dynamic thermal load, based on temperature-regulated movement of the metal pillar array in a microfluidic channel. With an illustrative device, the effectiveness of such a strategy is investigated using multiphysics modeling and simulation. As a case study, the device is considered to be initiated with a chip power of 5 W and an inlet coolant velocity of 0.3 m/s. It is shown that the temperature-regulated movement of the metal pillar heat sink will be activated rapidly and equilibrate within 30 s. Parts of the metal pillars immerse into the coolant flow, resulting in significantly improved heat transfer efficiency. The diminished thermal resistance leads to a reduction in chip temperature rise from 225 K (without structural adaptation) to 91.86 K (with structural adaption). Meanwhile, the immersion of metal pillars into the coolant also causes an increased flow resistance in the microfluidic channel (i.e., pressure drop increases from 859.27 Pa to 915.98 Pa). Nevertheless, the flow resistance decreases spontaneously when the working power of the chip decreases. Comprehensive simulation has demonstrated that the temperature-regulated structure works well under various conditions. Therefore, it is believed that the presented self-adaptive cooling strategy offers simple and cost-effective thermal management for modern electronics with dynamic heat fluxes.

Suitability of Embedded Liquid Cooling and Heat Generation for Chips.

Embedded liquid cooling is a preferred solution for dissipating the heat generated by high-power chips. The cooling capacity and pump power consumption of embedded liquid cooling heat sinks differ significantly between different structures. To achieve an accurate match between cooling capacity and heat dissipation requirements, the selection of a liquid-cooled heat sink should be carefully considered in conjunction with the heat dissipation needs of heat sources in real-world thermal management issues. Based on the manufacturing limitations on chip temperature and microchannel pressure, a composite performance index function was developed to assess the cooling capacity and cooling cost of the heat sink. This allowed for the establishment of an evaluation standard to determine the suitability of embedded liquid cooling and heat sink for the heat source. In this study, the suitability of four microchannel heat sinks with the same feature length and fin volume was evaluated under various thermal load conditions. The results show that the best-suited heat sink changes with variations in the thermal load of the chip. In the example, when the heat source was homogeneous at 100 W, the circular section pin fins have an optimal suitability of 0.928 for Re = 500. When the heat source was a heterogeneous heat source with a power of 100 W, the value of Θ was found to be 0.389. Additionally, the optimal suitability of drop section pin fins for Re = 971.5 was determined to be 0.862.

Effect of diamond grain shape on gallium nitride nano-grinding process

In the grinding process, the quality of the product in the process is affected by many factors. In order to improve the processing quality and take into account the processing efficiency, the selection of a reasonable abrasive grain shape can be considered. This is a low-cost and highly feasible approach. In this article, the molecular dynamics method was employed to simulate the process of grinding GaN with four common synthetic diamond of abrasive grains (spherical, octahedron, cubic and cub-octahedron), and the surface morphology, material removal rate, temperature, potential energy, grinding force, substrate structure deformation, subsurface damage and dislocation were investigated. The results show that the cubic abrasive grain has the highest material removal rate with the number of chip atoms per unit area about 1.68 times that of the cub-octahedron abrasive grain. The lowest subsurface temperature of the octahedron abrasive grain during processing is 498 K. In contrast, the other three grits have similar subsurface temperatures of 540 K, 535 K and 545 K, respectively. The tangential force per unit area of octahedron abrasive grain is about 0.68761 (spherical: 0.23987, cubic: 0.4476, cubo-octahedral: 0.4314), but its potential energy is the most stable during processing. The shape of the abrasive grain has no significant effect on the coefficient of friction, while it has a significant effect on the subsurface damage. The depth of subsurface damage is the smallest for both cubic and cub-octahedron abrasive grain (2.4 nm), while cub-octahedron abrasive grain is more capable of promoting the generation of dislocations within the substrate. In addition, the performance of cubic and cub-octahedron abrasive grain at different grinding depths was further explored. Number of chip atoms, temperature, grinding force and subsurface damage all increase with the grinding depth. Nevertheless, the machining performance of cubic abrasive grain is still superior to that of cub-octahedron abrasive grain when the grinding depth is more than 1 nm. The outcome of this study may provide a micro-scale insight into the selection of abrasive grain shapes for processing GaN substrates.

Thermal contact analysis of Flip-Chip package considering microscopic contacts of double-layer thermal interface materials

Flip-chip packaging technology is widely used in the field of electronic packaging. The thermal contact resistances (TCRs) of its double-layer thermal interface materials (TIMs) impact its thermal characteristics. In this paper, a flip-chip package thermal contact model is first constructed considering the internal rough contact interface of double-layer TIMs. Secondly, the effects of friction coefficient, pressure, elastic modulus of double-layer TIMs, thermal conductivity of double-layer TIMs, interstitial medium, and convective heat transfer coefficient on the flip chip package's contact mechanics and thermal properties are analyzed. Finally, the influence of secondary thermal effects on contact mechanics and thermal properties is investigated. The results show that the friction coefficient, pressure, and elastic modulus of double-layer TIMs have a significant influence on the TCRs by changing the actual contact area, but the impact on the heat dissipation of the chip is limited, and the maximum temperature reduction does not exceed 10 K. However, the interstitial medium, convective heat transfer coefficient, and thermal conductivity of double-layer TIMs greatly influence the heat dissipation of the chip and maximum temperature by directly affecting heat transfer performance. Furthermore, secondary thermal effects have varying degrees of influence on contact stiffness, TCRs, and temperature distribution.

The effect of wafer thinning and thermal capacitance on chip temperature of SiC Schottky diodes during surge currents

Due to superior material properties of SiC for high-voltage devices, SiC Schottky diodes are used in energy-conversion systems such as solar-cell inverters, battery chargers, and power modules for electric cars and unmanned aerial vehicles. The reliable operation of these systems requires the chip temperature of SiC Schottky diodes to be maintained within the limit set by the device package. This is especially crucial during surge-current events that dissipate heat within the device. As a thermal-management method, manufactures of commercial SiC Schottky diodes have introduced wafer thinning practices to reduce the thickness of the SiC chip and, consequently, to reduce its thermal resistance. However, this also leads to a reduction in the thermal capacitance. In this paper, we present experimental data and theoretical analysis to demonstrate that the reduced thermal capacitance has a much larger adverse effect in comparison to the beneficial reduction of the thermal resistance. An implication of the presented results is that, contrary to the adopted wafer thinning practices, SiC Schottky diodes fabricated without wafer thinning have superior surge-current capability.

Investigation on Thermal Conductivity Silver-coated Copper/GaInSn Composite Thermal Interface Materials

To enhance the heat transfer performance of GaInSn liquid metal, a new type of composite thermal interface material with GaInSn as thermal conductive matrix and silver-coated copper particles as thermal conductive fillers was prepared in this article. The morphology of the composites were characterized by scanning electron microscopy. The thermal conductivity of silver-coated copper/GaInSn composites with different silver-coated copper particle contents were measured by laser flash method. The interfacial bonding of the composites were investigated by X-ray diffraction. The results show that when the volume ratio of silver-coated copper particles is 15%, thermal conductivity of the silver-coated copper/GaInSn composite reaches the largest value of 25.01 W·m−1·K−1. The silver-coated copper/GaInSn composite material and commercially available thermal grease were put into the chip and copper plate to simulate the actual application scenarios for comparison. The heat dissipation capacity of silver-coated copper/GaInSn composite material is obviously better than that of the two commercially available thermal grease, and the chip temperature can be reduced by about 5°C.

Mesoscale multi-component energy density transport for natural convective microchip cooling with solid–liquid–gas phase changes

A design of microchip cooling with natural convection driven multi-phase coolant flows is proposed by using thermoelectric modules as heat sinks. A new multi-component multi-phase (MCMP) thermal energy transport model is built for convective heat transfer with solid–liquid–gas phase changes. Different from previous lattice Boltzmann models based on temperature distributions, the present model is based on MCMP energy density distributions, which track sensible and latent heat transport for each phase. The local MCMP heat fluxes are related to mesoscale relaxation times and phase volume fractions. Transient solid–liquid–gas interfaces and local temperatures are obtained through the dynamical balance of mesoscale forces and fluxes among all phases together with MCMP enthalpy–temperature distributions. Comparisons of the on and off states of the heat sink modules show that the chip temperature can drop from about 300 to 110 °C, with the coolant liquid–gas phase change temperature of 80 °C at equivalent heat source and sink intensities of 100 W/cm2. Results also show that increasing heat sink intensity to 300 W/cm2 or decreasing gas–liquid phase change temperature to 60 °C can further decrease the chip temperature to 90 °C. The effects of sizes of chips, modules, and cooling units are also illustrated. It is observed that gas bubbles attached on chips impede heat transfer due to the low gas phase thermal conductivity, which means future improvements should also focus on removing or degrading attached gas bubbles. This model provides a quantitative tool for immersion chip cooling performances.

Fluid flow and heat transfer behavior of a liquid based MEMS heat sink having wavy microchannels integrating circular pin-fins

MEMS heat sink having wavy microchannels integrating circular pin-fins for cooling of microelectronic chips is proposed and analyzed in this work; the pin-fins are placed at the valleys and peaks of the wavy structure. The pumping power and thermal resistance of the proposed MEMS heat sink is higher and lower than that of MEMS heat sink having straight microchannels. At Reynolds number of 250, the maximum temperature of the microelectronic chip, generating 106 W/m2, when using the proposed MEMS heat sink is only 0.77 of that when using MEMS heat sink having straight microchannels; this ratio lowers to 0.6 at Reynolds number of 1250. The thermal resistance of the proposed MEMS heat sink is only 0.72 and 0.43 of that of the MEMS heat sink having straight microchannels at Reynolds numbers of 250 and 1250, respectively. Regarding the pumping power of the proposed MEMS heat sink, it is higher than that of the MEMS heat sink having straight microchannels by 2 and 3.7 at the lowest and highest Reynolds numbers, respectively. This work also analyzes the contribution of geometric features on the behavior of the proposed MEMS heat sink in terms of maximum temperature of the microelectronic chip, thermal resistance, and pumping power as well as that of microchannel employed in the proposed MEMS heat sink in terms of Poiseuille and Nusselt numbers. Maximum temperature of the microelectronic chip and thermal resistance decrease along with increase in pumping power with increase in amplitude, diameter of pin-fins, and hydraulic diameter of microchannel as well as with decrease in wavelength. Poiseuille and Nusselt numbers increased with rise in amplitude, diameter of pin-fins, and hydraulic diameter as well as decrease in wavelength. In addition, experiments have been conducted on two designs of the proposed MEMS heat sink to generate data for purposes of validating the model. The experimental data are compared with data from simulations and the difference between the two are within the uncertainty of experimental data thereby validating the model.

Ground-facing radiative cooling for high power LED lights

Objects on Earth facing the sky have the ability to emit thermal energy into the universe through the transparent atmosphere. This process can enable electricity-free cooling due to the extremely low temperature of outer space. However, factors such as humidity, clouds, and air pollution within the atmosphere can affect this process, particularly for electricity-free sub-ambient cooling applications. For high-temperature objects, the dependency of radiative cooling performance on the environment is significantly reduced. In this study, we explore the potential of utilizing ground-facing radiative cooling for improved high-power light-emitting-diode (LED) lighting applications. By using a transparent material, like polyethylene, as the front cover of the LED light package, one can efficiently release thermal radiation from the semiconductor chips that can reach temperatures of 60–130 °C. As a result, we demonstrate a reduction in the operational temperature of the LED chip by 3.9 °C in controlled indoor settings and by 3.7 °C in selected outdoor environments. Our analysis reveals that employing ground-facing radiative cooling can enhance the luminous efficacy of LED lights by approximately 3.0%. Assuming all current global electricity consumption is used for LED lights, this enhancement translates to an estimated annual energy savings of 128 terawatt-hours and a reduction in carbon dioxide emissions by 55 million metric tons. Remarkably, according to our aging experiment over 4000 h, this method can extend the lifespan of LED lights by 21.7% due to the lowered junction temperature of the semiconductor chip, resulting in reduced material, labor, and maintenance costs for future global LED lighting products.

Modeling and Optimization of Mechanical Cutting of Downhole Tubing

Summary Mechanical cutting of tubing plays a vital role in solving the problem of pipe string jams in workover operations of oil wells. To improve the efficiency of downhole cutting operations and save operation costs, it is necessary to optimize the parameters of downhole-cutting operations. However, previous research did not involve related engineering problems. Therefore, in this paper, the equivalent simulation experiment of downhole cutting is conducted based on actual field data. Cutting speed, feed rate, and cutting thickness are used as parameters while cutting power (P), material removal rate (MRR), and tool chip temperature (T) are used as optimization objectives with the trade-offs between the three objectives considered. The full factorial design is used to carry out the experiments and the combination of grey relational analysis (GRA) method and entropy weight method is used to determine the weight of the three objectives. The influence of cutting parameters on the optimization objectives is analyzed, the mathematical model between cutting parameters and a single objective is established, and the adaptive weight particle swarm algorithm is used to optimize the coefficients of this model. The relationship between the multiobjective model and cutting parameters is established using a multiple nonlinear regression model, and the selection of interaction terms is completed using a stepwise regression method. The reliability of the model is also verified. This paper provides a reference for future research on downhole-cutting problems.

Influence of post-processing and build orientation on the micro-machinability and chip formation during micro-drilling of L-PBF AlSi10Mg

The requirement of micro holes or features on the additively manufactured (AM) components attract machinability investigations on Laser Powder Bed Fused (L-PBF) components, and directional anisotropy is one of the critical problems with parts made using L-PBF. As a result, the current study compares the machinability properties during the micro-drilling of several samples, including cast and L-PBF-produced AlSi10Mg. Moreover, the impact of T6 solution heat treatment and build orientation on microstructure, thrust force, cutting torque, surface roughness, and cutting temperature is analyzed. It was found that at a feed of 8 µm/rev and 5000 rpm, the force requirement perpendicular to the build direction (PPBD) was 23.11 % higher than parallel to the build plane direction (PBD). The force required is reduced after heat treatment because of the reduction in hardness. Similarly, a difference of 31.36 % in cutting torque requirement was observed, which increased to 46.82 % after heat treatment. At the same time, the difference in chip temperature in the as-built AlSi10Mg was less between PPBD and PBD. It was also observed that there is a reduction in the chip temperature with feed rate. The chip formation was further studied using a high-speed camera, and four stages of chip formation were identified. From the SEM analysis of the chips, microchips of different lengths and morphology can be identified, which are dissimilar to one another.