Stacked Chip Package Research Articles

Highly Selective Cu Electrodeposition for Filling Through Silicon Holes

In this work, a copper plating formula that can directly and selectively fill the through silicon holes (TSHs) for 3D chip stacking packaging was developed. The copper plating technology reduced and simplified the process steps for fabricating through silicon vias (TSVs) and TSHs. The highly selectivity of copper fill in the TSHs also reduced the manufacture cost of 3D chip stacking packaging, because the copper plating technology reduced the loading of a post-copper chemical mechanical polishing (CMP) and did not need a post-thermal annealing treatment. The copper plating formula was very simple, just containing single organic additive.

Interfacial delamination investigation between copper bumps in 3D chip stacking package by using the modified virtual crack closure technique

In this study, the modified virtual crack closure technique (MVCCT) incorporated with the finite element method (FEM) is applied to investigate the delamination behavior between stacked copper bumps in 3D chip stacking packaging at package-level and board-level, and the energy release rate at the delamination front is evaluated as the criterion of the crack expansion. The package-level structure is firstly simulated to validate the dependability of MVCCT, and the results reveal that the delamination between copper bumps within specific size will not induce delamination expansion during thermal cycling condition, which show good agreement with experiment results. The mesh density and the delamination geometry effect analyses are also studied at package-level to ensure the reliable result of finite element analysis. The results show that the former has an insignificant effect on the energy release rate, while the later has a significant influence. Moreover, based on the simulation results at package-level structure, the further delamination behavior at board-level is investigated to predict potential failure mode different from the package-level structure. The results show higher energy release rate is induced and mixed fracture mode occurs.

Study of Thermo-Mechanical Reliability of TSV for 8-Layer Stacked Multi Chip Package

Through silicon via (TSV) technology is becoming a hot topic for three dimensional integration in IC packaging industry. However, TSV technology raises several reliability concerns particularly caused by thermally induced stress. In this study, the thermo-mechanical reliability of copper TSV technology for the multi chip packaging was investigated using finite element method. For the multi chip package design, the 8-layer stacked chip packaging with TSV structure has been constructed as our test vehicle. The numerical analysis of stress/strain distribution and thermal fatigue life prediction were performed in order to study the impact of several design parameters such as via diameter, via pitch, die thickness, bonding pad geometry. The effects of various underfill materials which have different Young¡¯s modulus and coefficients of thermal expansion (CTEs) were also investigated. The DOE (design of experiment) analysis was performed to find the optimal design conditions for 8-layer multi chip package. The most influential factors for the stress reduction are TSV diameter and the coefficient of thermal expansion of underfill material. The larger via diameter and lower CTE showed the smaller stress distribution. On the other hand, thermal fatigue life increases with via diameter, and becomes maximum at via diameter of 20 um, then decrease with increasing via diameter. The presence of underfill material significantly increased the thermal fatigue life of TSV structure. The bonding pad design is also important for TSV durability. The smaller bonding pad showed less stress and higher thermal fatigue life. The characteristics of warpage for 8-layer multi chip package were also investigated.

A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

In this paper, we propose a new three-dimensional (3-D) clock distribution network (CDN) scheme using a low temperature co-fired ceramic (LTCC) package level interposer with a planar cavity resonator to achieve extremely low jitter and skew clock delivery even in severe power supply noise environments, especially for digital chips in 3-D stacked chip packages. It is based on a uniform-phase of the standing wave at the quarter-wavelength planar cavity resonator embedded inside the LTCC interposer. Substantial suppression of the timing jitter and skew was successfully demonstrated through a series of design, fabrication, and measurement processes of test devices and packages.

Suppression of Power/Ground Inductive Impedance and Simultaneous Switching Noise Using Silicon Through-Via in a 3-D Stacked Chip Package

We have thoroughly investigated the advantages of a silicon through-via (STV) interconnection in decreasing the inductive impedance of a power distribution network (PDN) and suppressing simultaneous switching noise (SSN) in a 3-D stacked chip package. A double-stacked chip package with STV interconnections was fabricated and measured together with a similar double-stacked chip package with conventional bonding-wire interconnections. We successfully demonstrated that significant reduction of the inductive PDN impedance, from 1.66 nH to 0.79 nH, can be achieved by replacing the conventional bonding wires in the multiple-stacked chip package by STV interconnections. Furthermore, we have shown that the STV interconnections can considerably reduce high-frequency SSN, by more than 80%, compared to the conventional bonding-wire interconnections.

Reliability evaluation of BOAC and normal pad stacked-chip packaging using low- K wafers

This work evaluates the wire bondability and the reliability tests for the stacked-chip TFBGA wire bond packaging with the Sn–4.0Ag–0.5Cu lead-free solder ball. The bonding-over-active-circuit (BOAC) pad is the top test chip and the normal pad is the bottom test chip and is combined in the stacked-chip packaging. Both test chips are 90 nm low- K dielectric with five copper layers and one layer aluminum pad and a background ranging from 775 μm to 150 μm. According to the simulation results, the maximum normal stress of low- K layer for the BOAC pad is higher than that of the normal pad by 146.4%. However, the maximum shear stress of Cu metal layer for the BOAC pad is lower than that of the normal pad by 64.2%. To compare the bonding pad strength for the BOAC and normal pad low- K wafers, this work uses the simplified two-layer model to extract the effective mechanical properties of the two bonding pad structures. The effective average Young’s modulus of the normal pad and the BOAC pad are 86 GPa and 69 GPa, respectively. The test results indicate that the effective Young’s modulus of the normal pad exceeds that of the BOAC pad by 17 GPa. The wire bondability test of the ball shear and the wire pull test results are superior to the specification by 80% and 83.75%, respectively. All stacked-chip TFBGA packaging samples underwent reliability tests, including HAST, TCT, and HTST. All the wire bondability and reliability tests passed the specification for the BOAC pad and the normal pad low- K structures. Accordingly, this work shows that the proposed stacked-chip TFBGA packaging passes the wire bondability and the reliability tests. The proposed packaging improves the electrical performance, enhances the utility of the active chip area and saves chip area through the use of low- K and BOAC chips. Furthermore, the results show that the equivalent stiffness of the bonding pad structure can be used as the bondability and reliability test index for the chip.

On-Chip Yagi–Uda Antenna for Horizontal Wireless Signal Transmission in Stacked Multi Chip Packaging

In this paper, we propose horizontal wireless signal transmission using on-chip Yagi–Uda antennas, which are used for stacked multi chip packaging (MCP). The features of this study are (a) multiple signal transmissions are realized using directional antennas, (b) measured directivities of on-chip Yagi–Uda antennas are demonstrated, and (c) a scaling scenario of the on-chip directional antenna is presented to achieve the same signal throughput as the clock frequency. The Yagi–Uda antenna offers high directivity and gain; thus, it can provide space-division multiplexing and multiple signal transmissions for intra and inter chip communication.

Injection Molding Simulation of 3D Stacked-Chip Assembly Packaging with Different Entrances

AbstractThis paper adopts a three-dimensional (3D) finite element method to simulate the injection molding of organic 3D stacked-chip assemblies. The geometry model of the assembly is simplified to a five-layered structure of stacked-chips with no solder bumps. The injection molding process incorporates 3D stacked-chip packaging and encapsulation techniques, and comprises primarily of multi-layer cavity-filling and reactive-thermosetting curing processes. The current investigation considers the effects of specifying different entrances on the resultant flow fronts, air-traps, and weld-lines. In general, the present results confirm the value of performing numerical simulations of the 3D stacked-chip packaging process to support the injection molding CAE approaches which are commonly applied nowadays to improve the packaging assembly design and to facilitate the rapid set up of mass-production conditions. The simulation results indicate that the best packaging results are obtained when the melt is introduced either at the center of the periphery side of the stacked-chip modulus or at its corner.

A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment

A Systematic Approach to Thinning Silicon Wafers to the sub-40μm Thickness Range

The present trend in electronics packaging is the stacking of die at the wafer or chip level. However to ensure stacked chip packages maintain overall low height and weight package profile, silicon wafers have to undergo extensive wafer thinning processes. In this work, a systematic approach to thinning silicon wafers down to sub-40μm in thickness is presented. This paper will cover a detailed three stage wafer thinning method, which includes the mechanical back-lapping method for the bulk removal process and a combination of mechanical polishing and spin-spray wet chemical etch method for the fine removal wafer thinning process. The results will show that by just utilizing the mechanical back-lapping and mechanical polishing process the wafers can be easily thinned from 380μm to less than 50μm with ±2.5μm Total Thickness Variation (TTV). These back-lapped wafers are then further thinned by the spin-spray etching method to achieve final wafer thickness of less than 40μm. The paper will also show that by utilizing a modified carrier wafer, the handling of these sub-40μm ultra-thin wafers do not require custom made tools and can be easily integrated into existing wafer handling tools.

A 3-D stacked chip packaging solution for miniaturized massively parallel processing

The development and evaluation of a three-dimensional (3-D) interconnect and packaging technology for massively parallel processor (MPP) implementation is reported. Following reviews of specific modular massively parallel computer (MPC) accelerator and chip stacking technologies, the paper reports the progress of a collaborative research project to pioneer a novel MPP module. The design of a highly compact 3-D chip-stack, integrating five MPP chips in a single package, is described in detail. Problems encountered and their solutions are reported. Test results for prototype MPP chip-stacks provide proof-of-principle for the 3-D chip stacking approach. Allowing from 2:1 to 4:1 savings in the modular MPC implementation size, without significant increase in cost or loss of performance, the emerging MPP chip stacking technology offers a cost-effective solution for MPP miniaturization.