Abstract
In this work, a copper plating formula that can directly and selectively fill the through silicon holes (TSHs) for 3D chip stacking packaging was developed. The copper plating technology reduced and simplified the process steps for fabricating through silicon vias (TSVs) and TSHs. The highly selectivity of copper fill in the TSHs also reduced the manufacture cost of 3D chip stacking packaging, because the copper plating technology reduced the loading of a post-copper chemical mechanical polishing (CMP) and did not need a post-thermal annealing treatment. The copper plating formula was very simple, just containing single organic additive.
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