Through Silicon Vias and Holes Metallization using CoWP and Cu Nanoparticles as Barrier and Seed Layers

Abstract

Three new technologies for Cu coating and deposition in through silicon vias (TSVs) and through silicon holes (TSHs) were developed. One is to synthesize Cu nanoparticles (CuNPs) with a particle size of 3–5 nm and then coat the CuNPs onto the sidewall of TSVs by a wet process to act as catalysts for a seed layer formation through copper electroless deposition. The wet process for Cu seed layer formation can make sure of conformal coating and reduce the process cost of TSV. Second, we develop a new Cu electroplating formula that can make selective Cu fill (SCF) in TSVs, which leads to no increase in Cu thickness on the top surface after electroplating. The plating technique, SCF, can greatly reduce the loading of Cu CMP and the process cost of TSV. Finally, we develop a novel Cu plating technique for direct TSH filling, meaning that the conducting template assembled on one side of the TSH in advance is unnecessary. Cu can fill the TSH directly in a middle-up mode. This filling mode can make sure of no void after electroplating. In addition, the barrier layer employed herein was formed through CoWP electroless plating to replace the traditional dry process for cost cut.