Chip Performance Research Articles

Dynamic visualization study of in situ cleaning of polystyrene microparticles off silicon wafer surface

With the improvement of chip performance, the requirements for cleaning the surface of silicon wafers are becoming higher. However, due to equipment and technology, it is difficult to observe the complex motion processes of particles at the microscopic scale. In this paper, an in situ dynamic visualization experiment on the cleaning of Polystyrene Latex (PSL) on the surface of silicon wafers is carried out by using a high-speed camera and image processing software. The mechanical behavior of PSL particles in fluid was investigated on a microscopic scale, and the trajectory and force of the polystyrene particles on the surface of the wafers were visualized, which provided a new perspective for understanding the complex cleaning process. Theoretical models were developed to explain the motion characteristics of the particles by calculating parameters such as van der Waals force, surface tension, and trailing force, and these models provide a theoretical basis for optimizing the cleaning process. There are four particle motion modes in the fluid: (1) interface capture, where the particles on the surface of silicon wafer are trapped by gas–liquid interface under surface tension; (2) particle collision, where the particles captured by the water film collide with the particles on the wafer surface to make the latter leave the silicon wafer; (3) jump attachment, where the particles jump and attach to the surface of the particle group under the action of lift; and (4) wall surface movement, where the particles start up under the action of water flow and then leave the silicon wafer quickly.

Research on Chip Manufacturing and Fault Detection Technology

In the wave of the digital era, the chip plays a key role in promoting the whole information technology revolution with its core position in the development of world science and technology. As the cornerstone of computing and data processing, the development of chips has promoted the progress of the entire technology field. The chip’s manufacturing is the key to determining the performance and computing power of the whole chip, and fault detection technology in the production process is an important part of determining the product’s quality and cost. Therefore, under the background of Moore’s law approaching the physical limit, how to ensure the yield of chip production while continuing to improve chip performance has become a major challenge for the chip manufacturing industry. Based on this, this paper summarizes the key manufacturing steps of the chip. The chip manufacturing technology is comprehensively sorted from design to silicon wafer manufacturing, photolithography, etching, ion implantation, and other processes. At the same time, the research direction of monocrystalline silicon manufacturing technology and the existing lithography technology are introduced, including optical lithography, extreme ultraviolet lithography, electron beam lithography, and so on. Fault detection technology in chip production has also been introduced. In addition, the chip manufacturing and fault detection technology introduced in this paper is summarized and its future development is prospected, which provides reference and inspiration for promoting the continuous progress of chip technology.

Quasi-visualizable detection of deep sub-wavelength defects in patterned wafers by breaking the optical form birefringence

Abstract In integrated circuit (IC) manufacturing, fast, nondestructive, and precise detection of defects in patterned wafers, realized by bright-field microscopy, is one of the critical factors for ensuring the final performance and yields of chips. With the critical dimensions of IC nanostructures continuing to shrink, directly imaging or classifying deep-subwavelength defects by bright-field microscopy is challenging due to the well-known diffraction barrier, the weak scattering effect, and the faint correlation between the scattering cross-section and the defect morphology. Herein, we propose an optical far-field inspection method based on the form-birefringence scattering imaging of the defective nanostructure, which can identify and classify various defects without requiring optical super-resolution. The technique is built upon the principle of breaking the optical form birefringence of the original periodic nanostructures by the defect perturbation under the anisotropic illumination modes, such as the orthogonally polarized plane waves, then combined with the high-order difference of far-field images. We validated the feasibility and effectiveness of the proposed method in detecting deep subwavelength defects through rigid vector imaging modeling and optical detection experiments of various defective nanostructures based on polarization microscopy. On this basis, an intelligent classification algorithm for typical patterned defects based on a dual-channel AlexNet neural network has been proposed, stabilizing the classification accuracy of λ/16-sized defects with highly similar features at more than 90%. The strong classification capability of the two-channel network on typical patterned defects can be attributed to the high-order difference image and its transverse gradient being used as the network's input, which highlights the polarization modulation difference between different patterned defects more significantly than conventional bright-field microscopy results. This work will provide a new but easy-to-operate method for detecting and classifying deep-subwavelength defects in patterned wafers or photomasks, which thus endows current online inspection equipment with more missions in advanced IC manufacturing.

Advancing high-volume GaN manufacturing: precision simulation of electrical and geometrical deviations through current spreading

Abstract Manufacturing process deviations pose significant challenges in GaN manufacturing especially when modern technologies demand extreme chip densities. More than a thousand of each of three distinct GaN-based flip-chips were manufactured where the standard deviations of the measured voltages ranged from 13 to 23 mV. By integrating Monte Carlo and finite element methods in the simulations which relies on the theoretical models, the results were validated by comparing the voltage measurements of the three thousand manufactured chips. Validation was even successful considering the voltage deviations of the three distinct designs equivalently, i.e., affected the geometrical and electrical properties in each wafer. In addition, comparing the three designs, Chip A emerged as the optimal choice for low current resistivity. Looking ahead, our theoretical modeling and simulation hold promise for high-accuracy predictions in high-volume GaN-based chip manufacturing, enhancing reliability and performance.

Axon-like active signal transmission

Any electrical signal propagating in a metallic conductor loses amplitude due to the natural resistance of the metal. Compensating for such losses presently requires repeatedly breaking the conductor and interposing amplifiers that consume and regenerate the signal. This century-old primitive severely constrains the design and performance of modern interconnect-dense chips1. Here we present a fundamentally different primitive based on semi-stable edge of chaos (EOC)2,3, a long-theorized but experimentally elusive regime that underlies active (self-amplifying) transmission in biological axons4,5. By electrically accessing the spin crossover in LaCoO3, we isolate semi-stable EOC, characterized by small-signal negative resistance and amplification of perturbations6,7. In a metallic line atop a medium biased at EOC, a signal input at one end exits the other end amplified, without passing through a separate amplifying component. While superficially resembling superconductivity, active transmission offers controllably amplified time-varying small-signal propagation at normal temperature and pressure, but requires an electrically energized EOC medium. Operando thermal mapping reveals the mechanism of amplification—bias energy of the EOC medium, instead of fully dissipating as heat, is partly used to amplify signals in the metallic line, thereby enabling spatially continuous active transmission, which could transform the design and performance of complex electronic chips.

Effects of Diethoxymethylsilane/Helium Flow Rate Ratio on Low-k Films Deposited by Plasma-Enhanced Chemical Vapor Deposition

As the semiconductor industry has continuously reduced the integrated circuit (IC) chip size, a resistance-capacitance (RC) delay emerged, causing deterioration of the chip performance. To reduce the RC delay, low dielectric constant (low-k) films with suitable mechanical strengths have been adopted as intermetal dielectrics (IMDs). In this study, low-k plasma-polymerized diethoxymethylsilane (ppDEMS) films were fabricated by plasma-enhanced chemical vapor deposition of the DEMS precursor with a flow rate ratio of the DEMS precursor to helium (He) carrier gas (DEMS/He FRR) as a key parameter. As the DEMS/He FRR increased, the refractive index was reduced from 1.401 to 1.386, and the k value decreased from 2.77 to 2.10. From high-resolution scans of C1s, O1s, and Si2p peaks of X-ray photoelectron spectroscopy, the carbon contents increased, and the oxygen contents decreased, along with a decrease in the film density. With the increased DEMS/He FRR, hardness decreased from 2.5 to 1.8 GPa, and elastic modulus decreased from 17.08 to 11.50 GPa. Leakage current densities for all the ppDEMS films were less than 10−7 A cm−2 at 1 MV cm−1. The ppDEMS films could be suggested as the IMDs according to their electrical and mechanical performance.

Effect of the pulsed current of on-chip thermoelectric cooler on temperature response during thermal shock in localized cooling

On-chip thermoelectric cooling (TEC) emerges as a promising solution to address the issue of localized chip overheating, effectively mitigating thermal shock induced by local heat flow conduction and enhancing both reliability and performance of chips. In this study, a three-dimensional numerical model is developed to investigate the effectiveness of on-chip thermoelectric cooler’s pulse current in mitigating temperature fluctuations caused by thermal shock at hot spots. The influence of the magnitude and lag time of the pulse current on the temperature fluctuation of Si chip during thermal shock is analyzed. The calculation results show that the implementation of on-chip TEC can effectively mitigate the issue of localized temperature overheating caused by thermal shock. By adjusting the maximum and minimum current of the on-chip thermoelectric cooler, it is possible to mitigate the fluctuation amplitude of chip temperature induced by thermal shock at the hot spot. The findings also indicate that the lag time between input current and thermal shock can lead to an increase in the maximum temperature of the chip. In addition, experimental results using commercially thermoelectric cooler also show that when the input current of TEC is pulse current, the temperature fluctuation caused by thermal shock can be reduced better.

Growth and characterization of micro-LED based on GaN substrate

As the diminution of micro-LED pixels advances, the pivotal role of dislocation phenomena becomes increasingly pronounced. This study provides insight into the key characteristics and dominant mechanisms of GaN-based micro-LEDs by comparing the homoepitaxial and heteroepitaxial configurations. Our findings reveal that variability in V-shaped pits distribution markedly influences the performance and uniformity of micro-LED chips. While the homoepitaxial micro-LEDs, alongside significantly reduced dislocation density and residual stress, effectively preclude the formation of them and thus ensuring superior uniformity both within and among micro-LED chips. Notably, the external quantum efficiency (EQE) peak of homoepitaxial micro-LEDs surpasses that of heteroepitaxial variants by 40%. Motivated by the realization that the reduced MQW thickness at the sidewalls of V-shaped pit aids carrier injection, a great enhancement in EQE from 7.9% to 14.8% (@ 10 A/cm2) was achieved by the optimization of homoepitaxial structure. Therefore, the growth of micro-LED with lower dislocation density, lower residual stress, and epi-structure of low-energy-barrier MQWs demonstrated the profound impact on advancing micro-LED technology to obtain the performance of high uniformity, high brightness, and low power consumption.

Computational-Aided Approach for the Optimization of Microfluidic-Based Nanoparticles Manufacturing Process.

In the last few years, the microfluidic production of nanoparticles (NPs) is becoming a promising alternative to conventional industrial approaches (e.g., nanoprecipitation, salting out, and emulsification-diffusion) thanks to the production efficiency, low variability, and high controllability of the production parameters. Nevertheless, the development of new formulations and the switching of the production process toward microfluidic platforms requires expensive and time-consuming number of experiments for the tuning of the formulation to obtain NPs with specific morphological and functional characteristics. In this work, we developed a computational fluid dynamic pipeline, validated through an ad hoc experimental strategy, to reproduce the mixing between the solvent and anti-solvent (i.e., acetonitrile and TRIS-HCl, respectively). Moreover, beyond the classical variables able to describe the mixing performances of the microfluidic chip, novel variables were described in order to assess the region of the NPs formation and the changing of the amplitude of the precipitation region according to different hydraulic conditions. The numerical approach proved to be able to capture a progressive reduction of the nanoprecipitation region due to an increment of the flow rate ratio; in parallel, through the experimental production, a progressive increment of the NPs size heterogeneity was observed with the same fluid dynamic conditions. Hence, the preliminary comparison between numerical and experimental evidence proved the effectiveness of the computational strategy to optimize the NPs manufacturing process.

A Review of Mechanism and Technology of Hybrid Bonding

Abstract With the development of semiconductor technology, traditional flip-chip bonding has been difficult to meet the high-density, high-reliability requirements of advanced packaging technology. As an advanced three-dimensional stacked packaging technology, Cu-SiO2 hybrid bonding technology can achieve high-density electrical interconnection without bumps, which expands the transmission performance and interconnection density of chips greatly. However, the investigation on Cu-SiO2 bonding is far from mature, and many researchers are studying Cu-SiO2 bonding passionately. There are many technologies that use different bonding mechanisms to achieve Cu-SiO2 bonding, which will affect the bonding strength directly. We review the mechanism and research progress of Cu-Cu bonding, SiO2-SiO2 bonding. What is more, we summarize the comparison of bonding conditions and bonding strength of various methods furtherly. According to the bonding mechanism, we propose some economical solutions for low-temperature Cu-SiO2 hybrid bonding, with the aim of providing certain references for the further development of advanced semiconductor packaging.

High-risk ARGs (HRA) Chip: A high-throughput qPCR-based array for assessment of high-risk ARGs from the environment

The global surge in antibiotic resistance genes (ARGs) presents a serious public health challenge. While methods like metagenomic analysis and qPCR arrays have been instrumental in investigating ARG distributions and dynamics, the vast diversity of ARGs often complicates effective monitoring and risk assessment. Here, we developed a High-Risk ARGs (HRA) chip based on high-capacity quantitative PCR array targeting previously identified high-risk ARGs. These ARGs are known to be prevalent in human-related environments, exhibit gene mobility, and are present in ESKAPE pathogens. The HRA chip include 101 primer sets and the 16S rRNA gene as a reference. These primer sets consist of 34 obtained from previous studies, and 67 newly designed primer sets which were validated in silico and experimentally. Absolute quantification of targeted ARGs is accomplished by generating standard curves for all ARGs with serially ten-fold diluted mixed plasmids containing targeted ARG sequences. The amplification efficiencies of all ARGs exceed 99% via plasmid template dilution tests, suggesting high reliability in quantification. The performance of HRA chip is further evaluated by practical applications in environmental samples from wastewater treatment plants (WWTPs) and soils with various land use types and fertilization regimes. The results indicate the dynamics of high-risk ARGs during wastewater treatment process, and reveal the profiles of soil high-risk ARGs which is distinct from those derived via metagenomic approaches. These findings highlight the potentials of HRA Chip in the evaluation of anthropogenic impacts on the environmental resistome with a more focused spectrum of high-risk ARGs. Overall, the HRA Chip emerges as a powerful and efficient high-throughput tool for rapid detection and quantification of high-risk ARGs, facilitating comprehensive profiling of high-risk resistomes in environmental samples which is essential for human health risk assessment of ARGs.

Balance regulation of heat transfer and flow performance in convective heat exchange process of microchannel plates

As high-performance computing devices continue to evolve toward miniaturization and integration, chip performance has increased significantly. However, chip dimensions are simultaneously shrinking. This trend has led to more challenging high heat flux density issues. Microchannel liquid cooling is an effective way to solve this issue, where the most critical aspect is the balance regulation of heat transfer performance and fluid dynamics. To address this challenge, this study initially divided a complete microchannel plate into two parts: an inlet distribution chamber (IDC) and an array structure. Subsequently, anentransy dissipation rate modeland apumping power consumption modelwere established for themicrochannel inlet diversion chamber, and an optimization design was carried out. This solved the problems of the optimal branch level and optimal channel size for designing the microchannel IDC within a given space. Next, themicrochannel array structurewas optimized to minimize boththermal resistanceandoverall flow resistance. This approach facilitated proactive optimization design for the microchannel array structure within the specified space. Finally, the independently optimizedinlet diversion chamberandarray structurewere combined into a complete optimized microchannel plate. Several comparative structures were also designed under the same constraints. Experimental research was conducted to validate the reasonableness of the optimization. The results indicated that, compared to randomly designed structures, the average overall performance of the optimized structure within the study scope hadincreased by at least 1.16 times, with the highest improvement reaching4.29 times. This study provides a theoretical reference for the active optimization design of microchannel plates in convective heat exchange process.

3D packaging and Moore’s Law

Abstract This paper describes how the semiconductor industry has seen steady improvements in key metrics such as performance, power consumption, and area, but as the semiconductor industry shrinks in device size and the technical challenges of ever-increasing performance demands, it is critical to improve chip performance for maximizing the operating frequency of individual ICs and reducing their power consumption. But when talking about improving chip performance, it is important not to focus solely on the individual integrated circuit (IC), but to evaluate it as part of the overall system. For example, as microprocessor frequency increases, so does the demand for main memory data. However, if the connections between the chips that transfer data to the processor do not keep pace with the increase in performance, these connections can become a bottleneck in the performance of the entire system. Instead, this paper describes a typical architecture for semiconductor 3D integration, highlights the technology choices for 3D integration implementation, and analyzes and explains the design challenges it presents. After outlining the above, this paper also analyzes the applications and achievements of 3D integration technology in recent years.

Screening of Methyl-β-cyclodextrins as an Antifading Agent for Cyanine Dye-Labeled Streptavidin to Improve the Performance of Genotyping Chips.

As a photostabilizing agent for cyanine dye, methyl-β-cyclodextrin (MβCD) was investigated as a possible antifading agent for cyanine dye-labeled proteins. Cyanine-3 (Cy3)-labeled streptavidin (SA-Cy3) solutions containing MβCD exhibited improved resistance against photobleaching. Further research revealed that MβCD can be used as a coating material on the surface of gene chips. Chips loaded with cyanine dye (Cy3 and Cyanine-5 (Cy5))-conjugated model microbeads exhibited resistance against photobleaching with MβCD coatings. MβCD coatings improved the imaging quality of model chips and resulted in higher discrimination ratios (DR) of single base recognition by a set of control beads (NP68). In a whole genome genotyping assay for human samples, the MβCD-coated samples were found to have a better clustering performance than the noncoated ones for a group of randomly picked single nucleotide polymorphisms (SNPs).

Thermal-flow-force-electrical coupling characteristics of microchannel cooling systems in high heat flux chips

To address the challenges faced by designers of multi-field coupled cooling systems for high heat flux chips, this paper proposes a “near-source” microchannel cooling strategy and establishes a thermal–flow-force electrically coupled model for chips. The effects of chip Joule heat and cooling water flow rate on the cooling performance with respect to multi-field coupling effects were studied. The impact of multi-field coupling effects was revealed, and a method for enhancing microchannel cooling performance in light of multi-field coupling effects is proposed. The results indicated that considering multi-field coupling effects in the microchannel cooling process leads to a deterioration in the thermal performance of chips, accompanied by a significant increase in electrical fluctuations and thermal deformation amplitude. Compared to chips upstream of the cooling water, chips downstream subjected to thermal cascade effects were more sensitive to multi-field coupling effects. Moreover, the temperature variance index, output current, and strain energy density of high heat flux chips were positively correlated with Joule heat but inversely proportional to the Reynolds number of the cooling water for cases in respect of multi-field coupling effects. Additionally, serpentine microchannels maximized the operational performance of high heat flux chips by reducing temperature of chip by up to 55.1%, decreasing strain energy density by 96.7%, and increasing input potential by 120%.

The Optimization Research on RF Chip Signal Processing Based on Deep Learning Algorithms

With the rapid development of wireless communication technology, radio frequency (RF) chips, as the core components of communication systems, directly influence the overall system performance through their signal processing capabilities. Traditional signal processing methods often struggle to achieve optimal results in the face of complex and variable communication environments. In recent years, deep learning technology, due to its powerful feature learning and pattern recognition capabilities, has shown tremendous potential in various fields. This paper addresses the signal processing issues of RF chips and proposes an optimization method based on deep learning algorithms. Firstly, the status and challenges of RF chip signal processing are analyzed, followed by the design of a deep learning model suitable for RF signal processing. Through data pre-processing and feature extraction, the generalization ability of the model is enhanced. Experimental results demonstrate that the proposed method outperforms traditional methods in signal noise suppression, interference cancellation, and signal distortion compensation, significantly improving the signal processing performance of RF chips. This research provides new ideas and methods for the application of deep learning in the field of RF chip signal processing and holds significant theoretical and practical importance for the future development of wireless communication systems.

Enhancing chip performance and reliability by CMOS+X technologies

Enhancing chip performance and reliability by CMOS+X technologies

Effect of temperature on GaN-integrated optical transceiver chips.

The gallium nitride (GaN) integrated optical transceiver chip based on multiple quantum wells (MQW) structure exhibits great promise in the fields of communication and sensing. In this Letter, the effect of ambient temperature on the performance of GaN-integrated optical transceiver chips including a blue MQW light-emitting diode (LED) and a MQW photodiode (PD) is comprehensively studied. Temperature-dependent light-emitting and current-voltage characteristics of the blue MQW LEDs are measured with the ambient temperature ranging from -70°C to 120°C. The experimental results reveal a decline in the electroluminescent (EL) intensity and an obvious redshift in the emission peak wavelength of the LED with increasing ambient temperature. The light detection performance of MQW PD under different temperatures is also measured with the illumination of an external blue MQW LED, indicating an enhancement in the PD sensitivity as the temperature rises. Finally, the temperature effect on the MQW PD under the illumination of the MQW LED on the GaN-integrated optical transceiver chip is characterized, and the PD photocurrent increases with higher ambient temperature. Furthermore, the measured temperature characteristics indicate that the GaN-integrated optical transceiver chip offers a promising application potential for optoelectronic temperature sensor.

Characterization of Transition Edge Sensors for Decay Energy Spectrometry

By using a superconducting transition edge sensor (TES) to measure the thermal energy of individual decay events with high energy resolution, decay energy spectrometry provides a unique fingerprint to identify each radionuclide in a sample. The proposed measurement requires optimizing the thermal parameters of the detector for use with 5 MeV scale energy deposited by alpha decay of the sample radionuclides. The thermal performance of deep-etched silicon TES chips is examined with the use of an onboard resistive heater. With known heater power and bath temperature, the thermal conductance, heat capacity, and frame temperature are calculated and compared to theory.

Measurement analysis of three phase intelligent electricity meter based on nonlinear load

In order to improve the accuracy of non-linear load measurement in three-phase smart meters, the author proposes a measurement analysis of three-phase smart meters based on non-linear loads. The author analyzed the nonlinearity of most differential amplifiers in metering chips, theoretically analyzed the reasons for low metering accuracy under non-linear loads, and analyzed and designed the reasons for phase errors in electric energy meters. The results indicate that: At 5 %, 20 %, 100 %, and 120 % of the rated current, the phase error limits of the current transformer are ±15 ', ±8', ±5 ', and ±5', respectively. At 5 % of the rated current, the phase error generated by the transformer reaches 100 % of the rated current and 3 times that of 120 %. This is also the reason for the large error in measuring small current signals in electric energy meters. ConclusionThe author provides a precise analysis and design method for nonlinear load measurement of three-phase smart meters to improve the performance of measurement chips and improve the accuracy of nonlinear load measurement.