Chip-on-film Research Articles

SI Considerations in Flexible Channels on High-Speed Intra-Panel Interface for Large-Size Flat Panel Display Applications

In flat panel display modules with a large-size and high-resolution for TV applications, signaling channels are relatively short on flexible printed circuit (FPC) cable or chip-on-film (COF) package when compared to those of the source PCBs. However, the short distance channels can significantly affect overall signal integrity (SI) performance. Thus, this letter focuses mainly on analysis and design of signal interconnection on FPC cable and COF package in terms of impedance matching and crosstalk. By optimizing the FPC cable design to mitigate crosstalk as well as insertion loss, the opening area of eye diagram was found to be improved more than twice over the previous one. In addition, through adjusting process of on-die capacitance of electro-static discharge (ESD) protection circuitry in the input stage of a high-speed circuit block, the created parasitic inductance of COF package trace was observed to be compensated. This optimization process can improve greatly system performance by widening the input eye opening. Finally, we propose channel design considerations and design guidelines to ensure better SI performance in flexible channels on high-speed intra-panel interface for large-size liquid crystal display (LCD) TV applications.

Wet chemical spray etching of the copper film for the application to chip on film in display devices

For achieving the fine pitch chip-on-film (COF) in display devices, wet chemical spray etching behaviors of the copper (Cu) films in the etching solutions with different cupric chloride (CuCl2) and hydrochloric acid (HCl) contents have been investigated. It is found that the etching rates and etching factors of the Cu films are strongly dependent on the composition of etchant solution and spray pressure, resulting from the chemical dissolution reaction and the kinetic energy of droplet, respectively. As a result, using the mixture of the CuCl2 and HCl, Cu films are defined successfully by wet chemical spray etching method, suggesting sufficient possibility for the application to fine pitch COF in the display devices.

Automatic Reel Editing in Chip on Film Quality Control With Computer Vision

Chip on film (COF) is a special packaging technology to pack integrated circuits in a flexible carrier tape. Chips packed with COF are primarily used in the display industry. Reel editing is a critical step in COF quality control to remove sections of congregating NG (not good) chips from a reel. Today, COF manufactures hire workers to count consecutive NG chips in a rolling reel with naked eyes. When the count is greater than a preset number, the corresponding section is removed. A novel method using object detection and object tracking is proposed to solve this problem. Object detection techniques including convolutional neural network (CNN), template matching (TM), and scale invariant feature transform (SIFT) were used to detect NG marks, and object tracking was used to track them with IDs so that congregating NG chips could be counted reliably. Using simulation videos similar to worksite scenes, experiments show that both CNN and TM detectors could solve the reel editing problem, while SIFT detectors failed. Furthermore, TM is better than CNN by yielding a real time solution.

Next-Generation Self-Assembled Anisotropic Conductive Adhesive Developed Using Solder Powder for Electrical Micro-Bonding in the Emerging IT Industry

The importance of the IT industry is becoming more and more prominent as it gradually changes to a non-face-to-face society after the COVID-19, and the next-generation smart devices of 5G mobile communication, micro LEDs, and wearable devices are emerging as the leading of the IT industry. Along with the development of these devices, limitations and problems of the Anisotropic Conductive Adhesive Film (ACF) used as a connection material for Film on Film (FOF), Chip on Glass (COG), Chip on Film (COF), and Film on Glass (FOG) are emerging. [1-5]

Latest advancement of fully additive process for 8 µm ultra-fine pitch chip-on-film (COF) by nano-size Ni–P metallization

This paper presents the first demonstration of a precision formation of conductor patterns as fine as 8 µm pitch for flex-based electronics assemblies. We have developed a novel fully additive process (FAP) by combining an ultra-thin chemical surface modification on polyimide (PI) to achieve a uniform Ni–P metallization and subsequent high-speed electrolytic pattern copper plating. On top of the modified interface, an ultra-thin anchoring layer (< 5 nm) constituting amide and carboxyl bonding is able to compensate the hydrophilic nature of the modification layer to obtain reliable adhesion even after being subjected to 300 °C heat treatment, as verified by XPS and TEM analysis at 1000kX. This exceptional property eliminates the trade-off concern by achieving both high-speed signal transmission and enhanced interfacial bond strength on a smooth surface (Ra < 60 nm). Experimental results revealed that the bending endurance and trace deformation characteristic of the fine pitch circuit by this FAP is comparable to conventional COF substrates and is also able to produce high-quality diffusion bonds with the formation of nano-twin structure on the Au–Au bonding interface. Insulation resistance measurements showed no metal residues and no current leakage between 16, 20, and 25 µm pitch COF after temperature humidity bias. On the basis of these results, FAP by direct Ni–P metallization proposed in this work provides unique opportunities for ultra-fine pitch and high electrical performance interconnects.

Research on Identification of Dust Particles on COF

Chip On Film(COF) is the key component of electronic products, and is different from Printed Circuit Board(PCB). The properties of high flexibility, thin thickness, lightweight and high wiring density make it difficult to inspect COF, especially dust particles interference. Dust particles are similar to defects, and it is hard to identify dust particles from defects, so dust particles interference of quality test is the difficulty of automatic surface defect detection. In this paper, a new method to identify dust particles is discussed from abnormal area called junction points detection and machine learning method Support Vector Machine(SVM) according to the characteristics of dust particles. As a result, a 94.8% correct rate of dust particles images identification has been achieved with the method.

Reliability of an ultra-fine-pitch COF flip-chip package using non-conductive paste

Ultra-fine-pitch chip-on-film (COF) packages such as display-drive-integrated circuit (DDI) modules are manufactured through an underfill process following Au-to-Sn thermo-compression bonding. As the interconnection pitch becomes finer and is reduced to less than 25 um, however, an alternative flip-chip technology, such as non-conductive paste (NCP) bonding, is needed in place of the capillary underfill process. In this study, new NCP formulations are investigated to achieve rapid curing at a temperature high enough to form a metallic bond between the bump and the pad. An appropriate curing agent was determined through a dielectric analysis (DEA). COF samples were prepared with a DDI chip 11,772 × 924 um in size and with a 38 um-thick polyimide flexible printed circuit by both NCP bonding and thermo-compressionunderfill processes. Pressure cooker tests lasting as long as 192 h revealed that the reliability of the NCP sample against high temperatures and high humidity levels exceeded somewhat that of the underfill sample. In thermal cycling test up to 500 cycles, however, the reliability of the NCP sample was inferior to that of the underfill sample. It was considered that unbonded faults and NCP trapping at the bump-to-pad joint were responsible for the premature failure of the NCP sample under a thermal cycling condition.

Experimental and Numerical Investigation Into the Influence of Chip-on-Film Package on Component Operating Temperature in Natural Convection

The thermal issues of chip-on-film (COF) packages are becoming increasingly important for high-pin-count chips, whose performance is becoming increasingly limited by the maximum power that can be spread without exceeding the maximum junction temperature. This paper conducts an experimental investigation to investigate the relationship between power dissipation and the surface temperature of the thermal chip in COF applications. This paper develops an ANSYS finite-element (FE) model to simulate the junction temperature and temperature distribution within the COF package under various boundary conditions. Based on an effective methodology of equivalent models for thermal conductance, comparing the simulation results with the experimental temperature measurements confirms the validity of the numerical model. This paper uses the proposed model in a $\hbox{2}^{3}$ factorial design process to evaluate the effect of the major components of COF packages. Results show that the thickness of copper lead plays a significant role in efficient thermal power dissipation of the package due to its inherent advantage. Several parametric studies reveal the effects of various configurations of the thermal model and the effects of the voids. This paper also analyzes the thermal resistance at the junction of the package. Results show that the natural convection of the COF package with thermally conductive tape achieves a cooling function that keeps the junction temperature of the COF package under 85 $^{\circ}\hbox{C}$ without using a fan. The validated FE models in this paper have enormous potential to quickly assess the thermal limits of many future COF packages and their variations.

참조영상 기반의 COF 결함 검출 및 분류 시스템

This paper presents an efficient defect detection and classification system based on reference image for COF (Chip-on-Film) which encounters fatal defects after ultra fine pattern fabrication. These defects include typical ones such as open, mouse bite (near open), hard short and soft short. In order to detect these defects, conventionally it needs visual examination or electric circuits. However, these methods requires huge amount of time and money. In this paper, based on reference image, the proposed system detects fatal defect and efficiently classifies it to one of 4 types. The proposed system includes the preprocessing of the test image, the extraction of ROI, the analysis of local binary pattern and classification. Through simulations with lots of sample images, it is shown that the proposed system is very efficient in reducing huge amount of time and money for detecting the defects of ultra fine pattern COF.

Effects of Nanofiber on the Electrical Properties of Anisotropic Conductive Adhesives (ACAs)

The effects of nanofiber on the electrical properties of anisotropic conductive films (ACFs) were investigated from the perspectives of the joint and insulation resistances. To obtain stable electrical properties for fine-pitch chip-on-film (COF) packages, two kinds of nanofiber ACFs were demonstrated: (1) polystyrene (PS) and polyacrylonitrile (PAN) nanofiber ACFs, which were formed by laminating ACFs on the top and bottom sides of PS and PAN nanofibers, and (2) PAN nanofiber coupled with conductive particle (PAN/Cp nanofiber) ACF, which was made by laminating non conductive films (NCFs) on both sides of a PAN/Cp nanofiber. The effects of the nanofiber thickness, melting, and structure on the electrical properties of the nanofiber ACFs were analyzed. Among the two different nanofiber ACFs, the PAN/Cp nanofiber ACF showed the most stable joint resistance (below 4 mOmega) and insulation resistance (above 10(8) Omega (between 7 microm bump space) due to the thin insulation layer.

Effects of Hardeners on the Low-Temperature Snap Cure Behaviors of Epoxy Adhesives for Flip Chip Bonding

Various adhesive materials are used in flip chip packaging for electrical interconnection and structural reinforcement. In cases of COF(chip on film) packages, low temperature bonding adhesive is currently needed for the utilization of low thermal resistance substrate films, such as PEN(polyethylene naphthalate) and PET(polyethylene terephthalate). In this study, the effects of anhydride and dihydrazide hardeners on the low-temperature snap cure behavior of epoxy based non-conductive pastes(NCPs) were investigated to reduce flip chip bonding temperature. Dynamic DSC(differential scanning calorimetry) and isothermal DEA(dielectric analysis) results showed that the curing rate of MHHPA(hexahydro-4-methylphthalic anhydride) at <TEX>$160^{\circ}C$</TEX> was faster than that of ADH(adipic dihydrazide) when considering the onset and peak curing temperatures. In a die shear test performed after flip chip bonding, however, ADH-containing formulations indicated faster trends in reaching saturated bond strength values due to the post curing effect. More enhanced HAST(highly accelerated stress test) reliability could be achieved in an assembly having a higher initial bond strength and, thus, MHHPA is considered to be a more effective hardener than ADH for low temperature snap cure NCPs.

칩 온 필름을 위한 자동 결함 검출 시스템 개발

본 논문에서는 <TEX>$30{\mu}m$</TEX> 이하의 초 미세 피치를 가진 칩 온 필름(chip-on-film, COF)에서 자주 발생하는 결함을 자동으로 검출할 수 있는 시스템을 제안한다. 개발된 시스템은 초 미세 패턴의 개방 및 단락 결함 뿐만아니라 소프트 개방 및 소프트 단락을 신속히 검출할 수 있는 회로 및 기술이 적용되어 있다. 결함 검출의 기본 원리는 결함 전의 패턴 저항값과 결함 후의 패턴 저항값 차에 의해 발생하는 미세 차동 전압을 읽어서 결함 유무를 판단한다. 또한 미세전압 차를 증폭시켜 결함 유무를 쉽게 판단할 수 있도록 고주파 공진기를 이용한다. 제안된 시스템은 초미세 패턴 COF 검사 과정에서 발생하는 다양한 결함을 신속하고 정확히 검출할 수 있으므로 기존의 COF 검사 시스템의 대안이 될 것으로 기대한다. This paper presents an automatic system to detect variety of faults from fine pitch COF(chip-on-film) which is less than <TEX>$30{\mu}m$</TEX>. Developed system contains circuits and technique to detect fast various faults such as hard open, hard short, soft open and soft short from fine pattern. Basic principle for fault detection is to monitor fine differential voltage from pattern resistance differences between fault-free and faulty cases. The technique uses also radio frequency resonator arrays for easy detection to amplify fine differential voltage. We anticipate that proposed system is to be an alternative for conventional COF test systems since it can fast and accurately detect variety of faults from fine pattern COF test process.

차영상을 이용한 실시간 TCP/COF 검사 시스템 개발

본 논문에서는 TCP/COF의 불량패턴 검출 알고리즘을 제안하고 실시간 검사 시스템을 구현하였다. TCP/COF는 마이크로미터 단위의 패턴 굵기를 갖는 관계로 검사를 위해서는 작업자가 고성능 현미경을 보며 전수 검사 해야 하는 어려움이 있다. 이에 본 연구에서는 작업자로 하여금 모니터를 보면서 검사시스템이 검출해내는 불량에 대해서 검사할 수 있는 시스템을 제안하였다. 검사 알고리즘은 기준 영상과 검사 영상간의 패턴 비교 방법에 의해 수행된다. TCP/COF의 특성에 맞는 고성능 카메라 및 조명시스템을 구현하기 위하여 카메라의 종류와 조명의 형태 및 광원에 따른 다양한 실험을 수행하였다. 실험결과 구현된 검사 시스템은 TCP/COF 필름의 불량 위치를 작업자에게 정확하게 알려줌을 확인할 수 있었다. In this paper, we proposed a faulty pattern detection algorithm of TCP(Tape Carrier Package)/COF(Chip On Film), and implemented a real-time system for inspecting TCP/COF. Since TCP/COF has very high resolution having several micro meters, the human operator should visually inspect all the parts through microscope. In this work, we implement an inspection system to detect the faulty pattern, so the operator can visually inspect only the designated parts by the inspection system through the monitor. The proposed defects detection algorithm for TCP/COF packages is implemented by the pattern matching method based on subtracting the reference image from test image. To evaluate performance of the proposal system. we made various experiments according to type of CCD camera and light source as well as illumination projection method. From experimental results, it is confirmed that the proposed system makes it possible to detect effectively the defective TCP/COF film.

Studies on various chip-on-film (COF) packages using ultra fine pitch two-metal layer flexible printed circuits (two-metal layer FPCs)

Various fine pitch chip-on-film (COF) packages assembled by (1) anisotropic conductive film (ACF), (2) nonconductive film (NCF), and (3) AuSn metallurgical bonding methods using fine pitch flexible printed circuits (FPCs) with two-metal layers were investigated in terms of electrical characteristics, flip chip joint properties, peel adhesion strength, heat dissipation capability, and reliability. Two-metal layer FPCs and display driver IC (DDI) chips with 35μm, 25μm, and 20μm pitch were prepared. All the COF packages using two-metal layer FPCs assembled by three bonding methods showed stable flip chip joint shapes, stable bump contact resistances below 5mΩ, good adhesion strength of more than 600gf/cm, and enhanced heat dissipation capability compared to a conventional COF package using one-metal layer FPCs. A high temperature/humidity test (85°C/85% RH, 1000h) and thermal cycling test (T/C test, −40°C to +125°C, 1000cycles) were conducted to verify the reliability of the various COF packages using two-metal layer FPCs. All the COF packages showed excellent high temperature/humidity and T/C reliability, however, electrically shorted joints were observed during reliability tests only at the ACF joints with 20μm pitch. Therefore, for less than 20μm pitch COF packages, NCF adhesive bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for over 25μm pitch COF applications. Furthermore, we were also able to demonstrate double-side COF using two-metal layer FPCs.

Properties Investigation on Chip-on-Film (COF) Thermosonic Bonding Using Anisotropic Conductive Films (ACFs)

Chip-on-film (COF) technology has been developed for liquid crystal displays (LCD) due to its high yield capability in fine pitch products. In this study, a new COF thermosonic (TS) bonding process using anisotropic conductive adhesive and ultrasonic vibrations will be introduced. Si chips with 16 cylindrical Cu bumps (¤100µm) and polyimide (PI) film substrate with a thickness of 70µm were prepared. For the bonding condition, the bonding temperature and ultrasonic time were varied from 413 to 453K and from 0.5 to 1s, respectively. Also, thermocompression (TC) bonding was conducted with a bonding temperature of 453K and bonding time of 8s to compare it to the bonding characteristics of TS bonding. The shear strength and electrical resistance of COF assemblies were measured to verify the feasibility of COF TS bonding using ACFs. The cross-sectional inspection and fracture surface analysis of COF joints were also conducted using field-emission scanning electron microscopy (FE-SEM). As a result, the mechanical and electrical properties of the COF assembly were improved by increasing the bonding temperature and ultrasonic dwell time. It was also determined that ultrasonic energy has a significant influence in improving the mechanical and electrical properties of the TS COF assembly. [doi:10.2320/matertrans.MB201210]

Optimization of screen-printing parameters of SN9000 ink for pinholes using Taguchi method in chip on film packaging

The influence of pinholes on the chip on film (COF) in screen-printing was studied in this paper. Yield improvement is the most challenging part of COF manufacturing in view of its processing complexity, mainly in the screen-printing process. The process parameters such as ink capacity, origin control distance, angle of the squeezer, method of mixing, freshness of ink, speed of printing, and speed of scraper are considered to improve the pinholes. In Taguchi method, a two level orthogonal array is used to determine the signal-to-noise (S/N) ratio. Analysis of variance and the F-test values are used to determine the most significant process parameters affecting the pinholes. Confirmation analysis tests with the optimal levels of process parameters are carried out. The results of the experiment show that Taguchi method is a very suitable approach with regard to solving quality problems related to such pinholes.

An experimental and numerical investigation into the effects of the chip‐on‐film (COF) processing parameters on the Au‐Sn bonding temperature

PurposeThe reliability of chip‐on‐film (COF) packages is fundamentally dependent upon the quality of the eutectic Au‐Sn joint formed between the Au bumps on the integrated circuit (IC) device and the Sn‐plated Cu inner leads. Therefore, it is essential that an appropriate bonding temperature is achieved during the inner lead bonding (ILB) process. The purpose of this paper is to identify the optimal processing conditions which maximize the reliability of the Au‐Sn joints.Design/methodology/approachThe paper commences by performing an experimental investigation to establish the temperature at three specific locations within the COF/ILB system in a typical gang‐bonding process. The relationship between the setting temperature of the bonding tool and the temperature of the tool surface is then calibrated using an off‐line experimental system. An ANSYS finite element (FE) model is then constructed to simulate the temperature distribution within the COF/ILB system under representative temperature conditions. The validity of the numerical model is confirmed by comparing the simulation results with the experimental temperature measurements. The FE model is then used in a 23 factorial design process to evaluate the effect of the principal COF/ILB processing parameters, namely the contact area, the tool temperature and the stage temperature, on the temperature induced at the interface between the Au bumps on the IC chip and the Sn‐coated Cu leads on the polyimide film.FindingsThe results reveal that the interfacial bonding temperature is determined primarily by the stage temperature.Originality/valueA regression analysis model is applied to the factorial design results to construct a COF/ILB design chart which enables the rapid identification of the stage and tool temperatures required to achieve the minimum feasible eutectic bonding temperature.

Failure mechanism of COF based Line Driver IC for Flat Panel Display by contamination

This study is about the field failure and mechanism of Chip on Film (COF) based Line Driver IC (LDI) for FPD. Due to LDI failure, there is vertical line defect on Flat Panel Display (FPD). Contamination is detected in bumps of LDI which is packaged by Resin. Chemical and physical method has applied for analyzing the elements and the isolation of contamination. The first detected contamination type is Gold (Au). The second contamination type is the mixed material of metal particle and organic material like Aluminum (Al), Iron (Fe), Chrome (Cr). It is found that all contamination is getting in during the Inner Layer Bonding (ILB) process. In case of Au contamination, remained Au particle is getting into the surface of collet (Rubber) which is used for Chip pick-up with collet particle. Fe, Cr, Al contamination is floating dust inside of the equipment and getting into with all kinds of dust. Dust inside is getting energy from temperature, moisture, Bias, catalyst. As a result, each contamination could cause short in bumps in LDI due to Au migration and by changing the characteristic from high resistor to low resistor.

Optimization of Bonding Force, Sinking Value, and Potting Gap Size in COF Inner Lead Bonding Process

The thermo-mechanical properties of the polyimide film used in chip-on-film (COF) packaging have a significant effect on the inner lead bonding (ILB) mechanism. Furthermore, specifying an appropriate bonding force is essential in establishing a suitable compromise between a good bonding strength in the ILB process and a suitable gap size for the subsequent resin potting process. This paper commences by performing a series of experimental micro-force tensile tests to investigate the stress-strain relations of two polyimide films, namely Kapton-EN and Espanex-M. The tests are performed using formfitting specimens from actual COF products at various temperatures ranging from 25degC to 200degC . Based on the experimental results, constitutive equations are developed to model the temperature-dependent stress-strain characteristics of the two films. A finite element model of the COF/system comprising the thermo-compression tool, the polyimide film, the copper lead and the gold bump is constructed and is used to simulate the ILB process under various bonding forces. A good agreement is found between the experimental and numerical results obtained for the deformed profile of a single polyimide/copper lead following the bonding process and the variation of the bump sinking value with the bonding force, respectively. The numerical results are used to construct COF/ILB parameter design charts for the Kapton-EN and Espanex-M polyimide films which enable suitable values of the bonding force to be selected for given gap size and bump sinking values. In general, the results show that Kapton-EN has a broader working range than Espanex-M as a result of its higher elastic stiffness. When performing the ILB process using Espanex-M polyimide film, it is necessary to carefully control the bonding force to ensure that the minimum potting gap size is maintained.

Board-Level ESD of Driver ICs on LCD Panel

In this paper, a method utilizing a charged-device model (CDM) test by the tape carrier package or chip-on-film (COF) samples to emulate the real-world board-level CDM or charged-board model (CBM) electrostatic discharge is proposed for large-sized chips such as liquid-crystal display (LCD) driver ICs, which successfully duplicated the same failure by CBM discharging. For small-sized chips, the evaluation board (or printed circuit board) emulation should minimize the parasitic <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RLC</i> loading of the interconnection on the board to achieve a more accurate CBM discharging. In addition, guidelines regarding chip-level design and layout optimization are proposed and have been successfully implemented to improve the immunity.