Chip Interconnection Research Articles

Research Progress of Palladium-Plated Copper Bonding Wire in Microelectronic Packaging.

Wire-bonding technology is the most commonly used chip interconnection technology in microelectronic packaging. Metal bonding wire is the key material for wire bonding and plays an important role in the reliability of electronic devices. In recent years, palladium-plated copper (PdCu) bonding wire has been widely used because of its low cost, good electrical and thermal conductivity, the fact that it is not easy to oxidize, and its high reliability. Therefore, it is necessary to review its research progress. In this paper, the preparation and application of palladium-plated copper bonding wire are reviewed. Firstly, the preparation methods of electroplating, electroless plating, and direct plating are introduced. Secondly, the factors affecting the distribution of Pd in free air balls and bonding interfaces, the effect of Pd on the formation and growth of intermetallic compounds in PdCu wire, stitch bond, and reliability of PdCu wire are summarized and analyzed in the application process. Finally, its development prospect is prospected. Hopefully, this review can help readers to have a comprehensive understanding of the preparation and application of palladium-plated copper bonding wires, and can accelerate the promotion of its application in more fields in the future.

Study on preparation and sintering properties of nano-silver-coated tin slurry

A nano-sized silver-coated tin (Sn@Ag) slurry was prepared by heterogeneous flocculation method by adjusting the pH value of solution and selecting different dispersants. The slurry improved the oxidation resistance of tin and its dispersibility in silver matrix. The sintering strength of nanometre Sn@Ag slurry increases with the increase of Sn content. When the Sn content reaches 5%, the shear strength of the joint reaches the highest 50 MPa, which is more than 10 MPa higher than that of the pure nanometre silver slurry sintered joint. The increase of shear strength is due to the fact that the equilibrium phase formed after sintering is Ag–Sn replacement solid solution and intermetallic compound Ag 3 Sn, which have the effect of replacement solution strengthening and dispersion strengthening, respectively. It is proved by experiments and analysis that the application of nano-silver paste in chip interconnection is feasible. The research of this subject provides experimental reference and theoretical basis for the application of new generation interconnect materials in power devices and promotes the development of microelectronics packaging technology.

Crosstalk Analysis of Delay-Insensitive Code in High-Speed Package Interconnects.

The development of integrated circuits has increased the size of chip interconnects, which has brought challenges to interconnect design in chip packages. The closer the spacing between interconnects, the higher the space utilization, which can cause severe crosstalk problems in high-speed circuits. In this paper, we applied delay-insensitive coding to the design of high-speed package interconnects. We also analyzed the effect of delay-insensitive coding on crosstalk improvement in package interconnects at 26 GHz for its high crosstalk immunity. Compared to the synchronous transmission circuit, the 1-of-2 and 1-of-4 encoded circuits designed in this paper can reduce crosstalk peaks by 22.9% and 17.5% on average at a wiring spacing of 1-7 μm, which can achieve closer wiring spacing.

Effect of reflow temperature and solder size on Cu-Ni cross-interaction in the Cu/Sn/Ni micro solder joints

PurposeSolder bumps for chip interconnections are downsizing from current approximately 100 µm to the expected 1 µm in future. As a result, the Cu-Ni cross-interaction in Cu/Solder/Ni solder joints will be more complicated and then strongly influence the growth of the intermetallic compounds (IMCs). Thus, it is critical to understand the fundamental aspects of interfacial reaction in micro solder joints. This paper aims to reveal the effect mechanism of reflow temperature and solder size on the interfacial reaction in Cu/Solder/Ni solder joints.Design/methodology/approachThe Cu-Ni cross-interaction in the Cu/Sn/Ni micro solder joints with 50 and 100 µm solder sizes at 250°C and 300°C were observed, respectively. The line-type interconnects were soaked in silicone oil, and the temperature of the line-type interconnects was 250 ± 3°C and 300 ± 3°C, which were monitored by a fine K-type thermocouple, and followed by an isothermal aging process at various times. After aging, the specimens were removed from the silicone oil and cooled in the air to room temperature.FindingsThe major interfacial reaction product on both interfaces was (Cu,Ni)6Sn5, and the asymmetric growth of (Cu,Ni)6Sn5, evidenced by the thickness of (Cu,Ni)6Sn5 IMCs at the Sn/Ni interface was always larger than that at the Sn/Cu interface, resulted from the directional migration of Cu atoms toward the Sn/Ni interface under Cu concentration gradient. The morphology of (Cu,Ni)6Sn5 IMC at Sn/Cu interface was columnlike at 250°C, and which changed from columnlike to scallop with large aspect ratio at 300°C, while that at Sn/Ni interface gradually evolved from needlelike to the mixture of needlelike and layered at 250°C, and which evolved from needlelike to scallop with large aspect ratio at 300°C. The evolution of morphology of (Cu,Ni)6Sn5 is attributed to the content of Ni. Furthermore, the results indicate that the Cu-Ni cross-interaction was stronger with small solder size and relatively low temperature in the Cu/Sn/Ni micro solder joints.Originality/valueThe asymmetric growth of (Cu,Ni)6Sn5 in the Cu/Sn/Ni micro solder joints, evidenced by the thickness of (Cu,Ni)6Sn5 IMCs at the Sn/Ni interface, was always larger than that at the Sn/Cu interface. The morphology evolution of (Cu,Ni)6Sn5 IMC at both interfaces was attributed to the content of Ni. The Cu-Ni cross-interaction was stronger with small solder size and relatively low temperature in the Cu/Sn/Ni micro solder joints.

On Allocation Algorithms for Manycore Systems With Network on Chip

Single-chip multicore processors and their network on chip interconnection mechanisms have received extensive interest since the early 2000s. The mesh topology is popular in networks on chip. A common issue in mesh is that it can result in high energy consumption and chip temperatures. It has been recently shown that mapping communicating tasks to neighboring cores can reduce communication delays and the associated power consumption and improve throughput. This paper evaluates the contiguous allocation strategy first fit and non-contiguous allocation strategies that attempt to achieve a degree of contiguity among the cores allocated to a job. One of the non-contiguous strategies is a new strategy, referred to as neighbor allocation strategy, which decomposes the job request so that it can be accommodated by free core submeshes and individual cores that have degree of contiguity. The results show that the relative merits of the policies depend on the job's communication pattern.

Design for Testability Methods for Detecting Resistive Opens at Chip Interconnects

Design for Testability Methods for Detecting Resistive Opens at Chip Interconnects

Numerical and experimental study on cooling high power chips of data centers using double-side cooling module based on mini-channel heat sink

With continuous increase in chip power, cooling has gradually evolved into the bottleneck restricting the development of data centers (DCs). In this study, a double-side cooling module based on mini-channel heat sink was proposed to solve the heat dissipation of multi-high power chips on the computing server of DCs. Numerical simulations were carried out to optimize the geometry of the cooling module and experiments were set up to test its cooling performance. The results show that staggered fins and parallel channels are beneficial to the heat transfer of the cooling module. Compared with traditional fins, the staggered fins bring a more uniform temperature distribution and reduce the maximum temperature of the chip because of the improved flow field. Compared with series channels, the maximum temperature and pressure drop of the heat sink with parallel channels can be decreased at the same time without changing inlet flow rate or heat transfer area. The cooling module was fabricated and assembled consisting of four heat sinks based on the optimized geometries. The experimental results indicate that it is capable of solving the cooling of 8 CPUs, 8 interconnect chips and multiple power supply chips on computing server with a total power up to 4400 W in 1U space when using water as coolant (10 L/min & 20 ℃). The maximum shell temperature of all CPUs can be kept under 45 ℃ when single chip power reaches 440 W. The assembly density of DCs can be doubled when cooled by this new module. These results imply that this cooling module is a promising solution for cooling DCs with high power and assembly density.

Research Progress on Bonding Wire for Microelectronic Packaging

Wire bonding is still the most popular chip interconnect technology in microelectronic packaging and will not be replaced by other interconnect methods for a long time in the future. Au bonding wire has been a mainstream semiconductor packaging material for many decades due to its unique chemical stability, reliable manufacturing, and operation properties. However, the drastic increasing price of Au bonding wire has motivated the industry to search for alternate bonding materials for use in microelectronic packaging such as Cu and Ag bonding wires. The main benefits of using Cu bonding wire over Au bonding wire are lower material cost, higher electrical and thermal conductivity that enables smaller diameter Cu bonding wire to carry identical current as an Au bonding wire without overheating, and lower reaction rates between Cu and Al that serve to improve the reliability performance in long periods of high temperature storage conditions. However, the high hardness, easy oxidation, and complex bonding process of Cu bonding wire make it not the best alternative for Au bonding wire. Therefore, Ag bonding wire as a new alternative with potential application comes to the packaging market; it has higher thermal conductivity and lower electric resistivity in comparison with Cu bonding wire, which makes it a good candidate for power electronics, and higher elastic modulus and hardness than Au bonding wire, but lower than Cu bonding wire, which makes it easier to bond. This paper begins with a brief introduction about the developing history of bonding wires. Next, manufacturability and reliability of Au, Cu, and Ag bonding wires are introduced. Furthermore, general comparisons on basic performance and applications between the three types of bonding wires are discussed. In the end, developing trends of bonding wire are provided. Hopefully, this review can be regarded as a useful complement to other reviews on wire bonding technology and applications.

Single-photon splitting by polymeric submicropillars structures

Optical splitters are one of the most important interconnects in the optical chips of future optical quantum computers. Here, we introduce novel quantum photonic splitters based on polymeric submicropillars that split the single-photon signal generated by a colloidal quantum dot (QD) into multiple outputs, which can be easily accessed through a conventional confocal scanning optical system. Using a single continuous-wave laser with a low absorption wavelength for both polymer material and QDs, we were able to first deterministically place a single-photon emitter (SPE) within one of the submicropillars and then characterize the single-photon guiding effect of the fabricated structures. The submicropillars, with their size and position which are comprehensively optimized by numerical simulations, act as single-mode directional coupler guiding both the laser excitation and the single-photon emission thanks to the evanescent wave coupling effect. With one-step fabrication, we can create a well-distributed array of “imaginary” SPEs from an original SPE. Our method opens various applications in integrated devices based on solid-state quantum emitters.

RF and Crosstalk Characterization of Chip Interconnects Using Finite Element Method

This paper presents new finite element method (FEM) based approach for radio frequency (RF) and crosstalk (X talk) characterization of chip interconnects. Being based on scattering parameters (S-parameters), this approach truly and accurately demonstrates the transmission line behavior of chip interconnects over a wideband of frequencies. To demonstrate FEM based method, a single-line and a 3-line interconnect test structures on SiO2-Si substrate have been designed and simulated in High Frequency Structure Simulator (HFSS). The RF and crosstalk characterization of chip interconnect materials Copper (Cu), doped multilayer Graphene Nanoribbon (DMLGNR), and neutral multilayer Graphene Nanoribbon (NMLGNR) have been demonstrated in terms of transmission coefficient (Sij & Smn) from 1 to 1000 GHz. The single-line three-dimensional (3D) structures comprising of Cu, DMLGNR, and NMLGNR have maximum transmission loss values of -15.93 dB, -22.03 dB, and - 13.73 dB at frequencies of 643 GHz, 402 GHz, and 643 GHz, respectively whereas three-line bus structure exhibit maximum victim-line transmission loss values of -15.28 dB, -17.47 dB, and -15.98 dB at frequencies of 247 GHz, 829 GHz, and 377 GHz, respectively. Further, the crosstalk results have demonstrated that as frequency increases significant crosstalk is observed between nearby lines due to electromagnetic interference and coupling (EMI/EMC) issues.

Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures

The integrated fan-out (InFO) wafer-level chip-scale package (WLCSP) is introduced for modern system-in-package designs with larger I/O counts, higher interconnection density, and small form factors. A redistribution layer (RDL) in an InFO package is an extra metal layer for interchip connections, and RDL routing is crucial for achieving desired interchip connections. In a high-density InFO package, multiple RDLs with flexible vias are often adopted. To integrate chips of different technology nodes into one package, irregular pad structures need to be considered; however, no published RDL routing work considers flexible vias or irregular pad structures. This article formulates a new RDL routing problem with unified-assigned pad pairs on a via-based multilayer multichip InFO package with irregular pad structures and presents the first algorithm for this problem. The algorithm consists of a preprocessing stage, three routing stages, and a layout optimization stage. The preprocessing stage analyzes routing resources and potential routing congestion. The first routing stage performs layer assignment based on a weighted maximum planar subset of chords algorithm to route interchip nets concurrently. The second routing stage constructs a 3-D routing graph based on partitioned octagonal tiles to handle the irregular layout structure and applies A*-search to route remaining interchip nets. The third routing stage transforms a routing graph into a network-flow model to perform concurrent routing for chip-to-board nets by applying the minimum-cost maximum-flow algorithm. Finally, we develop an efficient linear-programming-based layout optimization algorithm to find desired solutions. Experimental results show that our router can achieve 100% routablility for all benchmarks under limited RDLs, while the previous state-of-the-art work cannot.

(Invited) Chemistry Effects on the Electrodeposition of Re, Co, and Alloys

Electrodeposition has been adopted in various metallization processes. It allows conformal and super-conformal deposition on curved and recessed substrates, enables the fabrication of metals and alloys with well controlled composition, impurity, and grain structure, and provides fast growth rate, high throughput, and low cost of ownership. Organic additives have been used in electrolytes to tune not only the growth behavior, but also the impurity and grain structure of the deposited material. The most well-known cases are those used for magnetic alloy plating[1,2] in storage and MEMS industry and for damascene copper plating[3,4] in microelectronic industry. On the other hand, the electrolyte itself has largely remained aqueous for most cases. Organic solvents, room temperature ionic liquids, and deep eutectic systems have been widely studied with, however, relatively limited success in large scale adoption.The first part of this talk will introduce some studies on the electrodeposition of Cobalt as an alternative metal for semiconductor interconnect applications. Organic additives that tailor the deposition rate of cobalt are used to enable the Co filling in sub-micron structures. The effect of such additives on the impurity incorporation and film grain structure will be discussed. The second part of the talk will discuss some recent studies on the electrodeposition from “water-in-salt” electrolytes, where the hydration of a super high concentration of supporting salt depletes the free water molecules in the aqueous solution, thus limiting the hydrogen evolution reaction. The discussion will be in a context of Re and ReCo alloy deposition for superconducting connector applications for quantum devices. REFERENCES T. Osaka, M. Takai, K. Hayashi, K. Ohashi, M. Saito, and K. Yamada, A soft magnetic CoNiFe film with high saturation magnetic flux density and low coercivity, Nature, 1998, 392(6678), 796. E.I. Cooper, C. Bonhôte, J. Heidmann, Y. Hsu, P. Kern, J.W. Lam, M. Ramasubramanian, N. Robertson, L.T. Romankiw, and H. Xu, Recent developments in high-moment electroplated materials for recording heads, IBM Journal of Research and Development, 2005, 49(1), 103. P. Andricacos, C. Uzoh, J. Dukovic, J. Horkans, and H. Deligianni, Damascene copper electroplating for chip interconnections, IBM Journal of Research and Development, 1998, 42(5), 567. T.P. Moffat, J.E. Bonevich, W.H. Huber, A. Stanishevsky, D.R. Kelly, G.R. Stafford, and D. Josell, Superconformal Electrodeposition of Copper in 500–90 nm Features, Journal of The Electrochemical Society, 2000, 147, 4524.

Investigation of stress relaxation in SAC305 with micro-Raman spectroscopy

In the paper, μ-Raman spectroscopy is applied as non-destructive test method to access the creep in chip interconnection materials. To develop the method, a silicon test chip is soldered onto a copper substrate using SAC305 and the strain of the silicon crystal in the top surface of the chip is measured time dependent after assembly by the Raman shift. The in-plane stress in silicon crystal decreased exponentially within several days after soldering. To access the strain in the solder material a finite element model was calibrated based on the experimental data applying the Anand creep model and fitting its parameter. The analysis reveals the applicability of μ-Raman measurement to assess creep within interconnect material in microelectronic assemblies.

Experimental studies on application of silver paste in thermosonic flip-chip bonding

In this subject, thermosonic flip-chip technology was introduced to conduct low-temperature bonding of Ag paste and chip interconnection experiments with micro solder joints. The coating and printing method is used to realize the uniform coating of the Ag paste on the micro Cu pillars, and the thickness of the coated Ag paste can be controlled. During flip-chip bonding, different power, pressure, temperature, and bonding time will affect the shear resistance of the solder joint after bonding. Therefore, this article controls the above factors and only studies the impact of ultrasonic power and pressure on the shear force of the solder joint interface. The experiment found that before reaching the maximum shear force, as the ultrasonic power increases, the shear resistance of the solder joint also gradually increased. After that, as the ultrasonic power increased, the shear resistance of the solder joints gradually decreased. It shows that when using thermosonic flip-chip technology for chip bonding, the ultrasonic power should be maintained in an appropriate range to make the bonded flip-chip solder joints obtain a maximum shear strength. The bonding pressure is proportional to the shear strength of the solder joint.

Size effects on IMC growth of Cu/Ni/Sn-3.5Ag microbump joints during isothermal aging and prediction of shear strength using ANN

Significant downsizing trend is currently directing the advanced microelectronic packaging industry, which poses new challenges to the manufacturing process and reliability of high-density chip interconnections. In this paper, to investigate the size effect of microbump joints on the interfacial structure and bonding strength, the chip-to-chip bonding joints fabricated by microbumps of same Cu/Ni/Sn-3.5Ag construction but of various sizes were experimentally examined. After thermocompression bonding process to fabricate the chip-to-chip microbump interconnections, the intermetallic compound (IMC) growth on the Ni/Sn-3.5Ag interface during 150 °C isothermal aging was compared for joints of 100, 40 and 25 μm in diameter as well as 35, 25 and 15 μm in solder layer height, using field emission electron microscopy and electron probe microanalysis. A clear size effect on the thickness and morphology of Ni3Sn4 IMC was observed, showing thicker IMC in joints of smaller diameter and lower height. The Ni concentration distribution in the solder layer was verified to be dependent on the joint size, with possible reasons being enhanced sidewall diffusion and grain boundary diffusion through IMC grains in small-diametered joints, as well as shorter diffusion path in lower joints. The shear strength of chip-to-chip bonding vehicles was also found to be size-dependent. In addition, artificial neural network (ANN) approach was applied to establish the numerical correlation of structural factors and bonding strength. It was found that a properly constructed ANN model can successfully predict the influence of the complex combinations of geometric and interfacial factors with highly accurate output, providing an effective tool for design and optimization of microbump interconnection structures and processes.

Switching and Heat-dissipation Performance Analysis of an LTCC-based Leadless Surface Mount Package

A leadless surface mount package was developed to enhance the switching and heat-dissipation properties of a power semiconductor. The package was implemented through a low-temperature co-fired ceramic (LTCC)-based multilayer circuit substrate that could form embedded cavities. A silicon carbide (SiC) Schottky barrier diode (SBD) bare die was attached to the cavity in the LTCC substrate. Chip interconnection was realized using a wide and thick copper (Cu) clip with a low parasitic inductance and electrical resistance compared to those of a conventional wire. Silver-filled multiple vias and wide metal planes were used to reduce the electrical parasitic effects and enhance the heat-dissipation of the package. The DC and dynamic characteristics of the 600 V/10 A-class SiC SBD package involving the proposed technologies were evaluated. The dynamic test results indicated that the reverse recovery charge (Qrr) was 18.7% lower than that of a traditional TO-220 packaged product with the same bare die. Furthermore, two leadless commercial products and he proposed package prototype were applied to a power factor correction (PFC) converter, and the power loss and heat-dissipation performances were compared. The proposed package exhibited a lower loss and higher heat dissipation than those of the commercial products.

Microfluidic electroless deposition for uniform stacking chip interconnection: Simulation framework and experimental validation

Microfluidic electroless deposition interconnection is a novel approach proposed and demonstrated for stacking chip application, but the deposition uniformity is observed as the key issue for further implementation. This work investigates the deposition uniformity in microchannel for stacking chip interconnection from the perspective of electrochemistry and fluid dynamics, demonstrating that the mass transfer behavior is the underlying mechanism for the uniformity. The effects of flow velocity, flow pattern, geometry parameters and hydrogen generation on mass transfer and deposition uniformity are studied and discussed by a validated simulation framework. The numerical results indicate that high velocity oscilloscope flow with small pad pitch is the optimal design rule for high uniformity. The non-uniformity of plating rate is improved to 0.004 μm/h for oscillatory flow, and gas volume friction is reduced to 0.018 with flow velocity of 200 μm/s. This work provides theoretical and systematic investigation and insight into the evolution mechanism for the application.

A High Temperature SOI-CMOS Chipset Focusing Sensor Electronics for Operating Temperatures up to 300°C

Abstract Sensors are the key elements for capturing environmental properties and are increasingly important in the industry for the intelligent control of industrial processes. While in many everyday objects highly integrated sensor systems are already state of the art, the situation in an industrial environment is clearly different. Frequently, the use of sensor systems is impossible, because the extreme ambient conditions of industrial processes like high operating temperatures or strong mechanical load do not allow the reliable operation of sensitive electronic components. Fraunhofer is running the Lighthouse Project “eHarsh” to overcome this hurdle. In the course of the project, an integrated sensor readout electronic has been realized based on a set of three chips. A dedicated sensor fron-tend provides the analog sensor interface for resistive sensors typically arranged in a Wheatstone configuration. Furthermore, the chipset includes a 32-bit microcontroller for signal conditioning and sensor control. Finally, it comprises an interface chip including a bus transceiver and voltage regulators. The chipset has been realized in a high-temperature 0.35-micron SOI-CMOS technology focusing operating temperatures up to 300°C. The chipset is assembled on a multilayer ceramic low-temperature cofired ceramics (LTCC) board using flip chip technology. The ceramic board consists of four layers with a total thickness of approximately 0.9 mm. The internal wiring is based on silver paste while the external contacts were alternatively manufactured in silver (sintering/soldering) or in gold alloys (wire bonding). As an interconnection technology, silver sintering has been applied. It has already been shown that a significant increase in lifetime can be reached by using silver sintering for die attach applications. Using silver sintering for flip chip technology is a new and challenging approach. By adjusting the process parameter geared to the chipset design and the design of the ceramic board high-quality flip chip interconnects can be generated.

Fatigue life of solder joints in nanosilver tin paste in chip interconnect

Fatigue life of solder joints in nanosilver tin paste in chip interconnect

An Efficient Interconnection System for Neural NOC Using Fault Tolerant Routing Method

Large scale Neural Network (NN) accelerators typically have multiple processing nodes that can be implemented as a multi-core chip, and can be organized on a network of chips (noise) corresponding to neurons with heavy traffic. Portions of several NoC-based NN chip-to-chip interconnect networks are linked to further enhance overall nerve amplification capacity. Large volumes of multicast on-chip or cross-chip can further complicate the construction of a cross-link network and create a NN barrier of device capacity and resources. In this paper, this refer to inter-chip and inter-chip communication strategies known as neuron connection for NN accelerators. Interconnect for powerful fault-tolerant routing system neural NoC is implemented in this paper. This recommends crossbar arbitration placement, virtual interrupts, and path-based parallelization strategies in terms of intra-chip communications for the virtual channel routing resulting in higher NoC output at lower hardware costs. A lightweight NoC compatible chip-to-chip interconnection scheme is proposed regarding to inter-chip communication for multicast-based data traffic to enable efficient interconnection for NoC-based NN chips. Moreover, the proposed methods will be tested with four Field Programmable Gate Arrays (FPGAs) on four hard-wired deep neural network (DNN) chips. From the experimental results it can be illustrate that a high throguput can obtained effectively by the proposed interconnection network in handling thedata traffic and low DNN through advanced links.