Chip Failure Research Articles

Simulation on the Interfacial Singular Stress-strain Induced Cracking of Microelectronic Chip Under pPower On-off Cycles

Thermal fatigue failure of a microelectronic chip usually initiates from the interface between solder joint and substrate for the mismatch in coefficient of thermal expansion (CTE). Because of the viscoelastic creep properties of the solder, the interfacial stress-strain are, strongly, temperature and time dependent. Based on the established constitutive models of solder materials, the three-dimensional FEM analysis of the microelectronic chip undergoing power on-off thermal cycles is carried out. The time dependent stress-strain singular fields at the solder/substance interface are obtained, and the singular field parameters are quantitatively evaluated. Furthermore, the crack nucleation behavior of thermal fatigue failure are tested to verify the conclusion that singular stress-strain promote thermal fatigue failure from the solder/substance interface.

Gate–Emitter Pre-threshold Voltage as a Health-Sensitive Parameter for IGBT Chip Failure Monitoring in High-Voltage Multichip IGBT Power Modules

This paper proposes a novel health-sensitive parameter, called the gate-emitter pre-threshold voltage VGE(pre-th), for detecting IGBT chip failures in multichip IGBT power modules. The proposed method has been applied in an IGBT gate driver and measures the VGE at a fixed time instant of the VGE transient before the threshold voltage occurs. To validate the proposed method, theoretical analysis and practical results for a 16-chip IGBT power module are presented in the paper. The results show a 500 mV average shift in the measured VGE(pre-th) for each IGBT chip failure.

Development of Neural Network Model to Predict Flank Wear and Chipping Failure

Most of the researchers have developed Artificial Neural Network (ANN) models to forecast the cutting tool life based on whether it has either a flank wear or a crater wear or a nose wear. In this paper, an attempt has been made to classify the cutting tool wear based on whether it has flank wear, chipped-off cutting edge or a combination of both failures. To obtain the experimental results, both the failures namely flank wear and chipped-off cutting edge have been produced using Electric Discharge Machining (EDM) process. Experiments were carried out using cemented carbide-coated inserts on EN-8 steel and all the responses were acquired by using virtual instruments. The acquired data were analyzed to develop the ANN models to forecast the condition of cutting tool. Vibration and strain data were recorded using accelerometer and strain gauge half-bridge circuit.

Research on Breakthrough Failure of IGBT Chip

In large-capacity power electronic devices, fully controlled power electronic devices, such as insulated gate bipolar transistors ( IGBT ), which are widely used at present, are the core components to realize high-performance power conversion and control. With the increasingly wide application of IGB, its voltage, current level and working junction temperature are getting higher and higher, and its working environment is also getting worse, putting more and more stringent requirements on reliability, and the reliability of power electronic devices has also become the most important factor determining the safe operation of the whole device. Therefore, finding out the internal mechanism of IGBT failure is an important guarantee for improving the reliability of device operation and realizing optimal design and application. The research that has been carried out mainly focuses on various external factors that cause failure, namely various failure modes of IGBT, and lacks in-depth research on the internal mechanism of final failure. On the basis of in-depth analysis of IGBT’s structure and working principle, this paper analyzes the internal mechanism of IGBT’s breakdown failure with semiconductor physics theory, finds out the fundamental principle of causing failure, and designs experiments to reproduce the occurrence of failure, thus further verifying the conclusion reached in the analysis.

CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication

ABSTRACT We have been witnessing the continuous size reduction in consumer electronics devices with longer battery life. The Application Specific Integrated Circuits allow for integration of multiple electronics devices on the same dice. At the same time optimizing the transistor and device area lowers power consumption. It is a big challenge to develop such semiconductor processes and also to develop methodologies to monitor the process during semiconductor fabrication. After every major fabrication process, the wafer undergoes an inspection to detect any abnormality that may cause chip failure down the line. An optical inspection using Ultra Violet or Deep Ultra Violet light is designed to find the physical defects that might be “visible” on the wafer. In order to find electrical connection failure during fabrication, a separate approach of electron beam inspection is designed for monitoring metallization processes. In this study, we have used Computer Aided Design layout analysis to guide the defect inspection for both optical and electron beam wafer inspections. The goal was to increase the chances of finding critical defects as well as to reduce the cycle time for the inspection and defect characterization. The proposed approach has been compared with the existing baseline inspection results on the same wafer.

Experimental study on energy dissipation characteristics of adiabatic shear evolution in high-speed machining of U75V steel

As one of the main characteristics in high-speed machining process, the adiabatic shear evolution induced energy dissipation influences the development of serrated chip and tool failure, which was further investigated experimentally in this work. Through the high-speed machining experiment of U75V rail steel by applying the cemented carbide insert, the development of chip morphology accompanying with the adiabatic shear evolution and tool failure with the cutting speed increasing were investigated microscopically. Based on the adiabatic shear saturation limit analysis, the energy dissipation theory was further proposed to evaluate the energy dissipation accumulation and energy dissipation rate of adiabatic shear evolution. The influences of energy dissipation characteristics related to physical and mechanical properties on the tool failure were revealed and discussed. It was concluded from the analysis of experimental results that the energy dissipation of adiabatic shear evolution from adiabatic shear banding to fracture, resulting in the thermal and mechanical coupling, mainly influenced the mechanisms of tool failure on the rake face. The occurrence of adiabatic shear fracture weakened the friction effect on the rake face. The energy dissipation theory of adiabatic shear evolution reasonably assessed the tool failure characteristics in high-speed machining process.

Digital Microfluidic Biochips Online Fault Detection Route Optimization Scheme

Digital microfluidic biochips(DMFBs) have been widely used in biology, medicine and chemical experiments. These areas all have high requirements on the reliability of experimental results. Therefore, it is necessary to conduct chip failure detection during the experiment. In this work, based on Employed particle swarm optimization algorithm, the fault detection route optimization of direct-addressing and pin-constrained digital microfluidic chips are respectively studied. Combining the employed search operator of Artificial Bee Colony algorithm and Particle Swarm Optimization, the method can improve the searching accuracy of the algorithm while exploiting the ability of algorithm exploration. The simulation experiment is carried out by using the multi-element biochemical test chip model. The results show that the proposed method can shorten the fault detection path and improve the fault detection efficiency.

Performance of Si3N4/(W, Ti)C graded ceramic tool in high-speed turning iron-based superalloys

A Si3N4/(W, Ti)C graded nano-composite ceramic tool was fabricated and its performance in high speed turning iron-based alloys GH2132 was investigated compared with homogeneous and commercial ceramic tools. The chip morphology, cutting forces, cutting temperature, tool life and failure mechanisms and machined surface roughness were recorded and analyzed. The results showed that with the increasing cutting speed the resultant cutting force shows a tendency to first increase and then decrease while the cutting temperature increases gradually. Straight continuous chips, bending continuous chips, twist continuous chips and snarled chips form in turn. Saw-tooth chips tend to form when the cutting speed is more than 200 m/min. The graded tool shows longer tool life especially at the cutting speed of 150 and 200 m/min compared with the homogenous and commercial ceramic tools. Tool failure modes mainly include grooving on the rake face, notching on the flank face, abrasion and adhesion. The grooving on the rake face tends to decrease while notching on the flank face tends to increase as cutting speed increases. Surface roughness of the machined iron-based super-alloys is relatively high due to the serious adhesion. Better surface roughness can be got using the graded tool.

A real-time tool failure monitoring system based on cutting force analysis

This paper developed a novel, simple-to-use method for detecting tool failure in cutting. An EEMD filtering and restructuring method is launched according to entropy and correlation of cutting force signal in turning high-strength and high-hardness materials using carbide cutting tools. Then, friction coefficient and mean power theories are adopted to characterize tool failure status using restructured cutting force signal. Finally, an automatic detector is proposed using CUSUM control chart to monitor tool chipping and tool wear failure in real time based on previous analysis and can be verified by semi-finishing experiment. Without any need of other sensor equipment and long computing time, the method can be reliable and simple to operate in detecting tool failure in real time.

Ultrafast-laser dicing of thin silicon wafers: strategies to improve front- and backside breaking strength

Thin 50-µm silicon wafers are used to improve heat dissipation of chips with high power densities. However, mechanical dicing methods cause chipping at the edges of the separated dies that reduce the mechanical stability. Thermal load changes may then lead to sudden chip failure. Recent investigations showed that the mechanical stability of the cut chips could be increased using ultrashort-pulsed lasers, but only at the laser entrance (front) side and not at the exit (back) side. The goal of this study was to find strategies to improve both front- and backside breaking strength of chips that were cut out of an 8″ wafer with power metallization using an ultrafast laser. In a first experiment, chips were cut by scanning the laser beam in single lines across the wafer using varying fluencies and scan speeds. Three-point bending tests of the cut chips were performed to measure front and backside breaking strengths. The results showed that the breaking strength of both sides increased with decreasing accumulated fluence per scan. Maximum breaking strengths of about 1100 MPa were achieved at the front side, but only below 600 MPa were measured for the backside. A second experiment was carried out to optimize the backside breaking strength. Here, parallel line scans to increase the distance between separated dies and step cuts to minimize the effect of decreasing fluence during scribing were performed. Bending tests revealed that breaking strengths of about 1100 MPa could be achieved also on the backside using the step cut. A reason for the superior performance could be found by calculating the fluence absorbed by the sidewalls. The calculations suggested that an optimal fluence level to minimize thermal side effects and periodic surface structures was achieved due to the step cut. Remarkably, the best breaking strengths values achieved in this study were even higher than the values obtained on state of the art ns-laser and mechanical dicing machines. This is the first study to the knowledge of the authors, which demonstrates that ultrafast-laser dicing improves the mechanical stability of thin silicon chips.

LAXY: A Location-Based Aging-Resilient Xy-Yx Routing Algorithm for Network on Chip

Network on chip (NoC) is a scalable interconnection architecture for ever increasing communication demand between processing cores. However, in nanoscale technology size, NoC lifetime is limited due to aging processes of negative bias temperature instability, hot carrier injection, and electromigration. Usually, because of unbalanced utilization of NoC resources, some parts of the network experience more thermal stress and duty cycle in comparison with other parts, which may accelerate chip failure. To slow down the aging rate of NoC, this paper proposes an oblivious routing algorithm called location-based aging-resilient Xy-Yx (LAXY) to distribute packet flow over entire network. LAXY is based on the fact that dimension-ordered routing algorithms imposes the highest traffic load on the central nodes in mesh topologies. To balance the traffic over the network, certain routers at the east and the west of NoC, with dimension-order XY routing, statically are configured as YX. Various configurations have been explored for LAXY and the simulations show a specific configuration, called Fishtail , increases mean time to failure of the routers and interconnects by about 42% and 56%, respectively. Moreover, by balancing the load over the network, LAXY improves overall packet latency by about 7% in average, with negligible area overhead.

A Fast Method for Lifetime Estimation of Blue Light-Emitting Diode Chips Based on Nonradiative Recombination Defects

This paper proposes a new method for estimating the lifetime of the InGaN/GaN-based light-emitting diode (LED) chip by analysing the density of nonradiative recombination defects. The nonradiative recombination defect is a major factor affecting the performance of LED chips, and the increase in defects eventually leads to the chip failure. Therefore, the growth rate of defects determines the lifetime of the LED chip. A new measurement method of the defect density is introduced. A batch of 1-W blue LED chips is selected to conduct 6000-h accelerated life tests with constant current stresses. And through studying the data of defect densities and light output, it is concluded that compared with light output, the defect density is more sensitive to the current stress, which indicates that the defect density is more advantageous to reflect the performance degradation of the LED chip. In particular, the growth of defects induced by aging stress is found to follow a logarithmic law, then a mathematical model of the defect growth is introduced. And with the model we can obtain the key parameters about the growth rate of defects. Furthermore, we establish the quantitative relationship between the growth rate of defects and aging lifetime. Based on this relationship, the lifetime of the LED chip can be predicted in a more accurate and faster way. The result shows that under the stress condition of our experiments, this new method requires less than 1000-h stress time, and the traditional method requires more than 6000 h.

Reliability and failure analysis of solder joints in flip chip LEDs via thermal impedance characterisation

Flip chip technology has made significant improvements to LED chip on board (COB) packages and modules by reducing thermal resistance compared with traditional wire bonded LEDs. However, one of the critical issues of flip chip packaged LEDs is the reliability of their solder interconnects, which are responsible for the heat transfer to the substrate. Based on a supply switching test, also called power cycle test, a model for monitoring and reliability was done to describe the remaining lifetime and additional the solder fatigue. Therefore, changes in thermal resistance of the LED-module were measured and correlated with solder fatigue of the LED flip chip package. Thermal impedance measurements were performed to monitor the status of the LED-module. Detailed analyses, comparing with the initial state, allow the evaluation of the occurring temperature swing of each LED chip. Single chip analysis combined with a thermal resistance driven monitoring model allows the calculation of remaining lifetime at each time during testing and beyond the first chip failure in a multi chip LED-module. Accordingly, it could be shown that the thermal impedance is a powerful tool for reliability monitoring and failure analysis.

Mitigation of Hardware Trojan based Denial-of-Service attack for secure NoCs

As Multiprocessor System-on-Chips (MPSoCs) continue to scale, security for Network-on-Chips (NoCs) is a growing concern as rogue agents threaten to infringe on the hardware’s trust and maliciously implant Hardware Trojans (HTs) to undermine their reliability. The trustworthiness of MPSoCs will rely on our ability to detect Denial-of-Service (DoS) threats posed by the HTs and mitigate HTs in a compromised NoC to permit graceful network degradation. In this paper, we propose a new light-weight target-activated sequential payload (TASP) HT model that performs packet inspection and injects faults to create a new type of DoS attack. Faults injected are used to trigger a response from error correction code (ECC) schemes and cause repeated retransmission to starve network resources and create deadlocks capable of rendering single-application to full chip failures. To circumvent the threat of HTs, we propose a heuristic threat detection model to classify faults and discover HTs within compromised links. To prevent further disruption, we propose several switch-to-switch link obfuscation methods to avoid triggering of HTs in an effort to continue using links instead of rerouting packets with minimal overhead (1–3 cycles). To sustain data integrity over a compromised link, we propose an optimized implementation of algebraic manipulation detection (AMD) codes to detect any fault injection in targeted flits. Our proposed modifications complement existing fault detection and obfuscation methods and only add 2% in area overhead and 6% in excess power consumption in the NoC micro-architecture.

Edge chipping mechanism and failure time prediction on carbide cemented tool during drilling of CFRP/Ti stack

To investigate the edge chipping during drilling of the CFRP/Ti stack with carbide cemented tools, a drilling experiment was carried out and a tool failure model was proposed. Thrust force, drilling temperature, and tool wear were analyzed. A tool stressing model and a tool failure model of edge chipping were constructed respectively. On the basis of these, the prediction model on the edge chipping was established to forecast the failure time. Drilling temperature, Vickers hardness, and cutting speed were considered during the prediction model building. The results demonstrate that adhesive wear has a great influence on the edge chipping. The damage of adhesive wear for tool rake face leads to the load variation on rake face and the initial crack. Under the action of shear stress, the crack starts at rake face and then expands to the flank face, resulting in tool edge chipping. The affinity interaction (between titanium alloy with carbide cemented) and the thermal residual stress are two critical factors for tool edge chipping. Tear easily occurs inside the binding phase or at the boundary between hard phase and binder phase. As the drilling temperature increases, the hardness of the carbide cemented will gradually decrease. The prediction result of failure time is similar to the experimental result, and the effectiveness of the prediction model is verified.

Stress Reduction of Solar Cell with Nanostructures on Silicon Chip Surface

Silicon chip has been widely used in solar cell recently. The thinning of silicon chip, easily inducing surface defects, becomes necessary to produce solar cells more efficiently. The surface defects resulting in stress concentration on the silicon chip surface would be the source of chip failure. In this study, the finite element analysis was used to investigate the stress distribution near the surface crack of a solar cell on which the nanostructures were introduced to alleviate the induced stress. For the solar cell model, positive silver and negative aluminum electrodes were added on the top and bottom sides of silicon chip. The solar cell under four-point bending was simulated in analysis with and without nanostructures. The results show that the stresses reduce more than 50 % for the solar cell model with nanostructures. When the crack depth is deeper enough, the stress at crack tip is higher than that at junction near the electrode and the crack leads to the failure of solar cell. The effect of different section length of nanostructures on the stress distribution caused by the surface crack was also discussed.

Ultrashort pulse laser dicing of thin Si wafers: the influence of laser-induced periodic surface structures on the backside breaking strength

High power electronic chips are usually fabricated on about 50 µm thin Si wafers to improve heat dissipation. At these chip thicknesses mechanical dicing becomes challenging. Chippings may occur at the cutting edges, which reduce the mechanical stability of the die. Thermal load changes could then lead to sudden chip failure. Ultrashort pulsed lasers are a promising tool to improve the cutting quality, because thermal side effects can be reduced to a minimum. However, laser-induced periodic surface structures occur at the sidewalls and at the trench bottom during scribing. The goal of this study was to investigate the influence of these periodic structures on the backside breaking strength of the die. An ultrafast laser with a pulse duration of 380 fs and a wavelength of 1040 nm was used to cut a wafer into single chips. The pulse energy and the number of scans was varied. The cuts in the wafer were investigated using transmitted light microscopy, the sidewalls of the cut chips were investigated using scanning electron and confocal microscopy, and the breaking strength was evaluated using the 3-point bending test. The results indicated that periodic holes with a distance of about 20–30 µm were formed at the bottom of the trench, if the number of scans was set too low to completely cut the wafer; the wafer was only perforated. Mechanical breaking of the bridges caused 5 µm deep kerfs in the sidewall. These kerfs reduced the breaking strength at the backside of the chip to about 300 MPa. As the number of scans was increased, the bridges were ablated and the wafer was cut completely. Periodic structures were observed on the sidewall; the roughness was below 1 µm. The surface roughness remained on a constant level even when the number of scans was doubled. However, the periodic structures on the sidewall seemed to vanish and the probability to remove local flaws increases with the number of scans. As a consequence, the breaking strength was increased to about 700 MPa.

Information for Contributors

Solid-state lightings (SSL) rapidly penetrate the global illumination market because of the energy efficiency and the reliability. The energy efficiency can be easily evaluated but the reliability is not convenient to be estimated. Among several reliability issues, a LED chip level's reliability could be a difficult problem because chip failures related to electromigration phenomenon are hard to be detected in the early stages. In order to remove potential leakage LEDs in modules, additional screening method is necessary to be performed occasionally. In this study, chip package interaction (CPI) for LED packages was investigated in order to estimate stresses of the LED chip in the module level. This methodology would help LED manufacturers to perform a robust design of LED packages in terms of the LED chip reliability. The electromigration is related to metal diffusion, which belongs to a creep phenomenon. As the creep strain is a function of temperature, stress and time, quantifying stresses in the metal layers of the LED die can be useful information for LED manufacturers to make an engineering decision in the early stages of manufacturing.

Chip package interaction for LED packages

Solid-state lightings (SSL) rapidly penetrate the global illumination market because of the energy efficiency and the reliability. The energy efficiency can be easily evaluated but the reliability is not convenient to be estimated. Among several reliability issues, a LED chip level's reliability could be a difficult problem because chip failures related to electromigration phenomenon are hard to be detected in the early stages. In order to remove potential leakage LEDs in modules, additional screening method is necessary to be performed occasionally. In this study, chip package interaction (CPI) for LED packages was investigated in order to estimate stresses of the LED chip in the module level. This methodology would help LED manufacturers to perform a robust design of LED packages in terms of the LED chip reliability. The electromigration is related to metal diffusion, which belongs to a creep phenomenon. As the creep strain is a function of temperature, stress and time, quantifying stresses in the metal layers of the LED die can be useful information for LED manufacturers to make an engineering decision in the early stages of manufacturing.

Quantum-mechanical modeling of chip deformation and failure

An atomic approach to chip deformation and failure in cutting is outlined. The relation of the shear strength and the type of chip to the energy characteristics of the crystal lattice, its packing-defect energy, and the latent heat of fusion is established. The constancy of the shear with variation in the cutting conditions is related to the limiting dislocation density and the formation of an amorphous–liquid state.