Chip Backside Research Articles

Silicon Micromachined TSVs for Backside Interconnection of Ultra-Small Pressure Sensors.

This paper presents an ultra-small absolute pressure sensor with a silicon-micromachined TSV backside interconnection for high-performance, high spatial resolution contact pressure sensing, including flexible-substrate applications. By exploiting silicon-micromachined TSVs that are compatibly fabricated with the pressure sensor, the sensing signals are emitted from the chip backside, thereby eliminating the fragile leads on the front-side. Such a design achieves a flat and fully passivated top surface to protect the sensor from mechanical damage, for reliable direct-contact pressure sensing. A single-crystal silicon beam-island structure is designed to reduce the deflection of the pressure-sensing diaphragm and improve output linearity. Using our group-developed microholes interetch and sealing (MIS) micromachining technique, we fabricated ultra-small piezoresistive pressure sensors with the chip size as small as 0.4 mm × 0.6 mm, in which the polysilicon-micromachined TSVs transfer the signal interconnection from the front-side to the backside of the wafer, and the sensor chips can be densely packaged on the flexible substrate via the TSVs. The ultra-small pressure sensor has high sensitivity of 0.84 mV/kPa under 3.3 V of supply voltage and low nonlinearity of ±0.09% full scale (FS) in the measurement range of 120 kPa. The proposed pressure sensors with backside-interconnection TSVs hold promise for tactile sensing applications, including flexible sensing of wearable wristwatches.

Researches and Applications of Nanostructured 2D Materials growth By Continuous Wavelength Laser Process

Two-dimensional (2D) nanomaterials, such as graphene and hexagonal boron nitride (hBN), have recently attracted increasing attention of researchers due to their unique phonon and electronic structures. These nanomaterials have been widely used in applications, such as sensors, catalysts, and optoelectronic devices, due to the lack of interlayer bonds and the quantum confinement of electrons. There have been several well studied methods to synthesis 2D materials including chemical vapor deposition(CVD), physical vapor deposition(PVD), liquid exfoliation, Li-intercalation exfoliation,wet chemistry,ultrasonic-ball milling, Among them, CVD is the most famous method to fabricate electronic device with high quality materials characteristic. However, CVD processes will cause extremely harsh heat budget to substrate during high temperature process. Recently, researchers have established transfer method fabricating device on other undamaged substrate. It is the trickiest problem make it cannot apply to industry.In this research, we built an indirect laser projection transfer method. First, we sputter requiring material on Si wafer as donor chip. Followed, placed the donor chip upside down on acceptor substrate, and radiated by laser on the donor chip backside. The deposited component on donor substrate would evaporate, and the vapor would fill between two substrates interspacing. Then, the vapor will recrystallize on the cooler acceptor surface. We have successfully transferred low melting temperature 2D materials such as SnSex, NiSex, SbSex on different acceptor substrate, even on flexible and flammable paper. By controlling laser intensity and irradiation time, we can control the amount of Se scattering, finally manipulate SnSe/SnSe2 phase ratio successfully. The mechanism has been demonstrated by SEM, RAMAN, TEM, XPS, XRD. Owing to indirection irradation, it can transfer materials on several fragile substrates without any heat budget, which reveals the great potential of this method for electronics applications. In this report we successfully demonstrate transferred SnSe/SnSe2 have good feasibility in energy storage system and sensor device.

CONCEALING-Gate: Optical Contactless Probing Resilient Design

Optical probing, though developed as silicon debugging tools from the chip backside, has shown its capability of extracting secret data, such as cryptographic keys and user identifications, from modern system-on-chip devices. Existing optical probing countermeasures are based on detecting any device modification attempt or abrupt change in operating conditions during asset extraction. These countermeasures usually require additional fabrication steps and cause area and power overheads. In this article, we propose a novel low-overhead design methodology to prevent optical probing. It leverages additional operational logic gates, termed as “CONCEALING-Gates,” inserted as neighbor gates of the logic gates connected to the nets carrying asset signals. The switching activity of the asset carrying logic is camouflaged with the switching activity of the concealing-gate. The input signal and placement in the layout of the concealing-gates must be selected in such a way that they remain equally effective in preventing different variants of optical probing, i.e., electro-optical frequency mapping and Electro-optical probing. The methodology is suitable for the existing ASIC/FPGA design flow and fabrication process, since designing new standard logic cells is not required. We have performed a comprehensive security evaluation of the concealing-gates using a security metric developed based on the parameters that are crucial for optical probing. The attack resiliency of the logic cells, protected by concealing-gates, is evaluated using an empirical study-based simulation methodology and experimental validation. Our analysis has shown that in the presence of concealing-gates, logic cells achieve high resiliency against optical contactless probing techniques.

Dynamic optical beam induced current variation mapping: A fault isolation technique

In this paper, we describe the concept and applications of a dynamic laser stimulation technique based on optical beam-induced current (OBIC) variation mapping for global fault localization. A production tester exercised the chip dynamically while a 1064 nm wavelength laser interrogates the devices in the region of interest from the chip backside. OBIC variations at different test cycles are recorded for every scanned pixel and translated into a current profile. A post-processing scheme then determines the suspected defect location. Unlike laser-assisted device-alteration (LADA) which uses the same laser, this technique applies to hard defects localization. Five case studies will be presented as proof of concept.

SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory

The storage industry is moving toward emerging non-volatile memories (NVMs), including the spin-transfer torque magnetoresistive random-access memory (STT-MRAM) and the phase-change memory (PCM), owing to their high density and low-power operation. In this paper, we demonstrate, for the first time, circuit models and performance benchmarking for the domain wall (DW) reversal-based magnetoelectric-antiferromagnetic random access memory (ME-AFMRAM) at cell-level and at array-level. We also provide perspectives for coherent rotation-based memory switching with topological insulator-driven anomalous Hall read-out. In the coherent rotation regime, the ultra-low power magnetoelectric switching coupled with the terahertz-range antiferromagnetic dynamics result in substantially lower energy-per-bit and latency metrics for the ME-AFMRAM compared to other NVMs including STTMRAM and PCM. After characterizing the novel ME-AFMRAM, we leverage its unique properties to build a dense, on-chip, secure NVM platform, called SMART: A Secure Magnetoelectric Antiferromagnet- Based Tamper-Proof Non-Volatile Memory. New NVM technologies open up challenges and opportunities from a data-security perspective. For example, their sensitivity to magnetic fields and temperature fluctuations, and their data remanence after power-down make NVMs vulnerable to data theft and tampering attacks. The proposed SMART memory is not only resilient against data confidentiality attacks seeking to leak sensitive information but also ensures data integrity and prevents Denial-of-Service (DoS) attacks on the memory. It is impervious to particular power side-channel (PSC) attacks which exploit asymmetric read/write signatures for 0 and 1 logic levels, and photonic side-channel attacks which monitor photo-emission signatures from the chip backside.

Fiber grating couplers for optical access via the chip backside

For the majority of packaging schemes in silicon photonics, out-of-plane optical access to the waveguide layer is achieved via the chip frontside, away from the substrate. As such, fiber grating couplers have generally been optimized with this in mind. In this article, we present two strategies for designing a fiber grating coupler for coupling to optical fibers placed on the backside of the chip, without the need of superposed reflective layers. An all silicon O-band grating coupler is designed, fabricated, and measured with a peak coupling efficiency to a single mode fiber placed on the backside of the chip of −2.8 dB and a −1 dB bandwidth of ∼40 nm. In a second approach, a hybrid silicon nitride/silicon O-band grating coupler is measured in the same configuration with a peak coupling efficiency of −3.2 dB and a −1 dB bandwidth of ∼60 nm.

Study of Miniaturization of a Silicon Vapor Chamber for Compact 3D Microelectronics, via a Hybrid Analytical and Finite Element Method

The interest in silicon vapor chambers (SVCs) has increased in the recent years as they have been identified as efficient cooling systems for microelectronics. They present the advantage of higher thermal conductivity and smaller form factor compared to conventional heat spreaders. This work aims to investigate the potential miniaturization of these devices, preliminary to integration on the backside of mobile device chips, located as close as possible to hotspots. While detailed numerical models of vapor chamber operation are developed, an easy modeling with low computational cost is needed for an effective parametric study. Based on the study of the operating limits, this paper shows the thinning potential of a water filled micropillar for a device operating below 10 W and identify the corresponding vapour core height, and wick thickness.

Study of Miniaturization of a Silicon Vapor Chamber for Compact 3D Microelectronics, via a Hybrid Analytical and Finite Element Method

The interest in silicon vapor chambers (SVCs) has increased in the recent years as they have been identified as efficient cooling systems for microelectronics. They present the advantage of higher thermal conductivity and smaller form factor compared to conventional heat spreaders. This work aims to investigate the potential miniaturization of these devices, preliminary to integration on the backside of mobile device chips, located as close as possible to hotspots. While detailed numerical models of vapor chamber operation are developed, an easy modeling with low computational cost is needed for an effective parametric study. Based on the study of the operating limits, this paper shows the thinning potential of a water filled micropillar for a device operating below 10 W and identify the corresponding vapour core height, and wick thickness.

Experimental and numerical investigation of direct liquid jet impinging cooling using 3D printed manifolds on lidded and lidless packages for 2.5D integrated systems

Package level bare die jet impingement cooling on the chip backside has been previously demonstrated as a highly efficient jet cooling solution for high power devices, by eliminating the thermal interface material. However, bare die jet impingement cooling is a disruptive cooling technology requiring direct access to the backside of the semiconductor device. A less disruptive cooling implementation in which the impingement cooling is applied on the lid is now investigated as an intermediate step. In this work, the first comparison of the cooling performance with the liquid micro-jet array impingement cooling on lidded and bare die package is conducted and experimentally characterized for polymer coolers fabricated by additive manufacturing. The thermal characterization is performed on a 2.5D integrated system that contains two advanced thermal test dies. In addition, besides the reference cooler with vertical coolant supply channel, an improved design of 3D printed fluid delivery manifold with lateral inlet/outlet channels is introduced and benchmarked. The experimental and numerical comparison show that the cooler with the lateral feeding manifold requires 60% less pumping power with respect to the vertical feeding manifold for the same high thermal performance while reducing the overall thickness of the cooling solution by a factor of 2.

Prospects for automotive SiP modules applying IC assembly and packaging technology

Abstract We develop a package that ensures quality complying with AEC-Q 100 Grade 2 which is in-vehicle quality from various flip chip mounting methods and bump sealing technology with underfill resin and mold resin. FC CSP with heat spreader mounted on the product which has started mass production since last year is in the lineup, The heat dissipation can be improved by attaching the heat spreader directly to the chip backside which are heat sources and the Thermal Interface Material (TIM), using our assembly technology of flip chip mounting and molding the periphery while exposing the chip backside. By adjusting the Coefficient of Thermal Expansion (CTE) and thickness of the material, we realize low warpage and low coplanarity at reflow temperature and product use temperature environment and reduce package displacement behavior, we will improve the secondary mountability to the motherboard and provide reliable packages. Furthermore, it can be applied to SiP modules. It is also possible to construct multiple chip modules by mounting multiple ICs or placing low-passive components around them. We will consider heat spreader mounting on multiple ICs that generate heat, and metal coating on the entire SiP module to have a structure that achieves both heat dissipation and electromagnetic shielding as a future idea.

On the diffusion wear of cemented carbides in the turning of AISI 316L stainless steel

The present work has studied the wear and wear mechanisms of three different but comparable cemented carbide grades during orthogonal turning of AISI 316L. The influences of WC grain size and cutting speed on the resulting crater and flank wear have been evaluated by optical surface profilometry and scanning electron microscopy (SEM). The mechanisms behind the crater and flank wear have been characterized on the submicrometer scale using high resolution SEM, energy dispersive X-ray spectroscopy (EDS), Auger electron spectroscopy (AES) and time of flight secondary ion mass spectrometry (ToF-SIMS) of the worn cutting inserts and the produced chips. In addition to a dependence on cutting speeds, wear rates were also found to be dependent on the WC grain size. High resolution SEM, AES and ToF-SIMS analysis of the worn cemented carbide within the crater and flank wear regions revealed that the degradation of cemented carbide at higher cutting speeds is mainly controlled by diffusion wear of the WC-phase. This is supported by ToF-SIMS analysis of the back-side of stainless steel chips which reveals the presence of a 10 nm thin W-containing oxide film. The results are discussed and interpreted in the light of the conditions prevailing at the tool-chip interface.

Design, Fabrication, and Testing of a Monolithically Integrated Tri-Axis High-Shock Accelerometer in Single (111)-Silicon Wafer.

In this paper, a monolithic tri-axis piezoresistive high-shock accelerometer has been proposed that has been single-sided fabricated in a single (111)-silicon wafer. A single-cantilever structure and two dual-cantilever structures are designed and micromachined in one (111)-silicon chip to detect Z-axis and X-/Y-axis high-shock accelerations, respectively. Unlike the previous tri-axis sensors where the X-/Y-axis structure was different from the Z-axis one, the herein used similar cantilever sensing structures for tri-axis sensing facilitates design of uniform performance among the three elements for different sensing axes and simplifies micro-fabrication for the multi-axis sensing structure. Attributed to the tri-axis sensors formed by using the single-wafer single-sided fabrication process, the sensor is mechanically robust enough to endure the harsh high-g shocking environment and can be compatibly batch-fabricated in standard semiconductor foundries. After the single-sided process to form the sensor, the untouched chip backside facilitates simple and reliable die-bond packaging. The high-shock testing results of the fabricated sensor show linear sensing outputs along X-/Y-axis and Z-axis, with the sensitivities (under DC 5 V supply) as about 0.80–0.88 μV/g and 1.36 μV/g, respectively. Being advantageous in single-chip compact integration of the tri-axis accelerometers, the proposed monolithic tri-axis sensors are promising to be embedded into detection micro-systems for high-shock measurement applications.

Investigation of micro-textured cutting tools used for face turning of alloy 718 with high-pressure cooling

There is an increasing demand to improve the service life of cutting tools during machining of heat resistant superalloys (HRSA). Various studies showed that textured cutting tools improved the tribological properties and reduced cutting forces, temperature, and tool wear. Surface texturing can be seen as a futuristic design to improve the performance of the cutting tool and to increase productivity. However, only limited research has been conducted in machining superalloys with textured inserts and high-pressure coolant. In this work, three different micro texture designs on both rake and flank face are investigated in combination with high-pressure coolant in machining Alloy 718. Due to better tool life predictability, carbide cutting tools are used in machining components made from superalloys. However, the disadvantage is that machining can only be done at lower cutting speed/feed rate/depth of cut with high tool wear rates. The experimental investigation using different tool wear analysis methods showed that the combination of a cylindrical dimple on the rake and the square pyramid texture on the flank surface improved the wear resistance of the tool. An increase in tool life of about 30% was achieved as compared with a regular insert for the investigated cutting conditions. Different levels of adhering workpiece material were observed on the rake face of textured tools. Furthermore, the chip backside showed imprints from the tool textures. The tool textures on the rake face have influenced the tool-chip friction conditions during cutting.

Assessment of a Chip Backside Protection

Security-sensitive integrated circuits (ICs) are equipped with various hardware and software countermeasures which make them more secure. However, the chip backside is still exposed, and a proper countermeasure which is able to protect the ICs against physical and optical attacks through the silicon backside is required. This work presents the development, realization, and evaluation of a countermeasure concept for the IC backside against attack through the silicon backside, which is opaque to infrared light. This protection concept is able to detect any physical tampering on the IC backside. The IC backside, which is protected with an optically active layer and IC electronics, is used to create a signal to indicate a violation of the back surface. The advantages and drawbacks of the method are discussed. An assessment of the attacks through the chip backside, available countermeasures against them, and the properties of a proper protection structure are included.

IC security and quality improvement by protection of chip backside against hardware attacks

In this work, a protection structure for the silicon chip backside will be presented, which is a protective TiO2-Ti-TiO2 layer stack with an angular dependent reflectivity. It uses a selected p-n junction as the light emitter and other junctions as photodetectors of the light reflected in various angles inside the silicon. The measurement of this structure highlights strong angle-dependent reflectivity for the light reflected off the backside of the chip. Detecting these photocurrents indicates whether the IC backside is subject to a hardware attack that violates the backside layer integrity, like FIB, or preparative damage of the layer. Creating a pattern of photocurrent ratios when the IC is running can signal the IC whether such physical attacks from the backside have occurred. For this protection concept, there is no need to add additional masks or circuitry of the IC, since it could use the drain or source junctions of transistors already available.

Advanced through silicon vias for hybrid pixel detector modules

The through-silicon via (TSV) technology offers high-density vertical stacking of integrated circuits, providing a smaller and simpler structure, whilst increasing connectivity and performance. In High-Energy Physics (HEP) experiments, via-last TSVs are exploited to build low material modules for the upgrades of pixel detectors at the High Luminosity LHC (HL-LHC). In order to prove this concept a versatile via-last TSV process is being developed using ATLAS FE-I4 pixel read-out wafers. It allows modules being operated from the chip backside using the TSV-enabled connectivity. The current status of this development is discussed and results of the TSV formation process and the fabrication of the redistribution layer (RDL) on the ATLAS FE-I4 wafers are shown together with electrical results of the first read-out chips while operated via TSVs and RDLs. Another emphasis of this R&D is the industrial benefit, especially for small and medium companies, which will have access to more affordable and, therefore, competitive option.

IC Debug and Fault Isolation for an Age of IoE and High Data Rates—A Vision

The electronics industry faces an explosion of data collection, exchange and storage for the Internet of Everything, cloud computing, and many more applications. A dramatic performance gain of circuits and systems will be required, including a drastic increase of operating frequency, combined with very low power and low latency—all this at no cost increase. Although the International Technology Roadmap for Semiconductors, representing the progress of Moore’s law, edited their final report in 2016, it can easily be predicted that electronic systems and packages will undergo enormous miniaturization and new interconnect concepts involving new materials and solutions, called “heterogeneous integration.” First silicon debug and diagnosis and failure analysis (FA) rely on internal signal tracking using contactless fault isolation (CFI). CFI is performed from the chip backside utilizing near-infrared optical probe that interacts with the logical signal. This paper assesses CFI readiness for the expected evolution on chip level and system/package level. Challenges and new opportunities will be discussed that CFI encounters with 3-D integration and photonic interconnects. Together with innovations in test, reliability, and security, a vision and several options are presented. They indicate how challenges to CFI may be mastered by new concepts of debug and FA, when they are part of the design concept of the electronic systems from early on.

An Optical Inspection System Development for Defects on Multi-surfaces of Chips

We proposed a new architecture with multiple pick and place heads to suck inspected chips and to be moved synchronously for acquiring the images of different surfaces on different chips at their corresponding acquisition stations. The computation loading of defect inspection for each chip also can be distributed because of sequential image acquisition. Considering the different computing loading of 6 surfaces of a chip, image acquisition for the front and back sides of chips is allocated at the first and second stations, and then 4 edge sides of chips. The modification and calibration of position and orientation for each opto-mechanical device will be simpler and easier when the characteristics of inspected chips changed. Thus system can accomplish the inspection for 6 surfaces of each chip and determine its quality in real-time before that chip is put onto target wafer. Developed inspection system has advantages and contributions of real-time inspection with high throughput during chip sorting process, and easily adjustment and calibration for all opto-mechanical devices to inspectdifferent types of chips. The first phase of development was accomplished for an AOI system to inspect defects on 5 surfaces of chips. System has been integrated in customer’s chip sorter for testing. The inspecting accuracy for chip backside is better than 95%.

An Optical Inspection System for Chip Defects Using a High Rate Line Scanner

Based on a line scan imager, we propose anew defect inspection system to precisely identify defects with size of greater than criteria from chip backside. Only a corresponding raw image is acquiredfor each chip,and using anopto-mechanical device with very low geometry distortion to make it feasible to neglectprocesses of image calibration and mosaic. Defect inspection is based on a binary chip edge image and a novel methodof using edge pixels statistic. Thus defect size of crack, chipping and glue can be inspected quantitatively and efficiently.From test results by integrating inspection system with experimental and operational chip sorters, our system has capabilities of maximal chip moving speed of0.7 m/sec (5μm resolution) andinspecting chip defects with size accuracyof less than 1.0 pixel. Proposed system has features of automatically acquiring chip images during packaging process, improving performance of image processing and defects inspection. Moreover, manpower, time and cost for chip defect inspection manually can be saved. Chip quality control can be improved as well comparing with the one by manual way.Developed system has been integrated with operational chip sorters successfully for sale now.

DEVELOPMENT OF AN ULTRA THIN DIE-TO-WAFER FLIP CHIP STACKING PROCESS FOR 2.5D INTEGRATION

3D integration relying on novel vertical interconnection technologies opens the gate to powerful microelectronic systems in ultra-thin packages answering the demand of the mobile market. Among these, die-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by, in one hand, the increase of the die surface and the number of I/Os and, on the other hand, the reduction of the vertical dimensions. In our integration scheme we have achieved flip chip stacking (or Face to Face) of 35 μm ultra-thin dies with low stand-off (< 15 μm) copper micro-bumps and tin-silver-copper solders (SAC). Ultra-thin dies are prepared using dicing before grinding (DBG) technique. After DBG, plasma stress release process is applied to the backside of the singulated chips. Copper μbump technology is challenging with this very low profile stacking since the current flip chip process is no longer adapted to this geometry and that the die flatness tolerance become very critical to obtain a high soldering yield. Process improvements have been achieved on the copper pillar fabrication itself with several metallurgy stack configurations as well as new processes using damascene techniques. Furthermore, innovative technologies have been deployed on the pick and place and collective soldering processes. Intermetallic formation during reflow process is achieved through transient liquid phase (TLP) reaction leading to thorough consumption of the tin layer and to the formation of Cu6Sn5 and Cu3Sn compounds. Capillary underfill is finally successfully applied in the narrow die-to-wafer gap by jetting technique. After optimization, electrical tests show a very high yield close to 100% over a representative number of fully populated wafers. Reliability tests have also been carried out at wafer level exhibiting no significant resistance increase or yield loss over 1000 thermal cycles between −40 and +125°C.