Study of Miniaturization of a Silicon Vapor Chamber for Compact 3D Microelectronics, via a Hybrid Analytical and Finite Element Method

Yue Ma,M R S Shirazy,Q Struss,J.P Colonna,A Souifi,L G Fréchette,P Coudrain,C Gontrand

doi:10.14738/tnc.76.7569

Abstract

The interest in silicon vapor chambers (SVCs) has increased in the recent years as they have been identified as efficient cooling systems for microelectronics. They present the advantage of higher thermal conductivity and smaller form factor compared to conventional heat spreaders. This work aims to investigate the potential miniaturization of these devices, preliminary to integration on the backside of mobile device chips, located as close as possible to hotspots. While detailed numerical models of vapor chamber operation are developed, an easy modeling with low computational cost is needed for an effective parametric study. Based on the study of the operating limits, this paper shows the thinning potential of a water filled micropillar for a device operating below 10 W and identify the corresponding vapour core height, and wick thickness.

Highlights

The generation of heat in the circuits became, in a few decades, the factor more limiting in the continuation of the improvement of the performances of the integrated devices for mobile telephony and the wandering applications
Analytical and numerical modeling, and experimental simulations of the heat pipes significantly facilitated a much better understanding of the various physical phenomena found in the heat pipes and the development of computer and experimental methods
Before some true applications are introduced, some transfer mechanisms will be included in the model. These include the effect of external boundary conditions on the interface mass flow profile, the vapor convection, and the flux of the interface mass in the adiabatic phase with a 2-D drive

Summary

Introduction

The generation of heat in the circuits became, in a few decades, the factor more limiting in the continuation of the improvement of the performances of the integrated devices for mobile telephony and the wandering applications. This last era, known as of nano-electronics, is associated to the presence of localized hot points, in particular at the places of strong densities of calculation in the logical cores, and the emergence of stackings of homogeneous and heterogeneous chips. The silicon layers are finer but are insulated between them and are isolated from substrate (BGA or PCB)

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