Chemical Mechanical Polishing Technique Research Articles

Investigation of material removal mechanism of silicon wafer in the chemical mechanical polishing process using molecular dynamics simulation method

Chemical mechanical polishing (CMP) technology, being the mainstream technique of acquiring global planarization and nanometer level surface, has already become an attractive research item. In the case of CMP process, the indentation depth lies in the range of nanometer or sub-nanometer, huge hydrostatic pressure induced in the local deformation area which makes the material removal and surface generation process different from traditional manufacturing process. In order to investigate the physical essence of CMP technique, the authors carry out molecular dynamics (MD) analysis of chemical mechanical polishing of a silicon wafer. The simulation result shows that huge hydrostatic pressure is induced in the local area and leads to the silicon atom transform from the classical diamond structure (α silicon) to metal structure (β silicon). This important factor results in the ductile fracture of silicon and then in the acquisition of a super-smooth surface.

Advanced ultraviolet cross-link process and materials for global planarization

The use of conventional thermal cross-link materials such as negative resists, antireflective coating, and planarizing layers does not lead to excellent planarization for multilevel interconnects and specially via arrays prior to trench patterning for an advance lithography. The large thicknesses bias between the blanket areas and interconnect areas, and between the blanket areas and via arrays are usually observed. Large thickness bias creates problems during next lithography by narrowing the process latitude. Recently, chemical mechanical polishing (CMP) technology has been proposed to achieve the planarization. However, CMP planarization technique is very sensitive to pattern density, and there is a strong possibility that chemical etching reaction will increase the dielectric constant. The current CMP technique still requires a new investment in the equipment. We report another novel approach for global planarization using UV cross-link material (XUVTM) and the dielectric UV exposure unit in coater equipment (Clean Track). This planar technique provides benefits for reducing the thickness bias observed in the 22- to 65-nm generation lithography and imprint processes. Using this technique, XUVTM TNG076 has achieved global planarization of 10-nm thickness bias in 85-nm diameter via topography when the blanket film thickness was only 110 nm.

Surface planarization of ZnO thin film for optoelectronic applications

In this paper, surface morphology and optical properties are investigated to find the optimum microstructure of zinc oxide (ZnO) thin films deposited by radio frequency (RF) magnetron sputtering. To achieve a high transmittance and a low resistivity, we examined various film deposition conditions. The transmittance and surface morphology of ZnO thin films were measured by an ultraviolet (UV)–visible spectrometer and atomic force microscopy (AFM), respectively. In order to improve the surface quality of ZnO thin films, we performed chemical mechanical polishing (CMP) by change of process parameters, and compared the optical properties of polished ZnO thin films. As an experimental result, we were able to obtain good uniformity and improved transmittance efficiency by the CMP technique.

Evaluation of electrical and optical properties of indium tin oxide thin film using chemical mechanical polishing technique

In this study, the optimum process parameters and the influences of their process parameters were investigated for indium tin oxide–chemical mechanical polishing (ITO–CMP) with the sufficient removal rate and the good planarity. And then, the optical property such as transmittance and absorption efficiency, and the electrical characteristics such as sheet resistance, carrier density and Hall mobility were discussed in order to evaluate the possibility of CMP application for the organic light emitting display (OLED) device using an ITO film. Light transmission efficiency and current–voltage characteristics of ITO thin film were improved after CMP process using optimized process parameters compared to that of as-deposited thin film before CMP process.

전기화학 기계적 연마를 이용한 Cu 배선의 평탄화

Copper has been used as an interconnect material in the fabrication of semiconductor devices, because of its higher electrical conductivity and superior electro-migration resistance. Chemical mechanical polishing(CMP) technique is required to planarize the overburden Cu film in an interconnect process. Various problems such as dishing, erosion, and delamination are caused by the high pressure and chemical effects in the Cu CMP process. But these problems have to be solved for the fabrication of the next generation semiconductor devices. Therefore, new process which is electro-chemical mechanical polishing(ECMP) or electro-chemical mechanical planarization was introduced to solve the technical difficulties and problems in CMP process. In the ECMP process, Cu ions are dissolved electrochemically by the applying an anodic potential energy on the Cu surface in an electrolyte. And then, Cu complex layer are mechanically removed by the mechanical effects between pad and abrasive. This paper focuses on the manufacturing of ECMP system and its process. ECMP equipment which has better performance and stability was manufactured for the planarization process.

Porosity model for flows in CMP

In an effort to explore the contribution of the pad, which is usually full of pores, to the performance of CMP (chemical mechanical polishing), a three-dimensional flow model of CMP is presented by assuming that the fluids in the porous layer comply with Darcy’s law, which states that the flow velocity is proportional to the pressure gradient and inverse proportional to the viscosity. The flow equation is deduced accordingly and, by taking advantage of the multi-level technique and line relaxation technique, numerical simulations are carried out to reveal the relationships between the load capacities and operational parameters (including pivot height, roll angle and pitch angle), under conditions with different porous parameters and different thicknesses of the porous layer. The little porous parameter will lead to a prominent increase of load capability (for instance, the load and the moment predicted), which is still augmented by the thicker layer parameter. This will result in a higher material removal ratio of CMP. A pad full of large pores will be used to deduce load capability, facilitating the free flow of the fluids through the pores. The research will add some insights on the mechanism of the CMP technique.

Augmented CMP Techniques for Silicon Carbide

Chemical-mechanical polishing (CMP) has proven a powerful tool for the final polishing of semiconductor and compound semiconductor substrates such as silicon, sapphire, gallium arsenide, and indium phosphide. For these materials, conventional CMP techniques have been able to produce removal rates of several μm/hr while achieving pristine, epi-ready surfaces with subsurface damage less than 10[nm]. For certain materials of interest in the compound semiconductor community, particularly silicon carbide (SiC) and the III-V nitrides, conventional CMP techniques perform poorly. These materials are extremely chemically inert, negating the desired chemical effect leading to removal rates of less than 0.1[μm/hr]. These materials are also very brittle and take damage easily, so a significant amount of material must be removed to ensure a sufficiently low subsurface damage for epitaxy. This paper documents the improvements made in the CMP of 4H and 6H SiC by augmenting a colloidal silica slurry with chemical additives and with special treated nano size diamond particles. The chemical additives proved most effective on 4H SiC, enhancing the slurry’s chemical effect and improving its removal rate. For both materials, the addition of the diamond (Chemical-Mechanical Polish with Diamond, CMP-D) greatly enhanced the removal rate and provided strong synergy between mechanical strain and chemical effect resulting in low subsurface damage.

Polymer Adsorption Effects on Stabilities and Chemical Mechanical Polishing Properties of Ceria Particles

Characterization of ceria particles in the presence of poly(vinyl pyrrolidone) (PVP) was performed by the measurements of adsorbed amounts of PVP, average sizes, and back scattering intensities of the ceria particles as functions of PVP molecular weight and PVP concentration. Adsorption of PVP on the ceria particles enhanced the stability of ceria particles due to steric stabilization of the thick adsorbed layer of PVP. Moreover, SiO2 and Si3N4 films deposited on Si wafers were polished by the ceria particles in the presence of PVP in order to understand the effect of PVP adsorption on chemical mechanical polishing (CMP) technique, together with ceria particles without PVP and re-dispersed ceria particles adsorbed by PVP in water (re-dispersed ceria). Removal rates of the deposited SiO2 and Si3N4 films were decreased with an increase in the concentration of free PVP chains in the dispersion media, while the removal rates by the re-dispersed ceria were the same as those by the ceria particles in the absence of PVP.

FLOW FEATURES IN CMP WITH PAD PROPERTY CONSIDERED

In an effort to explore the contribution of the pad, which is usually fall of pores, to the performance of chemical mechanical polishing (CMP), a three-dimensional flow model of CMP is presented by assuming the fluids in the porous layer complied with Darcy law, i.e., the flow velocity is proportional to the pressure gradient and inverse proportional to the viscosity. The flow equation is deduced accordingly and, by taking advantage of the multilevel technique and line relaxation technique, numerical simulations are carried out to reveal the relationships between the load capacities and operational parameters (including pivot height, roll angle and pitch angle), under conditions with different porous parameters and different thicknesses of the porous layer. The little porous parameter will lead to prominent increase of load capability (for instance, the load and the moment predicted), which is still augmented by the thicker layer parameter. This will result in a higher material removal of CMP. A pad full with larger pores will lead deduction in load capability, facilitating the free flow of the fluids through the pores. The research will add some insights to the mechanism of CMP technique.

Self-differential detection using laminated magnetic tunnel junctions

We report on self-differential detection using laminated magnetic tunnel junctions. The self-differential elements using laminated magnetic tunnel junctions (MTJs) with 400-nm width were fabricated using photolithography. A chemical mechanical polishing technique was used before preparing the top MTJs. The differential resistance shows the signal output of plus and minus at the zero magnetic field, which indicates the potential for applications realizing high-density magnetic random access memories with very fast access time.

An Effective Fabrication Method for Producing Color Filters of Liquid Crystal Displays

An effective process for fabricating color filters (CF) must satisfy three requirements: 1) low-cost material, 2) simple procedures, and 3) high throughput. Several systemic issues affect the conventional CF process, such as the pigment-dispersion method. For high yield and low cost, it is necessary to develop a new fabrication method for CFs which are not affected by these systemic issues. In this paper, an entirely new process for fabricating CFs is introduced. This process, which satisfies the three requirements above, introduces chemical-mechanical polishing techniques to produce CFs for LCDs. Because of the usage of chemical-mechanical polishing techniques, this new CF fabrication method is named the color filter polishing (CFP) method.

High-performance Nb integrated circuit process fabrication

For the last 15 years, Nb-based digital circuits were fabricated with 1-2 kA/cm/sup 2/ junctions. However, use of high critical current density Nb junctions coupled with state-of-the-art photolithographic tools greatly reduced parasitic capacitance and increase circuit speed. Our 150 mm-wafer integrated circuit process uses 6 kA/cm/sup 2/ junctions by following a hybrid approach to both optimize wafer throughput and maintain the critical aspects of device fabrication uniformity and reproducibility. Junctions with area less than 0.25 sq./spl mu/m are defined using an in-house production electron-beam system. Other process layers not requiring such resolution are defined with an in-house i-line optical stepper allowing line pitch down to 1 /spl mu/m and layer-to-layer alignment of less than 80 nm. To avoid circuit-limiting parasitic inductance, a chemical mechanical polishing technique is introduced that enables low-inductance 'outside' contacts to our Josephson junctions. In addition, the judicious use of planarization in a fabrication process to decrease circuit inductance are addressed.

Effect of surface preparation on Ni Ohmic contact to 3C-SiC

The effect of roughness and chemical treatment of 3C-SiC film surface on Ni ohmic contact was studied in this work. 3C-SiC(1 1 1) film was grown on Si(1 1 1) in a chemical vapor deposition reactor. The 3C-SiC surface was polished using a chemical mechanical polishing (CMP) technique to get a smooth and flat surface. The polished surface was oxidized and then was etched in BHF solution to remove subsurface damages formed during the CMP process. The morphology of thus prepared silicon carbide (SiC) surfaces was investigated using SEM and AFM. Ni contact resistance to the 3C-SiC films was evaluated using linear transmission line method pattern. The formation of good ohmic contact characteristics was observed from Ni contact to all the tested SiC samples. After the CMP process, it was found that the RMS roughness of 3C-SiC surface apparently reduces and the specific contact resistance to 3C-SiC decreases as well, in proportion to the SiC surface roughness. The sacrificial oxidation and etching of the polished SiC surface abruptly decrease the contact resistance to be 3.7×10 −4 Ω cm 2. It was shown that the surface morphology and subsurface damage concentration of 3C-SiC films are important factors to give a great effect on the contact characteristic of the 3C-SiC films. However, it was considered that the reduction of subsurface damage concentration is essential to get better contact resistance to 3C-SiC surface.

Surface smoothing of SiGe strain-relaxed buffer layers by chemical mechanical polishing

We flattened the rough surface of the strain-relaxed Si 0.7Ge 0.3 buffer layers by chemical mechanical polishing technique and successfully obtained the ultra-smooth surface whose root mean square roughness was less than 1 nm. The regrowth of Si 0.7Ge 0.3 films on the polished Si 0.7Ge 0.3 buffer layer was found to keep its surface roughness less than 1 nm, and efficient photoluminescence with narrow line width was observed from quantum wells grown on the polished buffer layer. This indicates high crystalline quality of the regrown layer with smooth interfaces, which makes it possible to fabricate high-performance SiGe devices with low surface roughness scattering.

Stacked Pt/SrBi2Ta2-xNbxO9/Pt/IrOx/Ir Capacitor on Poly Plug

A Pt/SrBi2Ta2-xNbxO9(SBTN)/Pt/IrOx/Ir capacitor was successfully fabricated up to the stage of metal-1 etching process on a polysilicon plug for mega-bit ferroelectric random access memory. The integration processes include the chemical-mechanical polishing technique, buried TiN barrier structure and electrode technologies for high thermal stability, and a low-temperature process for SBTN film. The thickness of the iridium layer was the most important factor in controlling the contact resistance of the plug. The Pt thickness also affected the contact resistance of the plug. The best contact resistance of the plug was about 2.0 kΩ/plug at the maximum process temperature of 750°C for 3 min in oxygen ambient at the contact size of φ0.30 µm. Hysteresis curves of the SBTN capacitor were obtained after the metal-1 etching process. The capacitor size dependency of the polarization was not observed in the range of 0.30–25 µm2 and the values of the sensing polarization were about 10 µC/cm2 at the applied voltage of 3 V. In addition, the capacitor exhibited no fatigue loss up to 5×1010 cycles at the switching voltage of 3 V.

Report on the growth of bulk aluminum nitride and subsequent substrate preparation

High-quality, bulk aluminum nitride crystal grains exceeding 1 cm in dimension have been obtained using a self-seeded sublimation–recondensation growth technique at 0.9 mm/h driving rate. X-ray double crystal diffraction and topography show a full-width-at-half-maximum of around 100 arcsec and extensive areas with a density of dislocations less than 10 4 cm −2, respectively. These substrates have been prepared by chemical mechanical polishing techniques to obtain a surface roughness of 1.4–1.6 nm. The size, structural quality, and surface roughness prove these substrates to be adequate for III-nitride device fabrication.

Trench formation and filling technique for dielectric isolation of plasma display panel driver integrated circuits

Trench etching and filling technique for the isolation between the control (low voltage) and the power (high voltage) region in power integrated circuits was investigated. This technique consists of a deep trench formation (8.0 μm) with positive etching using 45% He–O2 of the HBr and SiF4 chemistries followed by filling and global planarization with the chemical mechanical polishing technique. The novel trench etching technique provides better surface quality of 3.1 A roughness measured with atomic force microscopy. The filling and global planarization results in lower leakage current less than 1 nA at the supplying voltage of 400 V.

Growth of Self-Seeded Aluminum Nitride by Sublimation-Recondensation and Substrate Preparation

ABSTRACTBulk aluminum nitride boules have been grown at driving rates of 0.9mm/h by the self-seeded sublimation-recondensation technique. Up to 15mm diameter substrates cut from those boules present large single crystal grains that have been analyzed using different techniques. X-ray double crystal diffraction shows a full-width-at-half-maximum of around 100 arcsec and X-ray topography reveals extensive areas with a density of dislocations less than 104 cm−2. These substrates have been prepared by chemical mechanical polishing techniques to obtain a surface roughness of 1.4-1.6nm.

Effect of surface proximity on end-of-range loop dissolution in silicon

The effect of surface proximity on the dissolution of end-of-range dislocation loops in silicon was investigated by transmission electron microscopy (TEM). A layer of dislocation loops was formed at a depth of 2600 Å by annealing a Si wafer amorphized by a 1015 cm−2, 120 keV, and a 1015 cm−2, 30 keV dual Si+ implant for 30 min at 850 °C. The wafer was diced into 1 cm×1 cm pieces and polished by a chemical–mechanical polishing technique to decrease the loop depth to 1800 and 1000 Å. The samples were then furnace annealed at 900 and 1000 °C in N2 gas. Quantitative TEM analysis revealed that the density of small loops decreases as the loop band is brought closer to the surface. The flux of interstitials to the surface varied inversely with loop depth, indicating that the loop dissolution is diffusion limited. Assuming that the loops maintain a supersaturation of interstitials (CIL) around them, and by integrating the measured interstitial flux from the loop layer to the surface, the relative supersaturation of interstitials near the loop layer (CIL/CI*) was extracted 900 and 1000 °C.

Fabrication of x-ray mask from a diamond membrane and its evaluation

We have prepared a diamond membrane x-ray mask using our novel fabrication techniques which include fluidized bed pretreatment, stress control of diamond film, and chemical-mechanical polishing (CMP), and we have evaluated its important properties for practical use in detail. Surface roughness of diamond film was improved from 55.7 to 1.5 nm Ra using the CMP technique. The transmittance of visible light increased considerably due to the reduction of incident light scattering at the diamond surface, and the transmittance of 2.2-μm-thick smooth diamond film was 92% at 633 nm. In-plane distortion-induced synchrotron radiation irradiation was Max(x,y)=(13,10) nm with a dosage of 12.8 kJ/cm2. In final evaluation, that is, of lithographic performance, we confirmed that a 0.2 μm gate array pattern can be successfully transferred.