Chemical Dry Etching Research Articles

The Influence of Etching Method on the Occurrence of Defect Levels in III-V and II-VI Materials.

The influence of the etching method on the occurrence of defect levels in InAs/InAsSb type-II superlattice (T2SLs) and MCT photodiode is presented. For both analyzed detectors, the etching process was performed by two methods: wet chemical etching and dry etching using an ion beam (RIE-reactive ion etching). The deep-level transient spectroscopy (DLTS) method was used to determine the defect levels occurring in the analyzed structures. The obtained results indicate that the choice of etching method affects the occurrence of additional defect levels in the MCT material, but it has no significance for InAs/InAsSb T2SLs.

Wet chemical poly-Si(n) wrap-around removal for TOPCon solar cells

This work gives an overview on different technological solutions for polysilicon removal in industrial tunnel oxide passivated contact (i-TOPCon) n-type silicon solar cell fabrication. The removal of parasitically deposited poly-Si layers on the front and the edges is a mandatory requirement for a low reverse bias junction leakage current (Irev). A polysilicon removal study on wafer level shows (i) that the efficient removal of the surface oxide layer before poly-Si etching is crucial to achieve short etching times and (ii) that an additive in the KOH solution enhances etching selectivity between poly-Si and silicon oxide surfaces. To evaluate the impact on device level, TOPCon cells have been fabricated in parallel using in-situ n-doped PECVD and LPCVD layers, as well as ex-situ LPCVD poly-Si layers, with another variation of poly-Si removal processes, namely wet chemical inline, wet chemical batch cluster and atmospheric dry etching (ADE). Our results show that a two-minute inline polysilicon removal in hot KOH meets the Irev qualification in case of as deposited in-situ doped layers, whereas for ex-situ doped layers a batch process with a five-minute KOH etching time is needed. LPCVD poly-Si cells show efficiencies above 23%, PECVD poly-Si cells with a batch cluster poly-Si removal process up to 23.4%.

High-Density Patterning of InGaZnO by CH4: a Comparative Study of RIE and Pulsed Plasma ALE.

InGaZnO (IGZO)-based thin-film transistors and selector diodes are increasingly investigated for a broad range of applications such as high-resolution displays, high-density memories, and high-speed computing. However, its potential to be a key material for next-generation devices is strongly contingent on developing patterning processes with minimal damage at nanoscale dimensions. IGZO can be etched using CH4-based plasma. Although the etched by-products are volatile, there remains a concern that passivation─an associated effect arising from the use of a hydrocarbon etchant─may inhibit the patterning process. However, there has been limited discussion on the CH4-based etching of IGZO and the subsequent patterning challenges arising with pitch scaling (<200 nm). In this work, we systematically investigate dry chemical etching schemes to pattern an IGZO film into densely packed nanostructures using CH4. Straight IGZO lines, ∼45 nm in width at a pitch of ∼135 nm, are produced by employing the traditional reactive ion etching method. While the passivating effect of CH4 does not impede the etching process, any further shrinkage of feature and pitch dimensions amplifies reactive ion etching-induced damage in the form of profile distortion and residue redeposition. We show that this is efficiently addressed via atomic layer etching (ALE) of IGZO with CH4 using a pulsed plasma. The unique combination of ALE and plasma pulsing enables controlled reduction of ion-assisted sputtering and redeposition of residues on the patterned IGZO features. This approach is highly scalable and is successfully applied here to achieve well-separated IGZO lines, with critical dimensions down to ∼20 nm at a dense pitch of ∼36 nm. These lines exhibit steep profiles (∼80°) and no undesirable change in IGZO composition post-patterning. Finally, ALE of IGZO under pulsed plasma, reproduced on 300 mm wafers, highlights its suitability in large-scale manufacturing for the intended applications.

Fabrication of Micro-Patterned Chip with Controlled Thickness for High-Throughput Cryogenic Electron Microscopy.

A major limitation for the efficient and high-throughput structure analysis of biomolecules using cryogenic electron microscopy (cryo-EM) is the difficulty of preparing cryo-EM samples with controlled ice thickness at the nanoscale. The silicon (Si)-based chip, which has a regular array of micro-holes with graphene oxide (GO) window patterned on a thickness-controlled silicon nitride (SixNy) film, has been developed by applying microelectromechanical system (MEMS) techniques. UV photolithography, chemical vapor deposition, wet and dry etching of the thin film, and drop-casting of 2D nanosheet materials were used for mass-production of the micro-patterned chips with GO windows. The depth of the micro-holes is regulated to control the ice thickness on-demand, depending on the size of the specimen for cryo-EM analysis. The favorable affinity of GO toward biomolecules concentrates the biomolecules of interest within the micro-hole during cryo-EM sample preparation. The micro-patterned chip with GO windows enables high-throughput cryo-EM imaging of various biological molecules, as well as inorganic nanomaterials.

Perspectives of reactive ion etching of silicate glasses for optical microsystems

We provide a review of the latest research findings as well as the future potential of plasma-based etching technology for the fabrication of micro-optical components and systems. Reactive ion etching (RIE) in combination with lithographic patterning is a well-established technology in the field of micro- and nanofabrication. Nevertheless, practical implementation, especially for plasma-based patterning of complex optical materials such as alumino-silicate glasses or glass-ceramics, is still largely based on technological experience rather than established models. Such models require an in-depth understanding of the underlying chemical and physical processes within the plasma and at the glass–plasma/mask–plasma interfaces. We therefore present results that should pave the way for a better understanding of processes and thus for the extension of RIE processes toward innovative three-dimensional (3D) patterning as well as for the processing of chemically and structurally inhomogeneous silicate-based substrates. To this end, we present and discuss the results of a variety of microstructuring strategies for different application areas with a focus on micro-optics. We consider the requirements for refractive and diffractive micro-optical systems and highlight potentials for 3D dry chemical etching by selective tailoring of the material structure. The results thus provide first steps toward a knowledge-based approach to RIE processing of universal dielectric glass materials for optical microsystems, which also has a significant impact on other microscale applications.

Using block-copolymer nanolithography as a tool to sensitively evaluate variation in chemical dry etching rates of semiconductor materials with sub-5 nm resolution

Ion implantation is a robust and established method to customize the electronic properties of Si. However, fabricating doped, ultrafine semiconductor nanostructures can be challenging. Ion implantation has well-established effects on the dry etch rates of Si, which becomes increasingly consequential as the target dimension shrinks below a few tens of nanometers. While dry etching arrays of block copolymer-templated nanoscale holes (pitch = 37.5 nm, diameter ∼25 nm) into p-type, n-type, and undoped Si, we observed that the lateral etch rate was notably larger for the n-type regions than p-type or undoped regions. By doing image analyses on high resolution electron micrographs of the nanostructured hole arrays, we were able to extract the porosity and average radii of the holes with subnanometer sensitivity and compare the relative etch rates between different doping conditions. We found that degenerately doped n-type silicon consistently etches between approximately 17% and 27% faster in the lateral direction than p-type Si, resulting in significantly larger porosity and, consequently, less mechanical stability. Here, we demonstrate that top-down dimensional analysis of a densely packed porous nanostructure is a robust method for assessing extremely small differences in the lateral, chemical etch rate of doped Si to a degree of sensitivity that was previously unachievable. The minute, dense-packed nature of block copolymer self-assembled nanostructures is shown to be ideal for this application. This proposed method could be useful for designing fabrication processes for heterogeneous nanostructures, as slight dry etch rate variations that may be within process tolerance at the micrometer-scale appear to have nontrivial consequences at the nanometer scale.

Dry Phosphorus silicate glass etching and surface conditioning and cleaning for multi-crystalline silicon solar cell processing

As an alternative to the wet chemical etching method, dry chemical etching processes for Phosphorus silicate glass [PSG} layer rel11ova] using Tri?uormethane/Sulfur Hexafluoride (CHF3/ SF6) gas mixture in commercial silicon-nitride plasma enhanced chemical vapour deposition (SiN-PECVD) system is applied. The dependence of the solar cell performance on the etching temperature is investigated and optimized. It is found that the SiN-PECVD system temperature variation has a signi?cant impact on the whole solar cell characteristics. A dry plasma cleaning treatment of the Si wafer surface after the PSG removal step is also investigated and developed. The cleaning step is used to remove the polymer ?lm which is formed during the PSG etching using both oxygen and hydrogen gases. By applying an additional cleaning step, the polymer ?lm deposited on the silicon wafer surface after PSG etching is eliminated. The effect of different plasma cleaning conditions on solar cell performance is investigated. After optimization of the plasma operating conditions, the performance of the solar cell is improved and the overall gain in ef?ciency of 0.6 % absolute is yielded compared to a cell without any further cleaning step. On the other hand, the best solar cell characteristics can reach values close to that achieved by the conventional wet chemical etching processes demonstrating the effectiveness of the additional O2/H2 post cleaning treatment.

Surface etching and early age hydration mechanisms of steel slag powder with formic acid

Dry chemical etching technology was employed to modify the surface of steel slag powder (SS) with formic acid (FC) aiming to improve the early-age hydraulic ability and soundness of SS as supplementary cementitious material (SCM). Results reveal that FC etching changes the surface mineral composition and increases the surface roughness of SS, resulting in higher specific surface area and hydraulic reactivity of SS. It is found that the total mass loss obtained from thermogravity analysis of FC etched SS pastes at 3 d, 7 d and 28 d all increase, accounting for the enhanced compressive strength at early age. Moreover, both the FC etched SS pastes and the FC etched SS blended cement pastes show much better soundness performances after boiling and autoclaved curing tests when compared with corresponding pastes with SS without treatment. It provides a promising approach for efficient and safe utilization of SS as SCM.

Thermal gas-phase etching of titanium nitride (TiN) by thionyl chloride (SOCl2)

In this work, thermal based gas-phase etching of titanium nitride (TiN) is demonstrated using thionyl chloride (SOCl2) as a novel etchant. A single etchant is utilised in a pulsed fashion to etch TiN. This type of etching technique may also be considered as a chemical gas-phase or dry etching. The removed TiN amount was measured by various techniques like spectroscopic ellipsometry (SE), weighing balance and in some cases X-ray reflectometry (XRR). Additionally, the post-etch surfaces were analysed with X-ray photoelectron spectroscopy (XPS) and bright field transmission electron microscopy (BF-TEM). The surface roughness and morphology of before and after etching TiN films were measured using atomic force microscopy (AFM). The etch per cycle (EPC) was calculated and is plotted as a function of SOCl2 pulse time, purge time after SOCl2 exposure, number of etch cycles and etch temperature (Tetch). An increase in EPC with an increase in SOCl2 pulse time as well as etch temperature was observed. SOCl2 is able to etch TiN starting from 270 °C with an EPC of about 0.03 Å to almost 1.2 Å at 370 °C. Arrhenius plot determined the activation energy (Ea) of about 25 kcal/mol for TiN etching by SOCl2. In addition, the etch selectivity between different substrates such as silicon dioxide (SiO2), silicon nitride (Si3N4) and aluminum oxide (Al2O3) was investigated on blanket as well as 3D structures. Moreover, thermodynamic calculations were performed for various possible etch reactions. Titanium from TiN is proposed to be etched in the form of either titanium trichloride (TiCl3) or titanium tetrachloride (TiCl4). Nitrogen from TiN films may form volatile by-products such as diatomic nitrogen (N2), nitrous oxide (N2O) and nitrogen dioxide (NO2).

Selective-Area Growth of AlInAs Nanowires

High performance transistors are required for the beyond CMOS in terms of low drive voltage, high drain current, high ION/IOFF ratio, and scalability. A superlattice (SL) resonance tunneling field-effect transistor (RTFET) achieves a steep subthreshold slope (SS < 60 mV/decade) while enhancing drain currents with high ION/IOFF ratio as compared with conventional TFETs [1]. However, the difficulty remains in forming high quality SL with various lattice mismatched system. NW structures enable us to maintain lattice strain and increase the critical thickness as compared with planar structures [2]. Thus, NWs can avoid formation of the misfit dislocations in highly lattice mismatched systems. In addition, vertical NWs are suitable for the vertical gate-all-around FETs (VGAA-FETs), which have superior scalability as compared with lateral FETs [3]. The lattice mismatched InGaAs/AlInAs SL is promising candidate for the RTFET [1]. There are, however, no insights regarding nanometer-scaled selective-area growth of AlInAs. Here, we characterized the selective-area growth of AlInAs NWs for the InGaAs/AlInAs NW RTFETs.AlxIn1-xAs NWs were grown by selective-area MOVPE. First, 20-nm-thick SiO2 film was formed on InP(111)B substrates by RF sputtering. Mask openings with various opening diameter (Dop: 50 - 160 nm) and pitch (Pop: 350 - 1000 nm) were formed using the electron beam lithography, dry and wet chemical etching. Next, AlxIn1-xAs was grown in a horizontal MOVPE systems with working pressure of 0.1 atm. Trimethylindium (TMIn), trimethylaluminum (TMAl), arsine (AsH3), and tertiarybutylphosphine (TBP) were used as source precursors. The growth temperature (TG) were varied from 550°C to 650°C. Al composition PAl (PAl = [TMAl] / [TMIn]+[TMAl]) in the vapor phase was changed from 0 to 30%. The partial pressure V/III ratio and growth time (t) were constant (V/III: 411, t: 12 min).Figure 1 shows results of selective-area growth of AlInAs with various PAl. Figure 2 exhibits the TG dependence of the AlInAs growths at PAl = 30%. Pop was 350 nm. Figure 3 shows average height of the NWs with the variation of the NW diameter with respect to PAl [Fig.3(a)] and TG [Fig. 3(b)]. As shown in Fig.1, the NWs had hexagonal pillars surrounded with the {-110} vertical facets and the (111)B plane. The lateral over growth along the <-110> directions were enhanced with increasing the PAl, while vertical NW growth along the <111>B direction was suppressed. The volume of the NWs was also decreased as shown in Fig. 3 (a), meaning that Al atoms disturbed surface diffusion of In atoms on NW sidewalls and SiO2 mask. Since the In atoms rarely reach on the top of the (111)B plane of the NWs under high PAl, the volume of the NWs was decreased. Figure 2 indicated that some AlInAs abnormal deposition occurred on the SiO2 mask at TG = 620°C. In Fig. 3 (b), the volume of the NWs was decreased with increasing TG, and eventually {-110} vertical flat facets disappeared at TG = 650°C, as shown in Fig. 2. This was because that the desorption process of group-III atoms was dominant at high TG. Thus, the optimum TG window to suppress the lateral over growth was thought to be in between 620°C and 650°C at the PAl. After the growth, NWs were etched to characterize Dop and the lateral over growth rate. We determined the diameter difference between the average DNW and Dop as Δdiameter. Figure. 4 shows the Δdiameter as a function of PAl or TG (Pop = 350 nm). In Fig. 4(a), the Δdiameter was gradually increased with PAl,,and, especially, was rapidly enhanced at PAl = 30%, while the NW volume was decreased. This indicated that the Al atoms enhanced the absorption of In atoms on the {-110} sidewalls under higher PAl. In Fig. 4(b) at PAl = 30%, the lateral over growth rate was decreased with increasing TG. Simultaneously, the volume of the grown AlInAs was rapidly decreased. Similar properties were observed in case of PAl = 20%. This indicated that the desorption process became dominant at higher TG. Further characterization of the growth mechanism for the selective-area growth of AlInAs will be presented.

Gas-phase reaction mechanism in chemical dry etching using NF3 and remotely discharged NH3/N2 mixture.

Modeling of dry etching processes requires a detailed understanding of the relevant reaction mechanisms. This study aims to elucidate the gas-phase mechanism of reactions in the chemical dry etching process of SiO2 layers which is initiated by mixing NF3 gas with the discharged flow of an NH3/N2 mixture in an etching chamber. A kinetic model describing the gas-phase reactions has been constructed based on the predictions of reaction channels and rate constants by quantum chemical and statistical reaction-rate calculations. The primary reaction pathway includes the reaction of NF3 with H atoms, NF3 + H → NF2 + HF, and subsequent reactions involving NF2 and other radicals. The reaction pathways were analyzed by kinetic simulation, and a simplified kinetic model composed of 12 reactions was developed. The surface process was also investigated based on preliminary quantum chemical calculations for ammonium fluoride clusters, which are considered to contribute to etching. The results indicate the presence of negatively charged fluorine atoms in the clusters, which are suggested to serve as etchants to remove SiO2 from the surface.

Evaluation of residual defects created by plasma exposure of Si substrates using vertical and lateral pn junctions

Defect creation in both the vertical and lateral directions of Si substrates during plasma processing has become a critical problem in the fabrication of three-dimensional structural devices. In this study, the authors present pn junction structures that can be used to evaluate defects in both the vertical and lateral directions of a Si substrate. Samples with these pn junction structures were exposed to fluorocarbon plasma; after plasma exposure, a chemical dry etching process was employed to determine the influence of residual species on damaged layer formation, and capacitance–voltage measurements were conducted to detect the formation of defects in the Si substrate. The results confirmed that defects created by plasma exposure act as carrier trapping sites. Spectroscopic ellipsometry and time-of-flight secondary ion mass spectrometry revealed that the damaged layers were tens of nanometers thick, and cathodoluminescence analysis identified the presence of “latent” defects in the damaged layer even after furnace annealing. Moreover, current–voltage measurements of devices with different pn junction distances revealed that leakage current in both the vertical and lateral directions increased with decreasing pn junction distance. The experimental results of this study demonstrate that plasma-induced damage (PID) creates defects in both the vertical and lateral directions; lateral defects are assumed to be caused by the stochastic straggling of incident ions, which has been predicted by molecular dynamic simulations. The implementation of devices with lateral pn junctions is essential in improving the understanding of PID mechanisms and designing future electronic devices that are sensitive to latent defects.

Compact water-cooled surface wave plasma source for remote plasma cleaning.

This paper describes the design and operation of a compact surface wave plasma source for remote plasma processing [i.e., plasma enhanced chemical vapor deposition chamber cleaning, dry etching (SiO2, Si3N4, and silicon), photoresist stripping (SU-8), and decapsulation of microchips]. In order to get higher radical generation and increased industrial throughput, the source is designed to generate plasma at a high flowrate. The source is designed to be compact so that it can be more beneficial in the case of positioning multiple sources on a large processing chamber for faster radical cleaning with better uniformity. The source can operate from low to high flowrates (i.e., 100 SCCM H2 or 10 slm NF3) and provide high decomposition rates for NF3. The etching rate for SiO2 (higher than 450 nm/min) is achieved with 2.5 kW microwave power and 3-5 slm. The key advantages of the source are compactness, higher microwave coupling due to indirect water-cooling, and thereby high operating flow and decomposition rates.

INVESTIGATION OF FOCUSED ION BEAM IMPLANTATION PROFILE OF Ga+ IONS FOR APPLICATIONS IN SILICON PHOTONICS

Use of focused ion beam (FIB) as a nanostructuring platform for fast prototype device development in the area of photonics has been attracting a considerable interest. In this study, we report a systematic investigation of focused ion beam (FIB) induced Ga+ ion implantation in silicon on insulator (SOI) structures. The local implantation of Ga+ ions during milling was studied for a wide range of ion doses, ranging from about 1014 to 1017 ions/cm2, using X-ray photoelectron spectroscopy (XPS). Ion implantation has been realized on identically sized areas for each dose by varying the FIB parameters such as dwell time and loop number. It was found that the most of the Ga+ is within the first 50 nm of Si. This suggests that it can be possible to potentially reduce optical losses caused by the ion implantation in any optical application. Methods such as thermal annealing and wet or dry chemical etching can result in removal of the 50 nm implanted layer of SOI, as a result removing the layer causing potentially high optical losses.

Heavily-Doped SOI with SAM-Based Gate Dielectrics in Application to TMDC FETs

Semiconducting transition metal dichalcogenides (TMDC) have been growing interest for both scientific interest and practical applications because of their various material properties. Potential applications and fundamental understanding in new classes of semiconductor materials motivates the fabrication of field-effect transistors (FETs) that are indispensable for probing of carrier transport properties, accumulation of charge and interfacial phenomena. This paper reports a fabrication and characterization of TMDC FETs with heavily-doped silicon-on-insulator substrate. The silicon processing is sophisticated technology that can be extended to the reliable operation of TMDC FETs with high reproducibility. In this presented approach, the heavily-doped SOI can work as a gate electrode in FETs, while the carrier injection into TMDC layer is possible by preparing overlap structure between gate electrode and source/drain contacts. The effectiveness of our approach was demonstrated through the fabrication and characterization of FETs.P-type SOI(88 nm)/BOX(145 nm) wafer was cleaned with SPM and HF solutions. For heavily-doped n-type SOI (n+ SOI), phosphorus-doped spin-on-glass (SOG) was deposited with spin coating and baked on a hot plate at 180 oC. The substrate was annealed at 1000 oC in N2 for 30 min to perform solid phase diffusion. Then, SOG was removed by 1 % HF for 30min. For heavily-doped p-type SOI (p+ SOI), B+ ions were implanted into SOI layer. Activation was performed at 1000 oC in Ar for 30 min. SOI layer was patterned by chemical dry etching with CF4/O2. Thermal SiO2 was grown by dry oxidation at 900 oC for 10 min. Next, AlOx was deposited by RF sputtering. After contact opening with 1 % HF, Al (20 nm)/TiN (20 nm) were deposited by RF sputtering and lift-off for electrical contact to SOI. The substrates were subjected to annealing in forming gas at 420 oC for 30 min to improve the quality of gate dielectrics and electrical contact of gate pad. Al (10 nm)/Au (40nm) was deposited by thermal evaporation and lift-off for contact electrodes. Subsequently, the substrate was exposed to oxygen plasma to form hydroxyl groups on the surface of AlOx. Then, the substrate was immersed into 2-propanol containing 5 mM n-octadecylphosphonic acid (ODPA) for 6 hours at room temperature. Annealing was conducted at 100 oC in N2 for 30 min to stabilize ODPA. The gate dielectrics consists of hybrid ODPA/AlOx/SiO2. Mechanically exfoliated WS2 was transferred to the substrate with the PDMS elastomer. Finally, devices were annealed in N2 at 150 oC for 30 min to improve source/drain contact.The FET operation was observed for both n+ and p+ SOI gate. The threshold voltage (Vth) was evaluated by linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of 0.05 V. In the case of n+ SOI gate electrode, the Vth of -0.71 V, On/Off ratio of 103～104 and subthreshold slope (SS) of 150 mV/dec were evaluated. On the other hand, the Vth of -0.13 V, On/Off ratio of 103～104 and subthreshold slope (SS) of 107 mV/dec were obtained for p+ SOI gate electrode. The difference in Vth between n+ and p+ SOI gate electrodes is derived from the difference in the Fermi level of SOI. The proposed method is suited for research in electrical characteristics of various TMDC semiconductors.

Rear passivated mc-Si solar cells textured by atmospheric pressure dry etching

In this contribution, atmospheric pressure dry etching (ADE) texture is integrated into a passivated emitter and rear cell (PERC) process. In order to make the texture suitable for the solar cell processing, two post-etching processes (inverted pyramid, spherical cap) are implemented and compared. The passivation of the front surface could be improved substantially by the introduction of an Al2O3 layer deposited via atomic layer deposition under the classical antireflection coating SiNX. The impact of the addition of the Al2O3 layer on the contact resistance cannot be neglected and becomes significant for thicknesses higher than 4 nm. Multicrystalline silicon (mc-Si) PERC solar cells are fabricated and measured, leading to a maximum efficiency of about 18.6% for the acidic texture, and for both posts-processed dry chemical etching (ADE) textures. No current gain for the ADE textured wafer compared to the acidic texture could be observed on cell level due to an inhomogeneous etching. However, a gain of 0.4 mA/cm2 for the ADE texture was calculated from local EQE measurements. ADE texture presents therefore 2 advantages: compatibility to diamond wire sawing and a potential current gain for PERC solar cell structure.

Preparation of copper thin film mask by sputtering technique assisted by polymer mask photolithography

This research aims to build cheaply homemade DC magnetron sputtering system for deposit metal thin films on substrate by assist of polymer mask photolithography. The metal thin film is able to use as a hard mask for patterning transfer via chemical wet etching or plasma dry etching process and it also can be used as a metal electrode in micrometre scale. Prepared copper thin films will be measured thickness by scanning electron microscope. Crystalline structure of the thin films will be examined by x-ray diffractometer. Elemental analysis contained in the films will be determined by energy dispersive x-ray spectrometer and morphology of the films will be revealed by scanning electron microscope.

Spray-coatable negative photoresist for high topography MEMS applications

In microsystem technology, the lithographical processing of substrates with a topography is very important. Interconnecting lines, which are routed over sloped topography sidewalls from the top of the protecting wafer to the contact pads of the device wafer, are one example of patterning over a topography. For structuring such circuit paths, a photolithography process, and therefore a process for homogeneous photoresist coating, is required. The most flexible and advantageous way of depositing a homogeneous photoresist film over structures with high topography steps is spray-coating. As a pattern transfer process for circuit paths in cavities, the lift-off process is widely used. A negative resist, like ma-N (MRT) or AZnLOF (AZ) is favoured for lift-off processes due to the existing negative angle of the sidewalls. Only a few sprayable negative photoresists are commercially available. In this paper, the development of a novel negative resist spray-coating based on a commercially available single-layer lift-off resist for spin-coating, especially for the patterning of structures inside the cavity and on the cavity wall, is presented.A variety of parameters influences the spray-coating process, and therefore the patterning results. Besides the spray-coating tool and the parameters, the composition of the resist solution itself also influences the coating results. For homogeneous resist coverage over the topography of the substrate, different solvent combinations for diluting the resist solution, different chuck temperatures during the coating process, and also the softbake conditions, are all investigated. The solvent formulations and the process conditions are optimized with respect to the homogeneity of the resist coverage on the top edge of the cavities. Finally, the developed spray-coating process, the resist material and the process stability are demonstrated by the following applications: (i) lift-off, (ii) electroplating, (iii) the wet and (iv) the dry chemical etching of metals on substrates with topographies.

Influence of Si wafer thinning processes on (sub)surface defects

Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1μm. For the case of Si thinning towards 5μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding+dry etch, vacancy defects were detected in subsurface around 0.5–2μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in between grinding and dry etch it is possible to significantly reduce not only the roughness, but also the remaining vacancies at the subsurface. The surface of grinding+CMP+dry etching gives an equivalent mono vacancy result as to that of grinding+CMP. This combination of thinning processes allows development of extremely thin 3D integration devices with minimal roughness and vacancy surface.

FFT-Impedance Spectroscopy for Silicon Microwire Anodes: Identifying Temperature and Diffusional Changes

Li-ion batteries replace nowadays many devices for different applications like in automotive industries, in smart phones, medicine, aerospace and in other fields. Those applications/fields are very different and many different requirements have to be fulfilled like fast charging, high capacity, long term stability, cost effective production and temperature stability. For a wide application range, a battery has to perform under different temperatures and environmental conditions and nevertheless have a stable and high capacity. The silicon microwire anodes exhibit a high stable capacity of 3150 mAh/g for 300 cycles with a high amount of active material (1.35 mg/cm2) at ambient temperatures. Those anodes are fabricated based on different dry and wet chemical etching processes as pre-structuring of the p-doped Silicon wafer. The main step in the micro-structuring of the silicon microwires lies in the electrochemical macropore etching. By applying a specific current-time profile, macropores of specific diameter and lengths are etched deep in the pre-structured p-doped silicon. Such a profile could be changed according to the needs of the application; changing the lengths and the shape of the pores. In this paper, wire lengths of 36 µm up to 75 µm with a constant thickness of 1.4 µm as well as wire thicknesses between 1.2 µm up to 1.8 µm with a length of 60 µm. During the additional over-etching step, the interstices between the pores are etched away until the wires remain free-standing. In a two-step process, a copper current collector is deposited galvanically on top and in between of the wires. With this approach a good mechanical stability between the silicon wires and the current collector is provided and reduces the lateral volume expansion in only one direction. In a layer-transfer process, the anode could be separated from the silicon wafer. Compared to other silicon anode systems, this approach manages without any conductive additives and with a high amount of active material. The anodes are tested in half cells with metallic Lithium as counter and reference electrode with standard anode electrolyte LP30, provided by BASF, with lithiumhexafluorophosphate (LiPF6) as lithium salt. In order to test the temperature influence on the electrochemical performance of the silicon microwire anodes, this study focuses on the properties inside the anode recorded via in-situ FFT-impedance spectroscopy. In a special set-up the half-cells are heated and recorded between 20 °C up to 75 °C. This technique is a linear response analysis, where a small senoidal signal is superimposed on the dc operation point. In comparison to the standard electrochemical impedance spectroscopy (EIS), perturbations of different frequencies can be applied at the same time between 5 Hz up to 20kHz [1, 2]. The resulting three time constants and resistances can be interpreted as different electrochemical processes inside the battery anodes. Those measurements are correlated with the cyclic voltammetry measurements which are performed in a voltage regime between 1 V and 20 mV for five cycles. In previous studies [3] the size dependency of the wire dimension on the lithiation/delithiation potential was shown at ambient temperatures. Here, it showed that the charge transfer mechanism into the silicon wires of different thicknesses a “radial diffusion” process dominates. This study illustrates the diffusional changes of the properties and its influence on the dimension if temperature is impeded on the anodes. Figure 1a shows results of the time-dependent resistances and time constants for two different temperatures. Figure 1b shows a photo of the type of anodes used for this study. Figure 1 c shows an example of curve of the cycling performance of the silicon wire anodes at different temperatures with SEM images of the microwires after the tests. This study focuses on the in-situFFT-Impedance spectroscopy to monitor the temperature influence on diffusional and charge transfer processes. The recorded time constants shown in Figure 1a at different temperatures show, that the charge transfer process is much slower at high temperatures showing the slow diffusional processes due to side effects. Those results are used for process optimizations to achieve long-term stable anodes under cycling temperatures. Figure 1: Results of electrochemical characterization a) in-situ-FFTImpedance spectroscopy at various temperatures for 75 µm long wires, b) an example of silicon wire anodes, c) cycling experiments at different temperatures. [1] J. Carstensen, H. Föll, A. Cojocaru, and M. Leisner, Phys. Status Solidi C6(7), 1629 (2009). [2] J. Carstensen and H. Föll, ECS Trans.25(3), 11 (2009). [3] S. Noehren, E. Quiroga-Gonzalez, J. Carstensen, and H. Foell, J.Electrochem.Soc. 163(6), A1 (2016). Figure 1