Evaluation of residual defects created by plasma exposure of Si substrates using vertical and lateral pn junctions

Abstract

Defect creation in both the vertical and lateral directions of Si substrates during plasma processing has become a critical problem in the fabrication of three-dimensional structural devices. In this study, the authors present pn junction structures that can be used to evaluate defects in both the vertical and lateral directions of a Si substrate. Samples with these pn junction structures were exposed to fluorocarbon plasma; after plasma exposure, a chemical dry etching process was employed to determine the influence of residual species on damaged layer formation, and capacitance–voltage measurements were conducted to detect the formation of defects in the Si substrate. The results confirmed that defects created by plasma exposure act as carrier trapping sites. Spectroscopic ellipsometry and time-of-flight secondary ion mass spectrometry revealed that the damaged layers were tens of nanometers thick, and cathodoluminescence analysis identified the presence of “latent” defects in the damaged layer even after furnace annealing. Moreover, current–voltage measurements of devices with different pn junction distances revealed that leakage current in both the vertical and lateral directions increased with decreasing pn junction distance. The experimental results of this study demonstrate that plasma-induced damage (PID) creates defects in both the vertical and lateral directions; lateral defects are assumed to be caused by the stochastic straggling of incident ions, which has been predicted by molecular dynamic simulations. The implementation of devices with lateral pn junctions is essential in improving the understanding of PID mechanisms and designing future electronic devices that are sensitive to latent defects.