Charge-pump Phase-locked Loop Research Articles

Computing low-frequency noise in charge-pump phase-locked loops

An efficient simulation method to compute the low-frequency noise spectrum found at the output of charge-pump phase-locked loops is described. It is investigated how such a noise component varies as a function of the division factor.

Design of High Gain, High Bandwidth Op-Amp for Reduction of Mismatch Currents in Charge Pump PLL in 180 nm CMOS Technology

The designing of charge pump with high gain OpAmp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop. Keywords—Charge pump (CP) Orthogonal frequency division multiplexing (OFDM),Phase locked loop (PLL), Phase frequency detector (PFD), Voltage controlled oscillator (VCO),

A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS Process

A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS ProcessDemand of modern measurement systems in submicron CMOS process introduced new challenges in design of low power high frequency clock generation systems. Technical possibilities for clock generation using classical oscillator based on a quartz filter is limited to tens of megahertz. Thus, 1 GHz clock generation is not possible without a frequency multiplier system. It is difficult to achieve, because in submicron process, where the integration of analog and digital blocks poses serious challenges. The proposed solution is a low power charge pump phase-locked loop (CPPLL) with the center frequency of 1 GHz. It combines various modern circuit techniques, whose main aim is to lower power consumption, which is below 800 μW for the whole PLL, while maintaining good noise properties, where the jitter rms is 8.87 ps. The proposed phase-locked loop is designed in 0.18 μm CMOS process.

A Generalized Linear Model for Single Event Transient Propagation in Phase-Locked Loops

A first-order linear model is formulated in closed-form for the examination of transient propagation through charge pump phase-locked loops (PLL). As a result, a novel PLL design parameter-the PLL critical time constant-is discovered as the primary factor influencing extraneous transient generation and propagation through the PLL independent of technology node. Various simulations and experiments have been performed on PLL circuits designed in 130 nm and 90 nm technology nodes. Using the described simulation and laser two-photon absorption (TPA) techniques, the generalized model is shown to accurately predict the output phase displacements and critical time constant of the PLL following transient perturbations, validating the analytical results independent of technology and without the need for calibration parameters. Moreover, the characteristic critical time constant is shown to be valuable for identifying and evaluating the single-event vulnerabilities in charge pump PLL designs.

Non-linear behaviour of charge-pump phase-locked loops

Abstract. The analysis of the mixed analogue and digital structure of charge-pump phase-locked loops (CP-PLL) is a challenge in modelling and simulation. In most cases the system is designed and characterized using its continuous linear model or its discrete linear model neglecting its non-linear switching behaviour. I.e., the time-varying model is approximated by a time-invariant representation using its average dynamics. Depending on what kind of phase detector is used, the scopes of validity of these approximations are different. Here, a preeminent characterization and simulation technique based on the systems event-driven feature is presented, merging the logical and analogue inherent characteristics of the system. In particular, the high-grade non-linear locking process and the dead-zone are analyzed.

Short locking time and low jitter phase-locked loop based on slope charge pump control

A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division

In charge-pump phase-locked loops (CP-PLLs), the reference signal samples the phase delay between reference and feedback signals. When a frequency divider is present in the loop, the spectrum folding of the voltage-controlled oscillator phase noise caused by the inherent subsampling operation adds a relevant contribution to the in-band output noise. This brief elaborates the discrete-time linear model of PLLs to take into account spectrum folding and provides a simple equation for the estimation of the output noise. The closed-form expressions are validated on the basis of behavioral simulations of a third-order CP-PLL.

Phase Locked Loop Integrated System

CMOS-MEMS integration is an indispensable technique for self-calibration of electromechanical performance to make MEMS devices independent on environmental drift or fabrication errors. The goal of single-chip integration (the “holy grail” for the semiconductor timing industry) would be to include the resonator, the oscillator, the PLL and a temperature compensation circuit (TCC) on a single silicon substrate. The current structure of silicon MEMS-based devices utilizes a stacked-die arrangement, housed in a multi-chip package [1]. MEMS-based timing circuits often use PLLs, which can succumb to phase jitter and noise at higher timing frequencies. The architecture of a charge pump phase locked loop (CPPLL) is proposed in this work. It is discussed how its functional blocks influence the overall system performance. We have performed voltage-controlled oscillator (VCO) phase noise analysis and have determined the relationship between CPPLL and VCO phase noises and have discussed the requirements and results of the accomplished design.

A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design

In this paper, a new design of on-chip CMOS voltage regulator, which provides two stable power supplies to charge pump and voltage controlled oscillator (VCO) in charge pump phase-locked loop (PLL), is presented. A power supply noise rejection (PSNR) whose peaking is less than −40dB is achieved over the entire frequency spectrum for VCO supply. The voltage regulator provides maximum 14mA current, and static current is about 780μA at 3.3V. Based on the proposed voltage regulator, a PLL clock generator has been developed and measured in the AMS 0.35μm CMOS process. Operating at 160MHz, a period jitter of 13.64ps was measured under a clean power supply, while period jitter became 16.24ps under a power supply modulated with a 400mV, 10kHz square wave.

Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application

This paper proposes a low-cost design-for-testability (DFT) structure for a classical charge-pump phase-locked loop (CP-PLL) circuit to allow simple digital testing. The proposed CP-PLL DFT structure uses the existing charge-pump circuit and voltage-controlled oscillator (VCO) as a stimulus generator and a measuring device, respectively. Thus, no extra test stimulus or measured instruments are required during testing. The primary advantage is that the analog blocks of the CP-PLL are unchanged and that the test output is purely digital, ensuring that the characteristics of CP-PLL are unaltered and that a suitable on-chip design can be developed using the proposed CP-PLL DFT structure. Fault simulation results indicate that the proposed CP-PLL DFT structure possesses high fault coverage (97.9%). In addition, the physical chip design is presented to show low area overhead (4.48%) and little degradation in performance.

Reduction of pump current mismatch in charge-pump PLL

A charge pump that minimises the mismatch between the charging and discharging currents and keeps the currents constant across a wide output voltage range is described. The improved current matching helps reduce the static phase offset and reference spur of a charge-pump phase-locked loop (PLL) and the constant currents help control the PLL dynamics precisely. The proposed charge pump with dual compensation circuits demonstrates current mismatch of less than 3.2% and pump-current variation of 1.7% over the output voltage ranging from 0.2 to 1.0 V in the 0.13 µm CMOS process with 1.2 V supply.

A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops

This paper presents a charge pump-phase locked loop (CP-PLL) that utilizes a frequency-modulated analog-to-digital converter (FM-ADC) as part of a calibration circuit to compensate for process variations and intemperate operating environments. The calibration circuitry first detects the shift in operating conditions, and then dynamically adjusts the loop bandwidth back to its nominal range to guarantee phase lock for all four process corners and the typical case, and across the telecommunications temperature range of 0 to 80 degC. Calibration comes at the expense of a worst case increase in lock time of 15% and increase of close-in phase noise of 13% for the PLL architecture examined. This self-calibrating PLL, including the FM-ADC, are designed and laid out in TSMC's 0.18-mum RF CMOS process (TSMC18RF).

Fault Classification in Phase-Locked Loops Using Back Propagation Neural Networks

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals

Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). In this letter, a low-power low-noise clock signal generator for ADCs is described. As a clock signal generator, a ring-VCO-based charge pump PLL is used to reduce power dissipation within a given jitter specification. The clock signal generator is fabricated on a CMOS chip with 200-MSPS 10-bit ADC. The measured results show that the ADC keeps a 60-MHz input bandwidth and 53-dB dynamic range and a next-generation mobile wireless terminal can be realized with the ADCs and the on-chip low-power clock generator.

An Application of the Second-Order Passive Lead–Lag Loop Filter for Analog PLLs to the Third-Order Charge-Pump PLLs

A second-order passive lead-lag loop filter for analog phase-locked loop (PLLs) is modified in this paper for the third-order charge-pump PLLs (CPPLLs). The analysis shows that the CPPLL employing the modified loop filter results in smaller area, lower power consumption, or better noise performance than the CPPLL employing the conventional loop filter.

BIST for Measuring Clock Jitter of Charge-Pump Phase-Locked Loops

This paper presents a built-in self-test (BIST) circuit that measures the clock jitter of the charge-pump phase-locked loops (PLLs). The jitter-measurement structure is based on a novel time-to-digital converter (TDC) which has a high resolution. A small area overhead is also achieved using the voltage-controlled oscillator and the loop filter of the PLL under test as parts of the TDC. The experiment result shows that the resolution is about 1 ps and that the measurement error is smaller than 20%.

A 50-GHz Phase-Locked Loop in 0.13-$\mu$m CMOS

A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13-mum logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology.

Stability Analysis of Fourth-Order Charge-Pump PLLs Using Linearized Discrete-Time Models

In this paper, we derive state equations for linearized discrete-time models of forth-order charge-pump phase-locked loops. We solve the differential equations of the loop filter by using the initial conditions and the boundary conditions in a period. The solved equations are linearized and rearranged as discrete-time state equations for checking stability conditions. Some behavioral simulations are performed to verify the proposed method. By examining the stability of loops with different conditions, we also propose an expression between the lower bound of the reference frequency, the open loop unit gain bandwidth, and the phase margin.

A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs

This brief presents a new technique for minimizing reference spurs in a charge-pump phase-locked loop (PLL) while maintaining dead-zone-free operation. The proposed circuitry uses a phase/frequency detector with a variable delay element in its reset path, with the delay length controlled by feedback from the charge-pump. Simulations have been performed with several PLLs to compare the proposed circuitry with previously reported techniques. The proposed approach shows improvements over previously reported techniques of 12 and 16 dB in the two closest reference spurs

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inversion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance