Charge Trapping Non-volatile Memory Device Research Articles

An organic ambipolar charge trapping non-volatile memory device based on double heterojunctions

An organic ambipolar charge trapping non-volatile memory device is proposed based on tris(8-hydroxy quinoline) aluminum(Alq3)/ fullerene(C60)/pentacene double heterojunctions. The double heterojunctions were analyzed and compared with the sole heterojunction. Even though the Alq3/pentacene sole heterojunction shows a negative threshold voltage shift for programming under negative biasing, light illumination is required to efficiently erase. In contrast, for C60/pentacene sole heterojunction, the negative shift of threshold voltage is observed even with a positive erasing voltage. By combining the two trapping layers, a large memory window with fully-electrical programming and erasing is obtained. The efficient programming and erasing of the double heterojunctions structure are analyzed, sufficient electrons can be injected that enables the electrical erasing, and the negative shift of the threshold voltage under positive erasing voltage for the C60/pentacene structure is suppressed due to the suppression of the large built-in potential for the sole heterojunction, which can be verified by a large positive shift for the pentacene/C60/pentacene double heterojunctions.

A comparative study of charge trapping in HfO2/Al2O3 and ZrO2/Al2O3 based multilayered metal/high-k/oxide/Si structures

The electrical properties of multilayered HfO2/Al2O3/HfO2/SiO2 and ZrO2/Al2O3/ZrO2/SiO2 metal-oxide semiconductor capacitors were investigated in order to evaluate the possibility of their application in charge-trapping non-volatile memory devices. The stacks were deposited by reactive radiofrequency magnetron sputtering on Si substrates with thermal SiO2 with a thickness ranging from 2 to 5nm. Both types of stacks show negative initial oxide charge and its density is higher for HfO2-based structures. Memory window up to 6V at sweeping voltage range of ±16V was obtained for HfO2-based stacks. The hysteresis in these structures is mainly due to a trapping of electrons injected from the Si substrate. The charge-trapping properties of ZrO2-based samples are compromised by the high leakage currents and the dielectric breakdown. The conduction through the capacitors at low applied voltages results from hopping of thermally excited electrons from one isolated state to another. The energy depth of the traps participating in the hopping conduction was determined as ~ 0.7eV for the HfO2-based layers and ~ 0.6eV for ZrO2-based ones, originating from negatively charged oxygen vacancies. At high electric fields, the current voltage characteristics were interpreted in terms of space charge limited currents, Fowler–Nordheim tunneling, Schottky emission, and Poole–Frenkel mechanism. The charge retention characteristics do not depend on the thickness of the tunnel SiO2.

Model based precise analysis of the injection currents in Al/ZrO2/Al2O3/ZrO2/SiO2/Si structures for use in charge trapping non-volatile memory devices

Metal/insulator/Silicon (MIS) capacitors containing multilayered ZrO2/Al2O3/ZrO2/SiO2 dielectric were investigated in order to evaluate the possibility of their application in charge trapping non-volatile memory devices. The ZrO2/Al2O3/ZrO2 stacks were deposited by reactive rf magnetron sputtering on 2.4nm thick SiO2 thermally grown on p-type Si substrate. C–V characteristics at room temperature and I–V characteristics recorded at temperatures ranging from 297K to 393K were analyzed by a comprehensive model previously developed. It has been found that Poole-Frenkel conduction in ZrO2 layers occurs via traps energetically located at 0.86eV and 1.39eV below the bottom of the conduction band. These levels are identified as the first two oxygen vacancies related levels in ZrO2, closest to its conduction band edge, whose theoretical values reported in literature are: 0.80eV, for fourfold, and 1.23eV, for threefold coordinated oxygen vacancies.

Threshold Voltage Fluctuations in Localized Charge-Trapping Nonvolatile Memory Devices

Threshold voltage fluctuations are studied in localized charge-trapping nonvolatile memory devices. Intensive program/erase cycling followed by high-temperature bake shifts the mean Vt of programmed bits and increases the variance of the Vt distribution. After long enough bake, the Vt decay saturates, and the mean Vt and the variance stabilize. Upon continuing bakes, Vt's of individual bits are found to fluctuate up and down while the envelope remains fixed. The formation of a stable envelope of randomly fluctuating bits is modeled in terms of charge displacements of trapped electrons confined to the cells' nitride storage layer. Implications to product reliability under high-temperature stress are discussed.

Interface states formation in a localized charge trapping nonvolatile memory device

Two NROM nonvolatile memory devices that are practically identical but exhibit different postcycling characteristics are investigated. Electrical characterizations combined with two-dimensional drift diffusion simulations were employed to quantify and differentiate the retention loss mechanisms. The comparison demonstrates the coexistence of two retention loss mechanisms, lateral charge transport in the nitride layer, and hot carrier induced interface states formation and anneal. The fabrication conditions in the various studies reported in the literature and the resultant impact on interface states formation are most likely the cause of the formally nonresolved debate regarding the origin of retention loss in NROM technology. The reduction in interface state formation during cycling is a key to achieving high reliability NROM cells and products.

Unified retention model for localized charge trapping nonvolatile memory device

Retention after cycling in an NROM nonvolatile memory cell is investigated. Electrical characterizations combined with two-dimensional simulations were employed. By combining subthreshold current characterizations with gate-induced drain leakage measurements, the retention loss mechanisms are quantified and differentiated. A unified retention model for the NROM technology is proposed, incorporating both lateral charge transport in the nitride layer and hot carrier-induced interface-states formation. The fabrication conditions in the various studies reported in the literature and the resultant impact on interface-states formation are most likely the cause of the formally nonresolved debate regarding the origin of retention loss in NROM technology.

Spatial characterization of localized charge trapping and charge redistribution in the NROM device

This paper discusses the spatial characterization and redistribution of hot carriers injected into the gate dielectric stack of the NROM localized charge trapping non-volatile memory device. The spatial characterization is based on a novel experimental method, which combines subthreshold and gate-induced-drain-leakage current measurements with two-dimensional drift diffusion simulations. It is shown that electron and hole trapping takes place in a narrow region near the drain junction, with a ∼20 nm tail situated above the transistor channel. The ability to adjust the hole injection location was demonstrated by characterizing trapped hole distributions following erasure under two different bias conditions. The NROM cell erase state threshold voltage drift is spatially quantified and shown to be a manifestation of lateral charge redistribution originating from the mismatch between the trapped electron and hole distributions inside the gate dielectric stack. The charge localization concept is shown to allow NROM technology to achieve both excellent scalability and high reliability.

Lateral charge transport in the nitride layer of the NROM non-volatile memory device

NROM is a two bits per cell, localized charge trapping non-volatile memory device. A unique erase state threshold voltage drift in the NROM cell is presented. The research aimed to determine the origin of this phenomenon and assess the role of lateral misalignment between electrons and holes trapped in the ONO gate dielectric stack. Electrical characterizations combined with two-dimensional drift diffusion simulations and charge-tunneling theory were employed. It was found that the drift direction could be controlled by alteration of the voltages applied to the cell during erasure. Furthermore, the drift diminished with the number of program/erase cycles performed on the cell and demonstrated an insensitivity to vertical electric fields applied to the device. A lateral trap-to-trap hole-tunneling model was developed and shown to resolve the unique drift characteristics. Theories ascribing vertical charge tunneling to this phenomenon are demonstrated as inconsistent with most of these observations.