Spatial characterization of localized charge trapping and charge redistribution in the NROM device

Abstract

This paper discusses the spatial characterization and redistribution of hot carriers injected into the gate dielectric stack of the NROM localized charge trapping non-volatile memory device. The spatial characterization is based on a novel experimental method, which combines subthreshold and gate-induced-drain-leakage current measurements with two-dimensional drift diffusion simulations. It is shown that electron and hole trapping takes place in a narrow region near the drain junction, with a ∼20 nm tail situated above the transistor channel. The ability to adjust the hole injection location was demonstrated by characterizing trapped hole distributions following erasure under two different bias conditions. The NROM cell erase state threshold voltage drift is spatially quantified and shown to be a manifestation of lateral charge redistribution originating from the mismatch between the trapped electron and hole distributions inside the gate dielectric stack. The charge localization concept is shown to allow NROM technology to achieve both excellent scalability and high reliability.