Retention loss characteristics of localized charge-trapping devices

Abstract

NROM/sup /spl reg// is a localized charge trapping memory device that realizes two physical bits per cell. A lateral charge redistribution-based retention loss model for electrons, locally trapped in the nitride layer has been published recently. The energy distribution of the electron traps has been extracted and the ability to predict the retention loss behavior has been confirmed. Nonetheless, this model dealt with the uni-charge case, of trapped electrons. The more intricate "two-charge" scenario, electron and hole trapping following a program/erase sequence, has not been discussed yet. An attempt has been made to explain threshold voltage drifts in the NROM cell by vertical charge transport. While such models may be attributed to discrete storage node non-volatile memories featuring a tunnel oxide, the thick bottom oxide layers incorporated in NROM devices inhibit vertical charge transport. In this paper we propose a different retention after cycling theory, based on a direct extension of the lateral re-distribution model. We claim that the retention loss is due to the lateral redistribution of holes trapped in the nitride layer above the n/sup +/ junction. Electrons that are localized in deeper traps induce an electric field that directs hole transport towards the channel.