Charge Trapping Layer Research Articles

Perhydropolysilazane Charge‐Trap Layer in Solution‐Processed Organic and Oxide Memory Thin‐Film Transistors

AbstractThe charge trapping property of spin‐coated perhydropolysilazane (PHPS) layers for solution‐processed organic and oxide thin film memory transistors is demonstrated. The nitrogen content within the PHPS layer is decreased by increasing the annealing temperatures from room temperature to 450 °C. The PHPS layer added to the SiO2 gate insulator in the charge trap memories (CTMs) shows good memory functionalities which are electrically programmable, and is erased either electrically or optically depending on the semiconductor used. The stored or erased charges in the p‐type semiconductor‐based CTM result in relatively large threshold voltage shifts (∆VTH > 60 V) and large memory on‐ and off‐current ratio (IM,ON/IM,OFF > 103) with the respective memory output current extrapolated to 108 s. The n‐type CTM shows ∆VTH ≈ 20 V, IM,ON/IM,OFF of 0.5 × 103 and is extrapolated to 1015 s. It is concluded that the origin of the charge‐traps in both the p‐type and n‐type CTMs mainly originates from the PHPS charge trap layer (CTL) and greatly occurs in highly concentrated nitrogen PHPS layers. There is a high possibility of using the PHPS CTL in a wide variety of cost‐effective CTMs even with high temperature processed semiconductors.

Influence of Nanoscale Charge Trapping Layer on the Memory and Synaptic Characteristics of a Novel Rubidium Lead Chloride Quantum Dot Based Memristor

AbstractMemristors are one of the fastest developing electronic devices in the field of data storage and brain inspired neural computing. As a two terminal device, memristors are numerously utilized as resistive random access memories (RRAM) and energy efficient artificial synapses. Herein, the fabrication of perovskite‐type rubidium lead chloride quantum dots (RPCQDs) is reported as a functional layer in a memristive system. The device, Al/RPCQDs/indium doped tin oxide (ITO), exhibits a cycling‐induced decrease in SET voltage, where Al and ITO work as a top and bottom electrode respectively. However, time dependent self‐recovery to the pristine state is observed in the Al/RPCQDs/ITO device. In contrast, the self‐rejuvenation is suppressed when a buffer capped conducting polymer (BCCP) is incorporated on the ITO layer to make a Al/RPCQDs/BCCP/ITO structure. This customized device structure successfully retains the reproducible bipolar switching behavior without severe deviation in operating voltages, which helps in studying reliable memristive properties. In addition, the Al/RPCQDs/BCCP/ITO memristive device also demonstrates some essential synaptic functions such as pair‐pulse facilitation, long‐term potentiation, and long‐term depression.

Hf-Based and Zr-Based Charge Trapping Layer Engineering for E-Mode GaN MIS-HEMT Using Ferroelectric Charge Trap Gate Stack

E-mode hybrid ferroelectric charge storage gate (FEG) GaN HEMTs have shown promising performances for future power GaN device applications. The FEG-HEMT demonstrates a combination of ferroelectric polarization and charge trapping process in the ferro-charge-storage gate stack, leading to a positive threshold voltage shift for E-mode operations. In this work, FEG-HEMTs with various Hf-based and Zr-based charge trapping layers are systematically studied. FEG-HEMT which employed nitrogen incorporated HfO2 (HfON) as the charge trapping layer shows an E-mode operation with the highest Vth (+2.3 V) after initialization. Moreover, the gate leakage of the HfON sample was further reduced due to the nitrogen incorporation, leading to a more complete charging process during initialization. The Vth instability is also addressed and investigated. The FEG-HEMT with HfON as the charge trapping layer showed a negligible Vth hysteresis (-43mV) and the highest Vth stability in both the PBTI (positive bias threshold voltage instability) and NBTI (negative bias threshold voltage instability) test measurements.

Transparent Floating Gate Memory Based on ZnO Thin Film Transistor With Controllable Memory Window

The transparent floating gate memory based on zinc oxide (ZnO) thin film transistors (TFTs) was fabricated by using one-step atom layer deposition of aluminia tunneling and ZnO charge-trap layers. Free electrons trapping mechanism of this memory device is proposed after systematical investigation of gate voltage scanning and thickness of the trapping layer. Furthermore, the relationship between the geometrical size of the charge-trapping layer and the memory window is explored. The devices with different memory windows can be controlled simply by designing the area of their trapping layer without any external process, which is much beneficial to the low cost process fabrication of the memory array and driving circuits, since the memory and switch/digital transistors can be fabricated at the same time. Finally, the presented TFT memory exhibits a maximum memory window of 15 V, excellent fatigue and retention properties more than 30,000 s without any charge loss. The transparent floating gate memory with the ZnO charge-trap layer has great potential for application of 3D, transparent or multi-value memory.

Triboelectric Nanogenerator with Intermediate Nanofibrous Charge Trapping Layer for Self-Powered Human Activity Recognition and User Identification Using Deep Learning

Triboelectric Nanogenerator with Intermediate Nanofibrous Charge Trapping Layer for Self-Powered Human Activity Recognition and User Identification Using Deep Learning

Improvement of the Charge Retention of a Non-Volatile Memory by a Bandgap-Engineered Charge Trap Layer

In recent years, research based on HfO2 as a charge trap memory has become increasingly popular. This material, with its advantages of moderate dielectric constant, good interface thermal stability and high charge trap density, is currently gaining in prominence in the next generation of nonvolatile memory devices. In this study, memory devices based on a-IGZO thin-film transistor (TFT) with HfO2/Al2O3/HfO2 charge trap layer (CTL) were fabricated using atomic layer deposition. The effect of the Al2O3 layer thickness (1, 2, and 3 nm) in the CTL on memory performance was studied. The results show that the device with a 2-nm Al2O3 layer in the CTL has a 2.47 V memory window for 12 V programming voltage. The use of the HfO2/Al2O3/HfO2 structure as a CTL lowered the concentration of electrons near the tunnel layer and the loss of trapped electrons. At room temperature, the memory window is expected to decrease by 0.61 V after 10 years. The large storage window (2.47 V) and good charge retention (75.6% in 10 years) of the device under low-voltage conditions are highly advantageous. The charge retention of the HfO2/Al2O3/HfO2 trap layer affords a feasible method for fabricating memory devices based on a-IGZO TFT.

Topochemical Synthesis of Copper Phosphide Nanoribbons for Flexible Optoelectronic Memristors

AbstractMetal phosphide nanoribbons are suitable building blocks for flexible photoelectronic microdevices due to the special electronic structure, large contact area, and excellent mechanical properties. In this work, single‐crystal copper phosphide nanoribbons (Cu3P NRs) are prepared topochemically from crystalline red phosphorus nanoribbons (cRP NRs) to retain the cRP morphology. The Cu3P NRs are used to construct flexible photoelectronic memristors on the ITO/PEN substrate with the native oxidized shell of Cu3P NRs serving as the charge trapping layer to modulate the resistance switching characteristics. The Cu3P NRs‐based memristors have outstanding nonvolatile memory properties in different mechanical bending states and different bending times. Optically and electrically modulated artificial synaptic functions are observed from the Cu3P NRs‐based memristors and owing to the memory backtracking function, pattern recognition is achieved with the Ag/Cu3P/ITO artificial synapse array. The topochemical synthesis method constitutes a universal approach to produce nanostructured compounds with an unusual morphology and specific crystalline orientation. The results also reveal that metal phosphides are excellent materials in memristors for future optoelectronic neuromorphic computing.

ZnO nanowire optoelectronic synapse for neuromorphic computing

Artificial synapses that integrate functions of sensing, memory and computing are highly desired for developing brain-inspired neuromorphic hardware. In this work, an optoelectronic synapse based on the ZnO nanowire (NW) transistor is achieved, which can be used to emulate both the short-term and long-term synaptic plasticity. Synaptic potentiation is present when the device is stimulated by light pulses, arising from the light-induced O2 desorption and the persistent photoconductivity behavior of the ZnO NW. On the other hand, synaptic depression occurs when the device is stimulated by electrical pulses in dark, which is realized by introducing a charge trapping layer in the gate dielectric to trap carriers. Simulation of a neural network utilizing the ZnO NW synapses is carried out, demonstrating a high recognition accuracy over 90% after only 20 training epochs for recognizing the Modified National Institute of Standards and Technology digits. The present nanoscale optoelectronic synapse has great potential in the development of neuromorphic visual systems.

Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory.

In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.

Large memory window with low operating voltages using Hf 1.5 Gd 2 O 6 charge trapping layer and thin MoS 2 channel

A charge-trapping memory (CTM) field effect transistor (FET) featured with an Hf1.5Gd2O6 charge trapping layer and thin MoS2 channel are fabricated. Benefit from high defect densities of the Hf1.5Gd2O6 film, large memory windows are achieved under low operating voltages (2.3 V@4 V, 3.1 V@5 V and 3.6 V@6 V), which distinctly outperform previously reported CTMs. In addition, high programming/erase (P/E) speeds, good data retention and endurance characteristics are experimentally demonstrated. The results demonstrate a feasibility of CTM FET with an HfGdO charge trapping layer and thin MoS2 channel for ultra-low power memory devices application.

High Pressure Deuterium Passivation of Charge Trapping Layer for Nonvolatile Memory Applications.

In this study, the deuterium passivation effect of silicon nitride (Si3N4) on data retention characteristics is investigated in a Metal-Nitride-Oxide-Silicon (MNOS) memory device. To focus on trap passivation in Si3N4 as a charge trapping layer, deuterium (D2) high pressure annealing (HPA) was applied after Si3N4 deposition. Flat band voltage shifts (ΔVFB) in data retention mode were compared by CV measurement after D2 HPA, which shows that the memory window decreases but charge loss in retention mode after program is suppressed. Trap energy distribution based on thermal activated retention model is extracted to compare the trap density of Si3N4. D2 HPA reduces the amount of trap densities in the band gap range of 1.06–1.18 eV. SIMS profiles are used to analyze the D2 profile in Si3N4. The results show that deuterium diffuses into the Si3N4 and exists up to the Si3N4-SiO2 interface region during post-annealing process, which seems to lower the trap density and improve the memory reliability.

Synaptic Weight Evolution and Charge Trapping Mechanisms in a Synaptic Pass-Transistor Operation With a Direct Potential Output.

We present an intensive study on the weight modulation and charge trapping mechanisms of the synaptic transistor based on a pass-transistor concept for the direct voltage output. In this article, the pass-transistor concept for a metal-oxide-semiconductor field-effect transistor is employed to a synaptic transistor with a charge trapping layer, which is named a synaptic pass transistor (SPT). Based on this SPT concept, the voltage signal would be provided at the output terminal directly without requiring a complicated circuitry, whereas the conventional synaptic transistor with the current output needs a conversion circuit. For the SPT, the definition of the synaptic weight as a transfer efficiency and operation principles of the SPT with charge-trapping mechanisms is analyzed theoretically. The respective semiconductor device simulation results, such as synaptic output and weight modulations as a function of time for a synaptic depression and facilitation, are presented with detailed analysis. Also, it is shown that an SPT array configuration can perform a synaptic scaling by itself, i.e., a self-normalization of the weight, which is confirmed with the simulation results of learning a simple classification example. Moreover, to verify the potential usage of the SPT array as an analog artificial intelligence accelerator, a classification task for a standard data set, e.g., Modified National Institute of Standards and Technology database (MNIST), is also tested by monitoring the accuracy. Finally, it is found that SPTs proposed here can exhibit low power consumption at a device level as well as sufficient accuracy at the array level while more closely mimicking the biological synapse.

UV light modulated synaptic behavior of MoTe2/BN heterostructure

Electrical synaptic devices are the basic components for the hardware based neuromorphic computational systems, which are expected to break the bottleneck of current von Neumann architecture. So far, synaptic devices based on three-terminal transistors are considered to provide the most stable performance, which usually use gate pulses to modulate the channel conductance through a floating gate and/or charge trapping layer. Herein, we report a three-terminal synaptic device based on a two-dimensional molybdenum ditelluride (MoTe2)/hexagonal boron nitride (hBN) heterostructure. This structure enables stable and prominent conductance modulation of the MoTe2 channel by the photo-induced doping method through electron migration between the MoTe2 channel and ultraviolet (UV) light excited mid-gap defect states in hBN. Therefore, it is free of the floating gate and charge trapping layer to reduce the thickness and simplify the fabrication/design of the device. Moreover, since UV illumination is indispensable for stable doping in MoTe2 channel, the device can realize both short- (without UV illumination) and long- (with UV illumination) term plasticity. Meanwhile, the introduction of UV light allows additional tunability on the MoTe2 channel conductance through the wavelength and power intensity of incident UV, which may be important to mimic advanced synaptic functions. In addition, the photo-induced doping method can bidirectionally dope MoTe2 channel, which not only leads to large high/low resistance ratio for potential multi-level storage, but also implement both potentiation (n-doping) and depression (p-doping) of synaptic weight. This work explores alternative three-terminal synaptic configuration without floating gate and charge trapping layer, which may inspire researches on novel electrical synapse mechanisms.

Flexible Layered-Graphene Charge Modulation for Highly Stable Triboelectric Nanogenerator.

The continuous quest to enhance the output performance of triboelectric nanogenerators (TENGs) based on the surface charge density of the tribolayer has motivated researchers to harvest mechanical energy efficiently. Most of the previous work focused on the enhancement of negative triboelectric charges. The enhancement of charge density over positive tribolayer has been less investigated. In this work, we developed a layer-by-layer assembled multilayer graphene-based TENG to enhance the charge density by creatively introducing a charge trapping layer (CTL) Al2O3 in between the positive triboelectric layer and conducting electrode to construct an attractive flexible TENG. Based on the experimental results, the optimized three layers of graphene TENG (3L-Gr-TENG) with CTL showed a 30-fold enhancement in output power compared to its counterpart, 3L-Gr-TENG without CTL. This remarkably enhanced performance can be ascribed to the synergistic effect between the optimized graphene layers with high dielectric CTL. Moreover, the device exhibited outstanding stability after continuous operation of >2000 cycles. Additionally, the device was capable of powering 20 green LEDs and sufficient to power an electronic timer with rectifying circuits. This research provides a new insight to improve the charge density of Gr-TENGs as energy harvesters for next-generation flexible electronics.

Low ON-State Resistance Normally-OFF AlGaN/GaN MIS-HEMTs With Partially Recessed Gate and ZrOₓ Charge Trapping Layer

Novel normally-OFF AlGaN/GaN MIS-high electron mobility transistors (HEMTs) with a ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> charge trapping layer are proposed. The deposition of the ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> charge trapping layer on the partially recessed AlGaN in conjunction with the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric has been accomplished. The developed MIS-HEMTs exhibit a threshold voltage of 1.55 ± 0.4 V and a maximum drain current of 730 ± 6 mA/mm, while associated low ON-resistance of 7.1 ± 0.2 Ω·mm, for a gate to drain separation of 3 μm. The TCAD simulation results are presented to explore the charge trapping and de-trapping behaviors. Moreover, the devices exhibit a high breakdown voltage. The results indicate the merits of employing ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> charge trapping layer to realize the normally-OFF GaN devices with low ON-state resistance.

Near-Infrared Artificial Synapses for Artificial Sensory Neuron System.

The computing based on artificial neuron network is expected to break through the von Neumann bottleneck of traditional computer, and to greatly improve the computing efficiency, displaying a broad prospect in the application of artificial visual system. In the specific structural layout, it is a common method to connect the discrete photodetector with the artificial neuron in series, which enhances the complexity of signal recognition, conversion and storage. In this work, organic small molecule IR-780 iodide is inserted into the memory device as both the charge trapping layer and near-infrared (NIR) photoresponsive film. Through electrical and optical regulation, artificial synaptic functions including short-term plasticity, long-term plasticity, and spike rate dependence are realized. In the established artificial sensory neuron system, NIR optical pulses can significantly improve the spiking rate. Moreover, the spiking neural networks are further constructed by simulation for handwritten digit classification. This research may contribute to the development of light driven neural robots, optical signal encryption, and neural computing.

C-axis aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) and high-k charge trapping film for flash memory application

C-axis aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) was obtained using tantalum (Ta) induced crystallization with appropriate post-annealing and applied as a channel of the thin film transistor (TFT) flash memory device. Atomic layer deposited Al2O3, HfO2, and Al2O3 thin films were used for the blocking layer (BL), charge trap layer (CTL) and tunneling layer (TL), respectively. X-ray diffraction (XRD) and high-resolution transmission electron microscopy (HRTEM) analysis show the formation of a CAAC-IGZO layer with a (009) peak on the c-axis. Compared with a device using amorphous IGZO (a-IGZO) material as a channel, a device using CAAC-IGZO as a channel material shows improved transistor characteristics with low threshold voltage, low subthreshold swing, high field effect mobility, and high on-current to off-current ratio (ION/OFF). In the program/erase (P/E) characterization, CAAC-IGZO channel device (ΔVTH = 1.0 V) has a larger memory window than a-IGZO channel device (ΔVTH = 0.5 V). The retention and endurance characteristics of the CAAC-IGZO device were obtained up to 104 s and 103 cycles, respectively, without any noticeable degradation. It is believed that the proposed CAAC-IGZO material could be considered as an alternative to the poly-Si material having defects due to the grain-boundaries.

Highly Reliable Charge Trap‐Type Organic Non‐Volatile Memory Device Using Advanced Band‐Engineered Organic‐Inorganic Hybrid Dielectric Stacks

AbstractWith the recent interest in data storage in flexible electronics, highly reliable charge trap‐type organic‐based non‐volatile memory (CT‐ONVM) has attracted much attention. CT‐ONVM should have a wide memory window, good endurance, and long‐term retention characteristics, as well as mechanical flexibility. This paper proposed CT‐ONVM devices consisting of band‐engineered organic–inorganic hybrid films synthesized via an initiated chemical vapor deposition process. The synthesized poly(1,3,5‐trimethyl‐1,3,5,‐trivinyl cyclotrisiloxane) and Al hybrid films are used as a tunneling dielectric layer and a blocking dielectric layer, respectively. For the charge trapping layer, different Hf, Zr, and Ti hybrids are examined, and their memory performances are systematically compared. The best combination of hybrid dielectric stacks showed a wide memory window of 6.77 V, good endurance of up to 104 cycles, and charge retention of up to 71% after 108 s even under the 2% strained condition. The CT‐ONVM device using the hybrid dielectric stacks outperforms other organic‐based charge trap memory devices and is even comparable in performance to conventional inorganic‐based poly‐silicon/oxide/nitride/oxide/silicon structures devices. The CT‐ONVM using hybrid dielectrics can overcome the inherent low reliability and process complexity limitations of organic electronics and expedite the realization of wearable organic electronics.

Characterization of nanoscale vertical-channel charge-trap memory thin film transistors using oxide semiconducting active and trap layers

We fabricated vertical-channel charge-trap memory thin film transistors (V-CTM TFTs) using an In–Ga–Zn–O channel and ZnO charge trap layers, in which a solution-processed SiO2 spacer pattern was introduced to scale down the vertical-channel length below 190 nm. The vertical gate-stack structure was implemented by atomic-layer deposition with excellent film conformality. The V-CTM TFTs with channel lengths of 190 (S1) and 140 nm (S2) showed charge-trap-assisted wide memory windows of 12.0 and 10.1 V, respectively. The memory margins between the on- and off-programmed currents were estimated to be 1.2 × 105 and 5.1 × 102 with a program pulse duration of 100 ms for S1 and S2, respectively. The programmed states did not exhibit any degradation with a lapse of retention for 104 s. With reducing the channel length, the number of endurance cycles decreased from 5000 to 3000 cycles. A vertical integration of oxide-based CTM device scaled down to sub-150 nm could be verified to show sound nonvolatile memory operations, even though there remain some technical issues such as a higher level of off-current for S2.

Extraction of Effective Charge Diffusivity in the Charge Trapping Layer of SONOS Flash Memory

Extraction of Effective Charge Diffusivity in the Charge Trapping Layer of SONOS Flash Memory