Trapped Charge Density Research Articles

Endowing smart self-reporting epoxy composites with superior electrical properties from ultralow-content electron-donating encapsulated microsensors

Smart self-reporting dielectrics (SRDs) have been extensively utilized for intelligentizing and miniaturizing next-generation advanced electrical and electronic devices. However, switchable structures towards the self-reporting function commonly damage electrical properties, severely undermining the reliability and practicality of SRDs. Herein, the smart self-reporting function and superior electrical properties are simultaneously achieved by incorporating ultralow content microsensors with electron-donating encapsulation into the epoxy matrix. The microsensor is a leuco dye system for self-reporting temperature anomalies through thermochromism. The strong electron-donating melamine–formaldehyde encapsulation of microsensors serves to confine the switchable structures and enhance electrical properties by constructing the interfacial barrier effect through triboelectrification. Under an ultralow doping content of 0.5 phr, the electrical conductivity of SRDs is considerably reduced by about 80% at the elevated temperature of 80 °C compared to that of the widely recognized epoxy insulation. The reduction efficiency is far superior to those of numerous micro- and nanofillers. The interfacial barrier effect can be supported by the significantly reduced trapped charge density and trap levels in SRDs based on thermal stimulated depolarization current results. Consequently, the charge injection and transport in SRDs can be distinctly inhibited, realizing the enhancement of electrical properties. The results of this study could provide a facile and efficient strategy for achieving high-performance SRDs, which is appealing and vital for widespread applications of SRDs.

Simulation of 1/f charge noise affecting a quantum dot in a Si/SiGe structure

Due to presence of magnetic field gradient needed for coherent spin control, dephasing of single-electron spin qubits in silicon quantum dots is often dominated by 1/f charge noise. We investigate theoretically fluctuations of ground state energy of an electron in gated quantum dot in a realistic Si/SiGe structure. We assume that the charge noise is caused by motion of charges trapped at the semiconductor–oxide interface. We consider a realistic range of trapped charge densities, ρ ∼1010 cm−2, and typical lenghtscales of isotropically distributed displacements of these charges, δr≤ 1 nm, and identify pairs (ρ,δr) for which the amplitude and shape of the noise spectrum are in good agreement with spectra reconstructed in recent experiments on similar structures.

Charge trapping and photovoltaic characteristics in monocrystalline silicon solar cells employing molybdenum oxide and copper oxide stacked hole-selective contacts

A hole-selective contact (HSC) composed of stacked layers of molybdenum oxide (MoOx) and copper oxide (CuOx), called MOCOSL, has been proposed as passivation booster for screen-printed monocrystalline silicon solar cell (SMSC) applications. The passivation quality of MOCOSL is investigated by characterizing its charge trapping properties, including fixed oxide charge (Qf) and interface trap density (Dit). The conversion efficiency (CE) of SMSCs is improved by MOCOSL, resulting in an increase from 20.66% to 21.76%. This improvement is attributed to an increase in the negative Qf and a decrease in Dit, which result in an increase in the open circuit voltage (Voc) and short circuit current (Jsc). Specifically, the number of negative Qf is increased by MOCOSL, which helps to reduce the recombination of charge carriers.

Current collapse suppression in AlGaN/GaN HEMTs using dual-layer SiNx stressor passivation

In this work, a dramatic reduction in current collapse is achieved in GaN-based high-electron-mobility transistors (HEMTs) using dual-layer SiNx stressor passivation (DSSP), and the related mechanism is proposed. The SiNx compression neutralizes the inherent piezo polarization caused by the lattice mismatch at the heterojunction and effectively mitigates the peak electric field crowding at the drain-side gate edge, as supported by technology computer-aided design simulation. Thus, the inverse piezoelectric effect is suppressed and the trapped charge density is reduced under high electrical stress. As a result, the current collapse effect can be significantly restrained. Upon pulsing (Vg = −6 and Vds = 20 V), the device with DSSP exhibits a negligible current collapse (∼3%), which is significantly lower than the baseline device (∼34%). Moreover, it shows a one-order-of-magnitude reduction in gate leakage and a significant enhancement in gate stability. These results prove that the DSSP process is an attractive technique to facilitate high-reliability GaN-on-Si HEMTs.

RETRACTED: Interfacial passivation by Mono-ethanolamine in planar perovskite solar-cell

Aluminium doped zinc oxide (AZO) is a potential replacement for the conventionally used TiO2 as an electron transport layer (ETL) in low-temperature solution processes for hybrid perovskite solar cells (PvSCs). However, the defects and energy-band mismatch at the ETL/perovskite interface accelerate the interfacial carrier's recombination, leading to a decrease in the fill factor (FF) and current density (JSC). To address this issue, a thin interfacial modification layer of monoethanolamine (MEA) has been used which not only reduces the energy barrier between AZO/perovskite for accelerating the charge transfer but also passivates the trap states on the perovskite interface. Due to the synergistic effect of charge extraction promotion and trap density passivation , the champion PvSCs exhibit a higher value of PCE of 8.25 % with a current density (JSC) of 22.59 mA/cm2 and FF of 46.55% compared to the without MEA passivate PvSCs and the device maintains 70% of its topmost PCE after 1000 h under ambient atmosphere, without any encapsulation. This interface engineering based on MEA provides a feasible and excellent strategy to fabricate the PvSCs with improved efficiency and stability of planar device architecture.

Preparation of Remote Plasma Atomic Layer-Deposited HfO2 Thin Films with High Charge Trapping Densities and Their Application in Nonvolatile Memory Devices.

Optimization of equipment structure and process conditions is essential to obtain thin films with the required properties, such as film thickness, trapped charge density, leakage current, and memory characteristics, that ensure reliability of the corresponding device. In this study, we fabricated metal-insulator-semiconductor (MIS) structure capacitors using HfO2 thin films separately deposited by remote plasma (RP) atomic layer deposition (ALD) and direct-plasma (DP) ALD and determined the optimal process temperature by measuring the leakage current and breakdown strength as functions of process temperature. Additionally, we analyzed the effects of the plasma application method on the charge trapping properties of HfO2 thin films and properties of the interface between Si and HfO2. Subsequently, we synthesized charge-trapping memory (CTM) devices utilizing the deposited thin films as charge-trapping layers (CTLs) and evaluated their memory properties. The results indicated excellent memory window characteristics of the RP-HfO2 MIS capacitors compared to those of the DP-HfO2 MIS capacitors. Moreover, the memory characteristics of the RP-HfO2 CTM devices were outstanding as compared to those of the DP-HfO2 CTM devices. In conclusion, the methodology proposed herein can be useful for future implementations of multiple levels of charge-storage nonvolatile memories or synaptic devices that require many states.

Influence of indium doping on electrical performance of gallium oxide thin-film transistors

In the field of oxide semiconductor thin-film transistors (TFTs), the occurrence of charge trapping in the gate dielectric and interfaces presents significant challenges to their operational stability and reliability. In this study, we present high-performing amorphous Ga2O3 TFTs created using atomic layer deposition with varying indium doping concentrations. The channel length (Lch) and channel width (Wch) are 50 and 200 μm, respectively. As the Indium concentration increases from 0% to 60%, the charge trap density (Nit) decreases, resulting in a smaller hysteresis window. The TFTs with a doping concentration of 20% are particularly noteworthy, exhibiting high field-effect mobility (22.6 cm2 V−1 s−1), lower subthreshold swing (160 mV/dec) than amorphous Ga2O3 channel devices, a high on-off current ratio (109), an appropriate threshold voltage (−1 V), and a substantial output current (26 mA/mm at VGS = 16 V).

Realizing improved performance of metal-insulator-semiconductor diodes with high-k MgO/SiOx stack

With the development of metal-insulator-semiconductor (MIS) field-effect transistors, the thickness of silicon dioxide (SiO2) must be scaled down; however, it causes a large gate leakage current and a low on/off current ratio. Magnesium oxide (MgO) exhibits a dielectric constant as high as 11.2, which is about three times larger than that (3.9) of SiO2; thus the thickness of MgO can be three times greater than that of SiO2 and significantly reduces the gate leakage current. Nevertheless, a large lattice mismatch (22.5%) exists between MgO and Si materials. In the study, the MgO/SiOx stack dielectrics are employed to suppress the large lattice mismatch and improve the performance of MIS diodes. The MgO/SiOx stack largely reduces the oxygen vacancy of MgO from 75% to 52.3%; also the fixed oxide charge and interface trap charge density are drastically decreased from 1.3 × 1012 and 1.8 × 1013 to 8.2 × 1011 cm−2 and 7.8 × 1012 cm−2eV−1, respectively. Compared to the MIS diodes with a single MgO, the MgO/SiOx stack dielectrics suppress the gate leakage current by about two orders in MIS diodes; hence the rectification ratio is enhanced from 114 to 1032 at ±2V. Band-diagram shows that Fowler-Nordheim tunneling occurs at a high reverse-bias voltage, and the barrier height increases from 0.18 to 0.42 eV in the MIS diodes with single MgO and MgO/SiOx stack dielectrics, respectively. Nevertheless, the MIS diodes operate through a direct tunneling at low reverse-bias voltages.

Impact of band edge energy on interface traps and electrostatics of ultra-thin-body silicon-on-insulator devices

Besides being impacted by quantum confinement effects, the channel electrostatics of ultra-thin-body silicon-on-insulator (SOI) MOS devices, with channel thicknesses less than 10 nm, are also likely to be impacted by interface trap states. In this work, we comprehensively investigated the effect of band edge energy (surface passivation energy) on the band structure of the silicon channel. We propose to utilize this band edge energy (ΔEedge) to study the effect of interface traps on device electrostatics, which is generally used to passivate the channel/oxide interface. First, by using sp3d5s∗ semi-empirical tight-binding methodology with a fully passivated interface (ΔEedge>5 eV) and by including suitable bandgap correction for different device temperatures, the band structure is obtained, which is solved self-consistently with Poisson’s equation to accurately determine the channel electrostatics, without the effect of trap states. Interface trap states are now seen in the band structure through suitably varying the edge energy (−5eV<ΔEedge<5 eV) based on which the interface trap density (Dit) and the interface trap charge density (Qit) are determined. Through incorporating Qit in the boundary condition for solving Poisson’s equation self-consistently with the band structure, channel electrostatics is recomputed to analyze the effect of traps for a wide range of device conditions. Finally, the degradation in the integrated charge density due to interface traps is accurately modeled for different SOI channel thickness and device temperatures.

Surface-modified polydimethylsiloxane with soft-plasma as dielectric layer for flexible artificial synaptic transistors

The conductance of field-effect transistors (FETs) can be effectively stimulated by electrical or optical pulses, which could be potentially applied as artificial synapses. The combination of solution processable elastomers with polymer semiconductors has attracted extensive interest in all-polymer flexible synaptic electronics, due to the flexible and light weight property. In this work, a glow-discharge soft-plasma is utilized to treat the widely-used elastomer polydimethylsiloxane (PDMS) layer. Subsequently, the surface energy of PDMS is increased, from the contact angle of 100° to fully spread state and induce high charge trapping density (Δn, about 1.9 × 1012 cm−2 under 525 nm green light irradiation and positive gate-bias stress) on the surface. The PDMS surface are homogenously etched by soft plasma without damaging underneath materials, which can be used as dielectric layer in organic FETs. Thus, prepared organic FETs warrant quick charge transfer dynamics between PDMS surface and semiconductor layer. Upon which, flexible synaptic FETs are demonstrated, corresponding synaptic functions like excitatory postsynaptic current (EPSC), paired pulse facilitation (PPF), short-term plasticity (STP) are all realized. Furthermore, the handwritten digits with an accuracy of 86.2% are realized utilizing prepared synaptic devices.

Double-Floating-Gate van der Waals Transistor for High-Precision Synaptic Operations

Two-dimensional materials and their heterostructures have thus far been identified as leading candidates for nanoelectronics owing to the near-atom thickness, superior electrostatic control, and adjustable device architecture. These characteristics are indeed advantageous for neuro-inspired computing hardware where precise programming is strongly required. However, its successful demonstration fully utilizing all of the given benefits remains to be further developed. Herein, we present van der Waals (vdW) integrated synaptic transistors with multistacked floating gates, which are reconfigured upon surface oxidation. When compared with a conventional device structure with a single floating gate, our double-floating-gate (DFG) device exhibits better nonvolatile memory performance, including a large memory window (>100 V), high on-off current ratio (∼107), relatively long retention time (>5000 s), and satisfactory cyclic endurance (>500 cycles), all of which can be attributed to its increased charge-storage capacity and spatial redistribution. This facilitates highly effective modulation of trapped charge density with a large dynamic range. Consequently, the DFG transistor exhibits an improved weight update profile in long-term potentiation/depression synaptic behavior for nearly ideal classification accuracies of up to 96.12% (MNIST) and 81.68% (Fashion-MNIST). Our work adds a powerful option to vdW-bonded device structures for highly efficient neuromorphic computing.

High-pressure H2O post-annealing for improving reliability of LTPS and a-IGZO thin-film transistors within a coplanar structure

Improving reliability of low-temperature polycrystalline silicon (LTPS) and amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs), components of low-temperature polycrystalline silicon and oxide (LTPO), is crucial for fabricating high-performance and high-stability LTPS and oxide semiconductor-based electronics and display products. However, improving the reliability of these TFTs simultaneously in a uniform and effective manner within a coplanar structure is challenging. In this work, high-pressure H2O post-annealing (H2O HPPA) as a post-treatment for LTPS and a-IGZO TFTs within a coplanar structure are proposed to improve the uniformity and stability of the electrical characteristics simultaneously. It was demonstrated that oxygen and hydrogen in the HPPA-passivated defect state at the channel/gate dielectric layer interfaces and bulk gate dielectric layers of LTPS and a-IGZO TFTs considerably improve the uniformity and stability of the electrical performance and morphologies of the interfaces. Thus, the distribution of electrical characteristics (mobility, threshold voltage, and subthreshold swing) in LTPS and a-IGZO TFTs was reduced by more than 2-fold, and the trap charge densities at their interfaces and bulk gate dielectric layers were reduced by approximately 1.6-fold. Furthermore, the threshold voltage shift was decreased in both LTPS and a-IGZO-TFTs fabricated with H2O HPPA under negative and positive bias temperature stresses, respectively. The proposed H2O HPPA method can effectively facilitate the industry-level application of LTPS and oxide semiconductor-based electronics and display electronics.

Charge trapping effects in nonvolatile memory cells with HfO2/Al2O3 nanolaminated trapping layer

The charge trapping effects in memory cells with HfO2/Al2O3 nanolaminated stacks with two different thicknesses (2.4 and 3.5 nm) of the tunnel SiO2 layer were investigated. The HfO2/Al2O3 stacks were fabricated by atomic layer deposition and received post deposition annealing in O2. The structures with 3.5 nm tunnel oxide were found to provide higher density of trapped charges. The obtained trapped negative charge density is -3.56×10−6 C/cm2 and the positive one is 4.03×10−6 C/cm2. It is demonstrated that the electron trapping is significantly influenced by the amount of available electrons in the inversion layer. Under illumination, pulses with duration of 1 ms could provide trapped negative charge density equal to ~60% the value obtained at 10 s duration, where a saturation of the trapped charge is found. The hole trapping is not influenced by the illumination of capacitors and it is found to be slower than the electron one. Some aspects of the trapping process as well as some of the peculiarities in the capacitance-voltage curves obtained in the course of the measurements are briefly discussed.

All region analytical modeling of 2-D transition metal dichalcogenide FET by considering effect of fringing field and region-wise mobility

In this paper, for the first time an analytical all region model of Transition metal dichalcogenide based FET has been developed to represent the current–voltage characteristics of the device in ultra-short channel regime. Starting from Gauss’s law, Poisson’s equation is formulated and short channel subthreshold current model is developed subsequently. In order to include fringing field effect, the gaussian box is considered for top and bottom oxides along with channel. Next, Velocity saturation model is developed by considering mobile charges due to top-bottom gates and region-wise field dependent mobility in the channel utilizing the drift diffusion approach. Both the models are then unified by finding the natural points of transition from one model to other. The intraband source to drain tunneling has also been incorporated to develop generalized 2-D material based FET model. Veracity of the model has been verified with NEGF simulations for different device parameters and excellent congruence is observed. The effect of the interface trap charge density has also been included in the model and its effects on the transfer characteristics are investigated. • Analytical modeling of I-V characteristics for TMD materials applicable for all channel lengths. • Validation of model with atomistic simulator data for Sub 10 nm channel length. • Effects of double gate and fringing field have been included. • Source to drain tunneling has been included to increase model applicability for any 2D materials.

Surface trap characteristics of polyimide and effect of surface charge accumulation on surface flashover

Charge accumulation on the surface of insulation dielectric used in high voltage DC equipment is one of the important causes of surface flashover. Surface charge accumulation is closely related to surface trap characteristics. In this paper, the surface trap energy level distribution of polyimide (PI) was calculated and analyzed by the corona charging method and surface potential decay method. Besides, electron and hole trap characteristics were studied by changing the polarity and amplitude of the charging voltage. Furthermore, the influence of surface charge polarity and quantity on the flashover voltage was researched. Experimental results indicate that the energy level of traps corresponding to the maximum trapped charge density ranges around 0.94 eV. In addition, the energy level of the hole trap is slightly higher than that of the electron trap. The maximum charge density captured by the electron trap and hole trap is about 1.17 × 1021 and 1.03 × 1021 eV−1 m−3, respectively. The polarity of the surface charge can influence the conductivity characteristics of PI, the surface heterocharge reduces the volume conductivity by about 80% while the surface homocharge improves the volume conductivity of PI by about 6.4 times. Besides, both negative and positive surface charges can improve surface conductivity. The polarity of surface charge influences the flashover characteristics of PI, the flashover voltage increases by about 37.8% with the increase of homocharge density and decreases by about 23.8% with the increase of heterocharge density, which is related to the change of electric field near the cathode caused by surface charge accumulation.

Nanoscale Mapping of Carrier Mobilities in the Ballistic Transports of Carbon Nanotube Networks.

Much progress has been made in the nanoscale analysis of nanostructures, while the mapping of key charge transport properties such as a carrier mobility remains a challenge, especially for one-dimensional systems. Here, we report the nanoscale mapping of carrier mobilities in carbon nanotube (CNT) networks and show that charge transport behaviors varied depending on network structures. In this work, the spatial distribution of localized charge transport properties such as mobilities and charge trap densities in CNT networks were mapped via a scanning noise microscopy. The mobility map was obtained from the conductivity maps measured at different back-gate biases, showing up to two orders of mobility variations depending on localized network structures. Furthermore, from the maps, correlations between mobility/conductivity and charge trap density were analyzed to determine charge transport mechanisms. In metallic CNT networks, the regions with rather high (low) or low (high) charge trap densities (mobilities) exhibited a diffusive or ballistic transport behavior, respectively. Interestingly, semiconducting CNT networks also exhibited a gradual transition from a diffusive to a ballistic transport behavior as the CNT mobility was increased by reaching the on-state with negative gate biases. The mapping of the cross-patterned CNT network showed that metallic CNT electrodes could achieve a good electrical contact with semiconducting CNTs without high contact resistance regions. Since this method allowed one to map versatile charge transport properties such as mobility, conductivity, and charge trap density, it can be a powerful tool for basic research about charge transport phenomena and practical device applications.

Charge Transport Capabilities of Dibenzo[n]phenacenes (n = 5–7): Influence of Trap States and Molecular Packing

A high carrier transport capability with strong π–π interactions is expected to result from the extension of π conjugation in small molecules. This is an important factor to create promising molecules, leading to the development of high-performance and new applications in organic electronic devices. We systematically demonstrate the charge transport capability and trap density of states in dibenzo[n]phenacenes (DBnPs) (n = 5–7) with a hybrid π structure between the phenacene and acene cores. A DB6P field-effect transistor (FET) achieves a relatively high-field-effect mobility beyond 2 cm2 V–1 s–1, which indicates excellent FET performance in comparison with DB5P and DB7P. The calculated charge-transfer integrals based on the crystal structure and the distribution of the trap density of states confirm the superior transport capability and FET properties in DB6P. We demonstrate that molecules with C2h symmetry result in high crystallinity and close packing in crystals, leading to high-performance FETs.

Electrical characteristics of normally off hydrogen-terminated diamond field effect transistors with lanthanum oxide gate dielectric

A normally off hydrogen-terminated diamond (H-diamond) metal-oxide-semiconductor field effect transistor (MOSFET) is realized by using lanthanum oxide (La2O3) gate dielectric. The threshold voltage is demonstrated to be −0.797 V, indicating that the La2O3-gated H-diamond MOSFET has normally off characteristics. The normally off mode could be greatly ascribed to the low work function of La2O3. Based on the capacitance–voltage (C–V) curves, the dielectric constant of La2O3 is calculated to be as high as 25.6. Moreover, the small hysteresis voltage extracted from the C–V curves exhibits low trapped charge density in the La2O3 layer. The maximum drain–source current, maximum transconductance, subthreshold swing, effective mobility, current on/off ratio, and sheet hole density of La2O3-gated MOSFET with a gate length of 2 μm are calculated to be −13.55 mA/mm, 4.37 mS/mm, 161 mV/dec, 202.2 cm2/V·s, 108, and 6.53 × 1012 cm−2, respectively. This work will significantly promote the development of normally off H-diamond MOSFET devices.

Effects of electron- and hole-current hysteresis on trap characterization in organo-inorganic halide perovskite

Charge trap density and carrier mobility of perovskite materials are the critical properties of perovskite solar cells. The space charge limited current (SCLC) method, which measures a dark current–voltage (I-V) curve of a single-carrier device has found extensive use for studying the trap density and charge carrier mobility in perovskite materials. Herein, it was found that the electron- and hole-current in organo-lead perovskite-based single-carrier device undergoes significant hysteresis under forward and reverse scanning due to the mobile ions. In addition, it was also observed that measuring history has a detrimental effect on hysteresis resulting in possible overestimation or underestimation of the extracted electrical values from the SCLC measurement. In the forward/reverse scanning process, the mobile ionic defects enhance/shield the charge in the traps due to ionic charging/discharging, thereby increasing/reducing the interface barrier and net charge in the I-V scanning, which in turn affects the determination of transport properties of the carrier. These results raise quite a few doubts over the direct application of classical SCLC measurements for the accurate characterization of intrinsic transport properties of the mixed ionic-electronic perovskite.

Stable Hole-Transporting Material-Free Perovskite Solar Cells with Efficiency Exceeding 14% via the Introduction of a Malonic Acid Additive for a Perovskite Precursor

Hole transport material-free perovskite solar cells (HF-PSCs) offer low-cost photovoltaic devices. For development and commercialization, they are more attractive than the expensive HTL-contained perovskite solar cells. Herein, we focused on enhancing the stability and efficiency of HF-PSCs with the malonic acid (MA) addition to the methylammonium lead iodide. The introduced additive increases the perovskite crystallinity and assembles a perovskite layer with larger grains along with fewer surface defects. In addition, the MA-modified HF-PSCs show suppressed charge recombination within devices, and a lower charge trap density has been obtained for them. A considerable power conversion efficiency of 14.14% is achieved for MA-modified HF-PSCs, higher than the performance of 11.88% for the untreated HF-PSCs. Finally, MA-based HF-PSCs show higher shelf stability than the control HF-PSCs. It is because the MA-modified perovskite layer with passivated grain boundaries is better at repelling water.