Charge Transfer Sense Amplifier Research Articles

Low Power Reduction Techniques Implementation and Analysis in Sense Amplifier Circuit Configurations

MTCMOS (Multi-Threshold CMOS), sleepy stack, sleepy keeper, and footer stack are examples of low power saving techniques incorporated into the core gpdk 90nm technology papers used in the proposed study using Cadence. The main focus of these tests is the power consumption of various sense amplifier circuits. The simulation results show that the charge-transfer sense amplifier uses much less energy than voltage and current sense amplifiers. The present mode detecting amplifier’s power consumption can be decreased by up to 98 percent by using MTCMOS technology.

IoT Applications: Analysis of MTCMOS Cache Memory Architecture in a Processor

The main goals of the suggested inquiry are to measure how much power an amplifier uses, determine how much leaks through SRAM, and use the data. The main issue with the cache memory's design was leakage power. The charge transfer sense amplifier had the lowest value compared to other sense amplifiers' power consumption figures, even though we used MTCMOS and Footer Stack to reduce leaky power. The design included MTCMOS-CTSA and MTCMOS-SRAM memory to reduce power consumption. Fusing CTSA and SRAM with MTCMOS technology can produce low-power cache memory. This cache memory uses a lot less power than CTSA and SRAM devices

A Review of Sense Amplifiers for Static Random Access Memory

Sense amplifier (SA) is being viewed as one of the most critical circuits in the periphery of high-speed, low-power-embedded static random access memory (SRAMs). This paper provides a systematic overview of voltage-mode, charge-transfer, current-mode SAs, and calibration-based SAs for SRAM. Recent advances in developing SAs have paved the way for lower delay, lower energy, and higher reliability. For comparison, all SAs based on 65 nm CMOS technology are simulated under different power supplies, bit-line capacitances, and various process corners. When the bit-line capacitance is 50 fF, charge-transfer and current-mode SAs are about 40% faster than voltage-mode SAs, and the energy consumption of charge-transfer SA is 30% lower than that of other voltage-mode SAs. Delay and energy of HCI-trimming SA and multi-sized SA are about equal to that of voltage-mode SAs. Because of low bit-line precharged voltage, the energy of charge-limited sequential SA (CLSSA) is 64% lower than that of charge-transfer SA, while the delay of CLSSA is five times larger than the other SAs.

A low leakage 500 MHz 2T embedded dynamic memory with integrated semi-transparent refresh

This paper presents a low-leakage 128kbit dynamic memory based on a 2T dynamic cell. The design is implemented in a logic 90nm technology and achieves a low static power consumption of 130μW and an access time of 2ns. It has a worst case retention time of 175μs. This performance is achieved by introducing an optimised hierarchical organisation and peripheral circuits for the read, the write and the refresh operations. A novel writing mechanism for 2T cells using a double phase approach is demonstrated. The area penalty of using short read bitlines is alleviated using a charge transfer sense amplifier (SA). A novel local write sense amplifier (WSA) that can operate as a latch makes it possible to perform the refresh operation at the local level, improving the energy efficiency of the refresh operation.The memory includes an integrated automatic refresh mechanism. Most read and write operations can still be performed during refresh cycles. In cases where the accessed address conflicts with the refresh operation, the memory handles access recovery internally.

High-speed charge transfer sense amplifier for 0.5 V DRAM array applications

A new high-speed charge transfer sense amplifier scheme is proposed for 0.5 V DRAM array applications. The combination of both the cross-coupled structure and the boosting capacitance used in the proposed sense amplifier leads to a maximum voltage difference between sense nodes. Based on post-layout simulations, the charge transfer speed and the voltage difference after charge transfer are improved 40.7% and 59.29%, respectively, over the prior art circuits. The power-delay product is then enhanced 38.26%. Besides, both high voltage pre-charge levels and high voltage control signals are not required in this proposed circuit as compared with prior arts.

A giant chip multigate transistor ROM circuit design

Defect-tolerant techniques based on memory-cell duplication with address dispersion, fail-safe operation, and defect-tolerable combination decoding were developed to improve the fabrication yield of a large-chip-size mask-programmable read-only memory (ROM). These techniques have features of automatic inspection, detection, and selection. A multigate transistor ROM (MUGROM) cell and a high-sensitivity charge-transfer sense amplifier appropriate to this MUGROM have been developed which achieve high packing density and low power dissipation. Using these techniques and n-well CMOS technology, a 4-Mb ROM with an internal I/O port on a 34/spl times/21-mm/SUP 2/ size chip has been realized. It enables the ROM to be connected to the microprocessor data bus without peripheral interface LSI. The I/O port was designed to have two READ modes: a block data access mode for reading continuous data up to 1-kbit with fast cycle time, and a random access mode. Operating under a 1-MHz block data READ cycle, the device has a typical power dissipation of 20 mW with an access time of 7 /spl mu/s.

Cross-coupled charge-transfer sense amplifier and latch sense scheme for high-density FET memories: K. S. Gray IBM J. Res. Devel. 24(3), 283 (1980)

Cross-coupled charge-transfer sense amplifier and latch sense scheme for high-density FET memories: K. S. Gray IBM J. Res. Devel. 24(3), 283 (1980)

Cross-Coupled Charge-Transfer Sense Amplifier and Latch Sense Scheme for High-Density FET Memories

This paper describes a sense scheme for use on high-density one-device cell field effect transistor random access memories (FET RAMs). The high-sensitivity threshold-independent cross-coupled charge-transfer sense amplifier and latch is used. The IBM 64K-bit one-device dynamic memory cell FET RAM chip design is used as the vehicle for the discussion. Adaptations made on the sense amplifier and latch for use with the sense scheme are discussed. Also described are 1) dummy cell design, 2) subthreshold leakage considerations, 3) single-ended input/output (I/O) circuitry sensing and ramifications, 4) multiple cycle signal degradations, and 5) a maximum supply voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</inf> ) buffer circuit sense scheme improvement.

High sensitivity charge-transfer sense amplifier

A balanced charge-transfer sense amplifier for one-device cell memory arrays is presented. Charge-transfer techniques are used to preamplify the sense signal and to isolate the large bit/sense (B/S) line capacitance from the nodes of a dynamic latch. The high sensitivity of the sense-refresh amplifier is demonstrated in an experimental memory array with a B/S line to ell storage node capacitance ratio of 40 and a sense signal of about 61 mV. Performance limitations are also discussed.