A low leakage 500 MHz 2T embedded dynamic memory with integrated semi-transparent refresh

Abstract

This paper presents a low-leakage 128kbit dynamic memory based on a 2T dynamic cell. The design is implemented in a logic 90nm technology and achieves a low static power consumption of 130μW and an access time of 2ns. It has a worst case retention time of 175μs. This performance is achieved by introducing an optimised hierarchical organisation and peripheral circuits for the read, the write and the refresh operations. A novel writing mechanism for 2T cells using a double phase approach is demonstrated. The area penalty of using short read bitlines is alleviated using a charge transfer sense amplifier (SA). A novel local write sense amplifier (WSA) that can operate as a latch makes it possible to perform the refresh operation at the local level, improving the energy efficiency of the refresh operation.The memory includes an integrated automatic refresh mechanism. Most read and write operations can still be performed during refresh cycles. In cases where the accessed address conflicts with the refresh operation, the memory handles access recovery internally.