Low voltage sensing techniques and secondary design issues for sub-90nm caches

Abstract

CMOS technology and architecture trends are causing the speed of VLSI systems to be increasingly limited by the large capacitance of cache bit-lines and interconnect. Despite reduced supply voltages, low-voltage sensing techniques are needed to avoid the time constants associated with large voltage swings on increasingly large capacitance. This paper describes two sensing techniques to overcome this problem: a current sense amplifier and a charge transfer sense amplifier and their implementation based on 90nm CMOS technology. The current sense amplifier senses the cell current directly and shows a speed improvement of 10-12% for 128 memory cells and 15-17% for 256 memory cells as compared to the conventional voltage mode sense amplifier, for iso-noise. The other technique is the charge transfer sense amplifier that takes advantage of large bit-line capacitance for its operation. CTSA shows an improvement of 12-15% less energy that the voltage mode sense amplifier. The energy consumed by bit-lines charging and discharging in CTSA is 30% less than the voltage mode sensing scheme.