High-performance and low-voltage sense-amplifier techniques for sub-90nm SRAM

Abstract

Large bit-line capacitance is one of the main bottlenecks to the performance of on-chip caches. New sense amplifier techniques need to explicitly address this challenge. This paper describes two sensing techniques to overcome this problem: a current sense amplifier (CSA) and a charge transfer sense amplifier (CTSA) and their implementation based on 90 nm CMOS technology. The current sense amplifier senses the cell current directly and shows a speed improvement of 17-20% for 128 memory cells as compared to the conventional voltage mode sense amplifier, for the same energy. The other is a charge transfer sense amplifier that takes advantage of large bit-line capacitance for its operation. The CTSA shows an improvement of 18-22% for read delay for 128 memory cells and consumes 15-18% less energy than the voltage mode sense amplifier. The CTSA results in reduced bit-line swing, which in turn leads to 30% lower bit-line energy than the conventional voltage mode.