A giant chip multigate transistor ROM circuit design

Abstract

Defect-tolerant techniques based on memory-cell duplication with address dispersion, fail-safe operation, and defect-tolerable combination decoding were developed to improve the fabrication yield of a large-chip-size mask-programmable read-only memory (ROM). These techniques have features of automatic inspection, detection, and selection. A multigate transistor ROM (MUGROM) cell and a high-sensitivity charge-transfer sense amplifier appropriate to this MUGROM have been developed which achieve high packing density and low power dissipation. Using these techniques and n-well CMOS technology, a 4-Mb ROM with an internal I/O port on a 34/spl times/21-mm/SUP 2/ size chip has been realized. It enables the ROM to be connected to the microprocessor data bus without peripheral interface LSI. The I/O port was designed to have two READ modes: a block data access mode for reading continuous data up to 1-kbit with fast cycle time, and a random access mode. Operating under a 1-MHz block data READ cycle, the device has a typical power dissipation of 20 mW with an access time of 7 /spl mu/s.