Charge Storage Medium Research Articles

Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire

A gate-all-around polycrystalline silicon nanowire (NW) floating-gate (FG) memory device was fabricated and characterized in this work. The cross-section of the NW channels was intentionally made to be triangular in shape in order to study the effects of the corners on the device operation. Our results indicate that the channel corners are effective in lowering the programming and erasing (P/E) operation voltages. As compared with the charge-trapping type devices, a larger memory window is obtained with the FG scheme under low-voltage P/E conditions. A model considering the nature of the charge storage medium is proposed to explain the above findings.

A multiscale modeling study of loss processes in block-copolymer-based solar cell nanodevices

Flexible photovoltaic devices possess promising perspectives in opto-electronic technologies, where high mobility and/or large-scale applicability are important. However, their usefulness in such applications is currently still limited due to the low level of optimization of their performance and durability. For the improvement of these properties, a better understanding and control of small-scale annihilation phenomena involved in the photovoltaic process, such as exciton loss and charge carrier loss, is necessary, which typically implicates multiple length- and time-scales. Here, we study the causes for their occurrence on the example of nanostructured diblock- and triblock-copolymer systems by making use of a novel solar-cell simulation algorithm and explore new routes to optimize their photovoltaic properties. A particular focus is set on the investigation of exciton and charge carrier loss phenomena and their dependence on the inter-monomeric interaction strength, chain architecture, and external mechanical loading. Our simulation results reveal that in the regime from low up to intermediate χ-parameters an increasing number of continuous percolation paths is created. In this parameter range, the internal quantum efficiency (IQE) increases up to a maximum, characterized by a minimum in the number of charge losses due to charge recombination. In the regime of high χ-parameters both block-copolymer systems form nanostructures with a large number of bottlenecks and dead ends. These lead to a large number of charge losses due to charge recombination, charge trapping, and a deteriorated exciton dissociation, resulting in a significant drop in the IQE. Moreover, we find that the photovoltaic performance of the triblock-copolymer material decreases with increasing mechanical loading, caused by a growing number of charge losses due to charge recombination and charge accumulation. Finally, we demonstrate that the process of charge trapping in defects can be reversed by changing the polarity of the electrodes, which confers these materials the ability to be used as charge storage media.

Novel Zn-Doped ${\rm Al}_{2}{\rm O}_{3}$ Charge Storage Medium for Light-Erasable In–Ga–Zn–O TFT Memory

A novel Zn-doped Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (ZAO) layer prepared by atomic layer deposition (ALD) is used as the charge storage medium in an In-Ga-Zn-O thin-film-transistor memory. The gate insulating stack of Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /ZAO/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> is assembled in a single ALD step, and is found to possess a high electron storage capacity due to very deep defect levels. The memory device shows a threshold voltage shift as large as 6.38 V after a +15V/1 ms programming pulse, and quite good charge retention. Once programmed, the memory can be only light erased. The underlying mechanisms are discussed with the assistance of density functional theory calculations.

Formation of CoSi2/CoSixNy Nanocrystals for Nonvolatile Memory Application

Nonvolatile nanocrystal memories recently have been one of the promising candidates to replace traditional floating gate nonvolatile memory because the discrete nanocrystal as the charge storage media have effectively improved data retention under endurance test for the device scaling down. In this study, CoSi2 nanocrystal surrounded with CoSixNy shell structure was proposed by rapid thermal annealing a nitrogen incorporated CoSi layer, which was deposited by sputtering CoSi target in the mixture gas of Ar+N2 or Ar+NH3, to improve data retention. The structures and elements composition of nanocrystal were analyzed by transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS), and the electrical characteristics of nanocrystals memories were defined by C-V curves. Because of the extra CoSixNy shell, the proposed memory can exhibit good data retention to 10 years.

Read Characteristics of Independent Double-Gate Poly-Si Nanowire SONOS Devices

This paper investigates the read operation of poly-Si nanowire silicon-oxide-nitride-oxide-silicon devices with independent double-gate (IDG) configuration. The device features oxide-nitride-oxide (ONO) stack as the charge storage medium in one of the two gated sides with pure oxide in the other. Owing to the IDG feature, the shift in the device's transfer characteristics due to a change in the amount of storage charges can be sensed with two different modes, which have one of the two gates applied with a sweeping bias (driving gate) and the other with a fixed bias (control gate). Our analysis and experimental data show that a larger memory window is obtained when the gate of the ONO side is used as the driving gate. Moreover, the memory window of this mode is essentially independent of the bias applied to the control gate. Based on this finding, a novel Flash structure featuring IDG cells with a common control gate is proposed.

Amorphous Oxide Semiconductor Memory Using High-k Charge Trap Layer

Amorphous oxide semiconductor memory devices with HfInZnOx as the channel layer and high k dielectric stacks as the charge storage medium were fabricated. HfO2 and Al2O3 and HfAlOx films were examined as the charge trap layers. The drain current - gate voltage transfer curves of the fabricated charge trap memories show a large hysteresis due to the electron trapping and de-trapping at the interfaces between the high-k charge storage layer and the SiO2. The device structure and operational scheme for the amorphous oxide semiconductor charge trap memories were suggested based on these properties.

Memory effect of a single-walled carbon nanotube on nitride-oxide structure under various bias conditions

We report on the memory effect of single-walled carbon nanotubes (SWNTs) placed on a nitride-oxide layer structure designed as a charge storage medium. The conductance of the SWNT was modulated by the injected charge in the nitride-oxide interface and the polarities of injected charges were then detected. A large on/off-state current ratio (&amp;gt;104) was obtained at a small program/erase voltage range (&amp;lt;3 V). We also studied the effect of a half-selected cell on the conductance of the SWNTs to identify the issues with cross-point memory architecture.

Transparent indium gallium zinc oxide transistor based floating gate memory with platinum nanoparticles in the gate dielectric

A transparent memory device has been developed based on an indium gallium zinc oxide thin film transistor by incorporating platinum nanoparticles in the gate dielectric stack as the charge storage medium. The transfer characteristics of the device show a large clockwise hysteresis due to electron trapping and are attributed to the platinum nanoparticles. Effect of the gate bias stress (program voltage) magnitude, duration, and polarity on the memory window characteristics has been studied. Charge retention measurements were carried out and a loss of less than 25% of the trapped elec-trons was observed over 104 s indicating promising application as nonvolatile memory.

Ferroelectric Transistors with Nanowire Channel: Toward Nonvolatile Memory Applications

We report the fabrication and characterization of ZnO nanowire memory devices using a ferroelectric Pb(Zr(0.3)Ti(0.7))O(3) (PZT) film as the gate dielectric and the charge storage medium. With a comparison to nanowire transistors based on SiO(2) gate oxide, the devices were evaluated in terms of their electric transport, retention, and endurance performance. Memory effects are observed as characterized by an eminent counterclockwise loop in I-V(g) curves, which is attributed to the switchable remnant polarization of PZT. The single-nanowire device exhibits a high (up to 10(3)) on/off ratio at zero gate voltage. Our results give a proof-of-principle demonstration of the memory application based on a combination of nanowires (as channels) and ferroelectric films (as gate oxide).

Ge[sub 2]Sb[sub 2]Te[sub 5] Charge Trapping Nanoislands with High-k Blocking Oxides for Charge Trap Memory

Charge trap memory capacitors using (GST) nanoislands as charge storage media were fabricated. The GST nanoislands were prepared by plasma-enhanced cyclic chemical vapor deposition on a 6 nm thick tunneling layer. A 16 nm thick or 40 nm thick film was used as the blocking oxide (BO). A shift in the flatband voltage in the capacitance–voltage test was achieved when the GST nanoislands were interposed between the and BOs, highlighting the feasibility of memory applications. The charges were trapped at the interface between the GST and BOs. Stable charge retention up to was observed.

Organic thin-film transistor memory with gold nanocrystals embedded in polyimide gate dielectric

An all-organic memory device based on a copper phthalocyanine (CuPc) thin-film transistor (TFT) using gold nanocrystals embedded in a polyimide gate dielectric is demonstrated. Both the gate dielectric and the active semiconductor layer are organic materials. Discrete gold nanocrystals are adopted as the charge storage medium. Under proper gate bias, gold nanocrystals are charged and discharged, resulting in the modulation of the channel conductance. Current–voltage (I–V) measurements at room temperature show the memory behaviour of the fabricated devices. The detailed programming and erasing operations are discussed. Low fabrication temperature and low cost are two benefits of the fabricated memory devices, which could provide a low-cost solution for the all organic circuits.

Silicon nanowire on oxide/nitride/oxide for memory application

We report the fabrication and characterization of Si nanowire memory devices withoxide/nitride/oxide stacked layers as the gate dielectrics and charge storage media. Thedevices were fabricated by using photolithography to pattern the metal contacts to the Sinanowires grown on pre-defined locations. A large memory window with high on/off-statecurrent ratio due to the small radius and intrinsic doping of the Si nanowire is obtained. Inaddition, the simple reversible write/read/erase operations have been implemented withthese memory devices. The dynamics of the nanowire/nitride charge exchange and itseffect on the threshold voltage and memory retention have been investigated.

NON-VOLATILE HIGH SPEED &amp; LOW POWER CHARGE TRAPPING DEVICES

We report the operational characteristics of ultra-small-scaled SONOS (below 50 nm gate width and length) and SiO 2/ SiO 2 structural devices with 0.5 um gate width and length where trapping occurs in a very narrow region. The experimental work summarizes the memory characteristics of retention time, endurance cycles, and speed in SONOS and SiO 2/ SiO 2 structures. Silicon nitride has many defects to hold electrons as charge storage media in SONOS memory. Defects are also incorporated during growth and deposition in device processing. Our experiments show that the interface between two oxides, one grown and one deposited, provides a remarkable media for electron storage with a smaller gate stack and thus lower operating voltage. The exponential dependence of the time on the voltage is reflected in the characteristic energy. It is ~0.44 eV for the write process and ~0.47 eV for the erase process in SiO 2/ SiO 2 structural device which is somewhat more efficient than those of SONOS structure memory.

Memory effect in thin films of insulating polymer andC60 nanocomposites

We describe the use of C60 fullerene molecules as the charge storage medium in an insulating poly-vinyl-phenol (PVP)polymer. The simple metal–organic–metal (MOM) sandwich structure devices depositedfrom solution exhibit distinct high and low conduction states, which can be used toprogram read, write and erase memory operations. The charge transfer and retention inC60 molecules at room temperature has been confirmed by capacitance–voltage and Ramanspectroscopy measurements. Conducting atomic force microscopy has been used todemonstrate that high and low conductance states persist even at the nanoscale.

Oxygen Transport and Charge Storage in Calcium Orthovanadate

Electrolytic effects, crystal coloration, and charge storage observed when an electric field is applied to single crystals of calcium orthovanadate at temperatures above 700 °C are shown to be associated with oxygen migration and the creation of V4+ centers in the crystal. The oxygen transport number is shown to be constant at 0.9 over the temperature range 650°–900°C with an activation energy for predominantly ionic conduction of 1.05 ± 0.05 eV. The amount of recoverable charge stored in the crystal depends on the sample used and also on the charging current, but is about 15% for an average crystal with a charging current density of several milliamperes/square centimeter. The open‐circuit voltage is of the order of several volts. Deterioration of the bulk material during electrolysis and barrier effects appear to be the major limitation on the use of the material as a charge storage medium.