NON-VOLATILE HIGH SPEED & LOW POWER CHARGE TRAPPING DEVICES

Abstract

We report the operational characteristics of ultra-small-scaled SONOS (below 50 nm gate width and length) and SiO 2/ SiO 2 structural devices with 0.5 um gate width and length where trapping occurs in a very narrow region. The experimental work summarizes the memory characteristics of retention time, endurance cycles, and speed in SONOS and SiO 2/ SiO 2 structures. Silicon nitride has many defects to hold electrons as charge storage media in SONOS memory. Defects are also incorporated during growth and deposition in device processing. Our experiments show that the interface between two oxides, one grown and one deposited, provides a remarkable media for electron storage with a smaller gate stack and thus lower operating voltage. The exponential dependence of the time on the voltage is reflected in the characteristic energy. It is ~0.44 eV for the write process and ~0.47 eV for the erase process in SiO 2/ SiO 2 structural device which is somewhat more efficient than those of SONOS structure memory.