Charge Pump Circuit Research Articles

Reduced-Ripple p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Charge Pump Circuit with Small Filtering Capacitance

This paper presents a two-stage, two-phase, p-channel metal–oxide–semiconductor field-effect transistor (PMOSFET) charge pump with special two-step clocks for ripple reduction. The ripple voltage can be reduced by adjusting the overdrive voltage during charge transfer. The charge pump including the circuit of the proposed clocks and 5 pF boosting capacitance was fabricated using 0.35 µm complementary metal–oxide–semiconductor field-effect transistor (CMOSFET) technology in an area of 0.182 mm2. With the new clock scheme, high voltage gain and driving capacity without overstress of the transistors are preserved. The experimental results reveal that the output voltage ripple is reduced from 23.2 to 12.8 mV for an output current of 36 µA at a frequency of 10 MHz and a supply voltage of 1.8 V, which indicates a 45% ripple reduction without increasing filtering capacitance.

Wireless Front-End With Power Management for an Implantable Cardiac Microstimulator

Inductive coupling is presented with the help of a high-efficiency Class-E power amplifier for an implantable cardiac microstimulator. The external coil inductively transmits power and data with a carrier frequency of 256 kHz into the internal coil of electronic devices inside the body. The detected cardiac signal is fed back to the external device with the same pair of coils to save on space in the telemetry device. To maintain the power reliability of the microstimulator for long-term use, two small rechargeable batteries are employed to supply voltage to the internal circuits. The power management unit, which includes radio frequency front-end circuits with battery charging and detection functions, is used for the supply control. For cardiac stimulation, a high-efficiency charge pump is also proposed in the present paper to generate a stimulated voltage of 3.2 V under a 1 V supply voltage. A phase-locked-loop (PLL)-based phase shift keying demodulator is implemented to efficiently extract the data and clock from an inductive AC signal. The circuits, with an area of 0.45 mm², are implemented in a TSMC 0.35 μm 2P4M standard CMOS process. Measurement results reveal that power can be extracted from the inductive coupling and stored in rechargeable batteries, which are controlled by the power management unit, when one of the batteries is drained. Moreover, the data and clock can be precisely recovered from the coil coupling, and a stimulated voltage of 3.2 V can be readily generated by the proposed charge-pump circuits to stimulate cardiac tissues.

Design of a programmable CMOS Charge-Pump for phase-locked loop synthesizers

A charge pump circuit capable of operating at different switching speed is presented. The switching speed control is added to a typical charge pump circuit by mean of enable switches which allow drive different currents. Charge pump circuit is implemented in AMI 0.5μm CMOS technology. Simulations were performed using Spectre from CadenceTM. Simulation results show clearly an increase in the slope of charging or discharging curves of load capacitor during the pumping-up and pumping-down phases.

Sunlight-variation-adaptive charge pump circuit with self-reconfiguration for small-scale solar energy harvesting

Sunlight-variation-adaptive charge pump circuit with self-reconfiguration for small-scale solar energy harvesting

An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme

In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18µm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.

A CMOS Energy Harvesting and Imaging (EHI) Active Pixel Sensor (APS) Imager for Retinal Prosthesis

A CMOS image sensor capable of imaging and energy harvesting on same focal plane is presented for retinal prosthesis. The energy harvesting and imaging (EHI) active pixel sensor (APS) imager was designed, fabricated, and tested in a standard 0.5 μm CMOS process. It has 54 × 50 array of 21 × 21 μm(2) EHI pixels, 10-bit supply boosted (SB) SAR ADC, and charge pump circuits consuming only 14.25 μW from 1.2 V and running at 7.4 frames per second. The supply boosting technique (SBT) is used in an analog signal chain of the EHI imager. Harvested solar energy on focal plane is stored on an off-chip capacitor with the help of a charge pump circuit with better than 70% efficiency. Energy harvesting efficiency of the EHI pixel was measured at different light levels. It was 9.4% while producing 0.41 V open circuit voltage. The EHI imager delivers 3.35 μW of power was delivered to a resistive load at maximum power point operation. The measured pixel array figure of merit (FoM) was 1.32 pW/frame/pixel while imager figure of merit (iFoM) including whole chip power consumption was 696 fJ/pixel/code for the EHI imager.

High-Efficiency CTS Charge Pump Using Three-Level Addressing Method

This paper proposes a new addressing method for high-efficiency switching-capacitor DC-DC voltage converter based on combination of CTS (charge-transfer-switch) charge pump and cross-coupled output stage is proposed in order to get a high output power and pump-efficiency. By using three level addressing methods, it can increase both of pump-efficiency and power-efficiency. The proposed three level addressing mixed-structure charge pump can operate at as high as 1MHz switching-frequency on the 0.1 μF pump-capacitors. Simulation by using HSPICE level 3 model shows that our work can convert the input low DC-voltage (Vin=1.5V) up near to 11.26 times of it (VOUT=16.9V), so that more output power can be generated with a little power loss. The newly proposed addressing method for DC-DC charge pump circuit is suitable for various low-voltage applications.

Single Inductor DC-DC Converter with Independent Bipolar Outputs Using Charge Pump

This paper describes a bipolar output DC-DC converter that uses a single inductor for size andcost reduction. We propose a timing diagram for a charge pump circuit which generates the negative outputvoltage, and present its con guration, operation principle and simulation results. We also show that employingpseudo-continuous conduction mode improves cross-regulation between the two outputs.

High Pumping Gain Dickson Charge Pump Using Bootstrapped Technique

This paper proposed a bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump for high output power and pump-efficiency. By using bootstrapped technique, it can increase both of pump-efficiency and power-efficiency. The proposed bootstrapped based charge pump can avoid the threshold voltage drop and enable to generate a higher output voltage. Simulation by using HSPICE level 3 model shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.4 times of it (VOUT=6.62V), pump efficiency can reach up to 88.26%.

A CMOS 5.4/3.24-Gbps Dual-Rate CDR with Enhanced Quarter-Rate Linear Phase Detector

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a ‘Mode’ switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under 2 31 –1 bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm×1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 µm CMOS process.

A CMOS 3.2 Gb/s serial link transceiver, using a new PWAM scheme

In this article, a 3.2 Gb/s serial link transceiver, that can be implemented in 0.35 μm CMOS technology is presented. In this transceiver a new multi-level pulse-width-amplitude modulation technique is used. The symbol rate is reduced, while the minimum pulse width (PW) is increased considerably, using the proposed modulation. The PW is larger than the conventional NRZ data format, with PW of Tb, so the ISI will be improved. The multiphase output of a three stage ring oscillator VCO in the PLL is used to modulate and to demodulate the signal. A new charge pump circuit is also introduced to decrease the mismatch between up and down paths. The peak to peak jitter of recovered clock is 21 ps at 800 MHz. The recovered data has the peak to peak jitter of 51 ps. The transmitter and receiver power consumption is 220 and 35 mW, respectively.

A Low-Power Bidirectional Telemetry Device With a Near-Field Charging Feature for a Cardiac Microstimulator

In this paper, wireless telemetry using the near-field coupling technique with round-wire coils for an implanted cardiac microstimulator is presented. The proposed system possesses an external powering amplifier and an internal bidirectional microstimulator. The energy of the microstimulator is provided by a rectifier that can efficiently charge a rechargeable device. A fully integrated regulator and a charge pump circuit are included to generate a stable, low-voltage, and high-potential supply voltage, respectively. A miniature digital processor includes a phase-shift-keying (PSK) demodulator to decode the transmission data and a self-protective system controller to operate the entire system. To acquire the cardiac signal, a low-voltage and low-power monitoring analog front end (MAFE) performs immediate threshold detection and data conversion. In addition, the pacing circuit, which consists of a pulse generator (PG) and its digital-to-analog (D/A) controller, is responsible for stimulating heart tissue. The chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) with 0.35-μm complementary metal-oxide semiconductor technology to perform the monitoring and pacing functions with inductively powered communication. Using a model with lead and heart tissue on measurement, a -5-V pulse at a stimulating frequency of 60 beats per minute (bpm) is delivered while only consuming 31.5 μW of power.

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18 μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range. Furthermore, a method of adding a precharging current source is proposed to increase the initial charge current, which will speed up the settling time of CPPLLs. Test results show that the current mismatching can be less than 0.4% in the output voltage range of 0.4 to 1.7 V, with a charge pump current of 100 μA and a precharging current of 70 μA. The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35μm 2P4M CMOS technology. The chip area without pads is only 0.87mm×0.65mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8V power supply voltage (VDD=1.8V) can be pumped up to 8.2V. The proposed charge pump circuit achieves efficiency of 60% at 80μA.

Benthic Microbial Fuel Cell as Direct Power Source for an Acoustic Modem and Seawater Oxygen/Temperature Sensor System

Supported by the natural potential difference between anoxic sediment and oxic seawater, benthic microbial fuel cells (BMFCs) promise to be ideal power sources for certain low-power marine sensors and communication devices. In this study a chambered BMFC with a 0.25 m(2) footprint was used to power an acoustic modem interfaced with an oceanographic sensor that measures dissolved oxygen and temperature. The experiment was conducted in Yaquina Bay, Oregon over 50 days. Several improvements were made in the BMFC design and power management system based on lessons learned from earlier prototypes. The energy was harvested by a dynamic gain charge pump circuit that maintains a desired point on the BMFC's power curve and stores the energy in a 200 F supercapacitor. The system also used an ultralow power microcontroller and quartz clock to read the oxygen/temperature sensor hourly, store data with a time stamp, and perform daily polarizations. Data records were transmitted to the surface by the acoustic modem every 1-5 days after receiving an acoustic prompt from a surface hydrophone. After jump-starting energy production with supplemental macroalgae placed in the BMFC's anode chamber, the average power density of the BMFC adjusted to 44 mW/m(2) of seafloor area which is better than past demonstrations at this site. The highest power density was 158 mW/m(2), and the useful energy produced and stored was ≥ 1.7 times the energy required to operate the system.

A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip

A phase-locked loop (PLL) is proposed for low-voltage applications. A new charge pump (CP) circuit, using gate switches affords low leakage current and high speed operation. A low-voltage voltage-controlled oscillator (LV-VCO) composed of 4-stage delay cells and a low-voltage segmented current mirror (LV-SCM) achieves low voltage-controlled oscillator gain (KVCO), a wide tuning range, and good linearity. A LV-SCM generates more current with small area by switching the body rather than the gate. The PLL is implemented in standard 90-nm CMOS with regular VT (RVT) devices. Its output jitter is 2.22 ps (rms), which is less than 0.5% of the output period. The phase noise is - 87 dBc/Hz at 1-MHz offset from a 2.24-GHz center frequency. Total power dissipation at 2.24-GHz output frequency, and with 0.5-V power supply is 2.08 mW (excluding the buffers). The core area is 0.074 mm2.

A new energy harvest system with a hula-hoop transformer, micro-generator and interface energy-harvesting circuit

This study presents a synthesis of a new energy harvest system that consists of a hula-hoop transformer, a micro-generator and an interface energy harvest circuit. The hula-hoop transformer mainly comprises a main mass sprung in one translational direction and a free-moving mass attached at one end of a rod, the other end of which is hinged onto the main mass. The transformer is capable of transforming linear reciprocating motions to rotary ones based on the concepts similar to the hula hoop motions. The transformer is subsequently integrated with a miniaturized rotary generator in size of 10 × 10 × 2 mm3 and its compact energy harvest circuit chip. The designed generator consists of patterned planar copper coils and a multi-polar hard magnet ring made of NdFeB. The genetic algorithm (GA) is next applied to optimize the critical dimensions of the miniaturized generator. The optimized generator offers 4.5 volt and 7.23 mW in rms at 10,000 rpm. With micro-generator successfully fabricated, a novel energy harvest circuit employing a new dual phase charge pump, power management circuit, a low dropout regulator and battery charger is designed and fabricated via the 0.35 μm process. This charge pump circuit owns the merit of automatic conversion of low-power AC signals by the micro-generator to DC ones. Experiments were conducted to show the favorable performance of the proposed energy harvest system. This is the first work that invents a motion transformer from ubiquitous reciprocating to rotational motions. In this way, higher-efficient energy conversion via compact-sized rotational electromagnetic generators can be realized as opposed to popular piezoelectric structures.

Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process

A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide reliability problem in low-voltage CMOS process. The four-phase clocks were used to control the charge-transfer devices turning on and turning off alternately to suppress the return-back leakage current. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage to drive a capacitive output load, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide overstress problem, the new proposed charge pump circuit is suitable for applications in low-voltage CMOS IC products.

A CMOS Digitized Silicon Condenser Microphone for Acoustic Applications

In this paper, a CMOS digitized silicon condenser microphone for acoustic applications is newly proposed. The proposed CMOS digitized silicon condenser microphone is attractive due to the fact that the sensor and all the circuits are robustly and compactly integrated. Another innovation of this proposed CMOS digitized silicon condenser microphone is that it could be operated without charge pump circuits. Thus, the sensor and circuits can be performed at the same power supply. Based upon 0.35 μ m 2P4M CMOS technology with 3 V power supply, measurement results have successfully verified the correct function and performance of the proposed CMOS digitized silicon condenser microphone. The area of the proposed CMOS digitized silicon condenser microphone is 1444 × 1383 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the FOM of the sigma-delta modulator is 163.85 dB. The proposed CMOS digitized silicon condenser microphone is suitable for mobile phones, laptops, PDAs, and hearing aids, etc.

Design of Charge Pump Circuit with VCO

For programming such as writing or erasing of the flash memory, two different kinds of high voltage are required, and the charge pump circuit has been used for this. The charge pump circuit proposed in this paper uses the VCO to adjust the clock frequency in order to match the reference voltage approved from the outside and the charge pump's output. Accordingly, I suggest a circuit that can produce a predictable output, regardless of not only an error by fabrication but also MOSFET's body effect generated in each part of the charge pump.