Charge Plasma Concept Research Articles

A novel Ge based overlapping gate dopingless tunnel FET with high performance

In this letter, the overlapping gate dopingless tunnel field-effect transistor (OGDL-TFET) is proposed and studied by TCAD simulation. To increase the tunneling efficiency and reduce the manufacture difficulty, a dopingless germanium tunneling junction based on charge plasma concept is induced in OGDL-TFET. A high efficiency line tunneling junction is formed by the gate/backgate overlap. The on-state current of 75.5 μA μm−1 and subthreshold swing of 1.9 mV/dec can be obtained. With cut-off frequency of 16.53 GHz and gain bandwidth product of 2.44 GHz, OGDL-TFET obtains good analog and radio frequency performance. The considerable good performance makes OGDL-TFET very attractive for ultra-low power application.

A Nano junctionless Double-Gate MOSFET by Using the Charge Plasma Concept to Improve Short-Channel Effects and Frequency Characteristics

In this study, a junctionless double-gate metal-oxide semiconductor field-effect transistor (MOSFET) is investigated by using the concept of charge plasma. The n+ charge plasma in source and drain regions is created electrically in the double-gate MOSFET (CPSD-MOSFET) using additional appropriate metals without applying doping. The results showed that the structure is like a conventional MOSFET, which can improve some electrical parameters. It protects the proposed structure from some limitations such as random doping oscillations and short-channel effects bearing its conventional structure. In addition, high temperature and annealing processes are unnecessary for making the source/drain doping of the CPSD-MOSFET because their regions are created electrically. Thus, the thermal budget step is removed. Furthermore, the proposed structure has some improvements as compared to the junctionless transistor structure, and it can overcome the main problem of this structure, namely the high off current. In general, in the proposed structure, the charge plasma idea changes the charges and depletion regions besides the channel and improves the short-channel effects such as hot electron effect and leakage current because of the improved electric field.

Impact of metal silicide source electrode on polarity gate induced source in junctionless TFET

Tunnel Field Effect Transistors (TFET) based on quantum mechanical band to band tunneling (BTBT) are promising alternatives for low power analog applications. Additionally, the concept of junctionless (JL) devices realized by the charge plasma concept offers added advantages in terms of simplified fabrication techniques. In n type JL-TFET, p+ source is induced using a polarity gate (PG) with suitable work function. However, retention of induced p+ source is not a sole contribution of PG, the source electrode (SE) metal silicide work function also plays a significant role in the retention of hole plasma (specially near the interface of SE/induced source). Thorough study regarding the combined influence of PG and SE metal silicide work function on induced p+ source is missing in the literatures. This work explores the performance of JL-TFET of different SE metal silicide such as TiSi2 (4.53 eV), CrSi2 (4.85 eV) and Pd2Si (5.3 eV). It is perceived that for SE metal silicide with work function lower than p+ induced source i.e., TiSi2 and CrSi2 the depletion of hole plasma (formation of Schottky interface) appears near the SE/p+ induced source interface. The depletion of hole plasma is attributed to the combined electric field of SE metal silicide and the PG, the immediate consequence is the refrainment of current. Further, due to the formation of Schottky interface for TiSi2 and CrSi2, the performance of the device is examined by revoking and evoking the Universal Schottky Tunneling (UST) model. Results reveal the undervalued performance of the device without the inclusion of UST, primarily a lower drain current (and thereby the analog performance) of the device is obtained, since it ignores the Schottky tunneling at SE/p+ induced source interface. However, the inclusion of UST model emulates the performance of JL-TFET precisely, by incorporating the Schottky tunneling at the SE/p+ induced source interface. Thus, for the retention of hole plasma, appropriate SE work function i.e., ΦSE > Φp+ induced source is required, whereas for SE work function ΦSE < Φp+ induced source appropriate Schottky tunneling must be considered for accurate analysis of the device. The study also reveals that the depletion of hole plasma and hence the formation of Schottky interface can be avoided using SE with metal work function source for which consideration of UST is immaterial.

An In0.53Ga0.47As/In0.52Al0.48As Heterojunction Dopingless Tunnel FET With a Heterogate Dielectric for High Performance

In this paper, an In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.52</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.48</sub> As heterojunction dopingless tunnel field-effect transistor (HDL-TFET) with an HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> heterogate dielectric is proposed, where the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -pocket with variable electron concentration can be formed by adjusting the length of source-side channel (LSC) based on the charge plasma concept, instead of employing conventional ion implantation or dual-material gate techniques. It aims to improve the device performance and simplify the device fabrication. At the drain bias of 0.3 V, numerical simulations show that the on-state current (ION) of the HDL-TFET with LSC = 4 nm can approach ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> A/μm that is far higher than that of the Si-DL-TFET (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> A/μm), and the average subthreshold swing (SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</sub> ) can approach 36.6 mV/decade that is significantly lower than that of the Si-DL-TFET (89.2 mV/decade). It is also found that the drain-induced barrier lowering (DIBL) effect and the ambipolar current can be effectively suppressed in the HDL-TFET because of an existence of heterojunction. Under the condition of low gate and drain biases, the HDL-TFET exhibits peak values of the cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and the maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) approaching 13 and 4.73 GHz, respectively, while the Si-DL-TFET yields those of 8.05 and 2.26 GHz, respectively, under relatively higher biases. It indicates that the HDL-TFET is a promising device for low-power consumption radio frequency applications.

Performance Improvement and Analysis of PtSi Schottky Barrier p-MOSFET Based on Charge Plasma Concept for Low Power Applications

This work reports a platinum silicide (PtSi) Schottky Barrier (SB) p-MOSFET (SB p-MOSFET) using charge plasma concept for low power applications. Here, we use two different materials to form source of the device. The source consists of two parts as primary source and extension. To consist source, PtSi and for extension, platinum metal is used. The proposed device is named as charge plasma (CP) SB p-MOSFET (CP SB p-MOSFET). The use of platinum extension induces the hole plasma near the source end. As a result, increased band bending reduces the SB width. This enhances the DC performance of the device. In addition, we have compared the DC and analog/RF performance of both the proposed device and the conventional SB p-MOSFET. It is observed that the proposed device exhibits improvement in on-state current (Ion), on- to off current ratio (ION/IOFF), transconductance (gm), cut-off frequency (ft), product of gain and bandwidth (fa) and transconductance generation factor (gm/Ids). We also optimized the performance of the device by modulating the work function and length of metal employed for extension. Moreover, the proposed device eliminated the doping, lowers the thermal budget requirement and unaffected from fluctuations due to randomly distributed dopant.

Electrostatically doped drain junctionless transistor for low-power applications

Junctionless transistors (JLT) are a promising alternative to address the stringent junction requirements in conventional transistors. However, JLTs are plagued by high OFF-state leakage current attributed to the band-to-band tunneling at the channel–drain interface. This leakage current is often referred to as gate-induced drain leakage (GIDL). In this paper, we propose an effective technique to suppress GIDL in JLTs. We use the charge plasma concept to realize an electrostatically doped drain (EDD) separated from the channel by an intermediate intrinsic region. Therefore, the proposed EDD–JLT is an n+–n+–i–n+ structure that widens the tunnel barrier at the gate–drain interface in the OFF-state (VGS = 0 V, VDS = 1 V) and offers significant reduction in leakage current. We compare, using 2D TCAD device simulations, the EDD–JLT with the conventional JLT in terms of various digital and analog performance metrics. We observe that EDD–JLTs of gate length 20 nm offer a significant reduction in IOFF (~ 4 orders) while substantially improving ION/IOFF ratio (~ 4 orders) as compared to conventional JLTs. To study the scalability of the proposed technique, the device thickness and gate length were scaled down to 5 nm. We observe that even for scaled-down structure, EDD–JLTs retain their performance benefit. We observe that the analog performance metrics such as intrinsic gain (GmRo), transconductance generation factor (Gm/ID), output conductance (GD), channel length modulation, and drain-induced barrier lowering of EDD–JLTs are also significantly improved as compared to conventional JLTs.

Dopingless 1T DRAM: Proposal, Design, and Analysis

In this paper, we have proposed a dopingless 1T DRAM (DL-DRAM) that utilizes the charge plasma concept. The proposed device employs a misaligned double-gate architecture to store holes and differentiates between the two logic states. The source, drain, backgate, and frontgate workfunctions are optimized to achieve the required concentration profiles in an intrinsic silicon body. Using TCAD simulations, we have analyzed the read/write mechanism in the device. Our study shows that the mechanism of current transport during reading operation depends strongly on the source workfunction. When the source workfunction is less than 4.5 eV the transport mechanism during reading is dominated by drift-diffusion. However, when the source workfunction is greater than 4.5 eV , the transport mechanism during read is dominated by band-to-band tunneling (BTBT). In general, when the dominant mechanism of current transport is BTBT, the retention time and the read-1/0 current ratio is higher, and the sense margin is lower in the case in which the dominant mechanism of current transport is drift-diffusion. Due to the avoidance of doping, the proposed DL-DRAM is expected to be free from random dopant fluctuation. Moreover, high temperature annealing processes required after ion implantation can be avoided. The lower thermal requirements of a DL-DRAM opens the possibility of fabricating DRAMs using processes which are compatible with bio-materials and opto-electronics and in ensuring bottom MOSFET and interconnects preservation in 3D VLSI integration.

Analytical Modeling of Charge Plasma-Based Optimized Nanogap Embedded Surrounding Gate MOSFET for Label-Free Biosensing

In this paper, analytical modeling of a charge plasma-based nanogap embedded surrounding gate MOSFET biosensor for label-free biosensing has been presented and verified with extensive simulated device data. Along the channel, considering parabolic potential profile, surface potential,threshold voltage,and drain currents have been modeled. Sensitivity has been analyzed by measuring the shift in I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> and threshold voltage when the biosensor interacts with the neutral or charged biomolecules. Less thermal budgeting scheme with simplified fabrication process flow, i.e., no ion implantation or diffusion can be achieved easily here due to new charge plasma concept. In addition, the issues related to the doping control and random dopant fluctuations have been reduced significantly to make the device immune to the process variation. Hence, the proposed device has been optimized for the enhancement in device electrostatics and sensitivity. Extensive TCAD simulations have been performed to investigate the device parameters and to verify the model data. Hence, the proposed model can be considered as an optimal model of a biosensor for the future reference.

A computational study of a carbon nanotube junctionless tunneling field-effect transistor (CNT-JLTFET) based on the charge plasma concept

In this work, a carbon nanotube junctionless tunnel field-effect transistor has been proposed and investigated. The presented structure uses two isolated gates with the same work function (main gate (MG) and P-gate (PG)) which are separated by a 3 nm SiO2 spacer. PG has a constant voltage and a constant length of 0.4 V and 12 nm, respectively which has been used for electrically activation of the source region to behave like a tunnel FET. Simulations show that in comparison with the conventional carbon nanotube tunnel field-effect transistor (CNT-TFET) and carbon nanotube tunnel field-effect transistor with hetero-gate dielectric (HGD-CNT-TFET) suggested structure has significant higher ON current and improvement in ambipolar behavior. Furthermore, analog characteristics like unity gain frequency (ft) and transconductance (gm) have been improved considerably.

Device and circuit level performance assessment of n‐ and p‐type dopingless MOSFETs

AbstractIn this paper, two structures of n‐ and p‐type dopingless MOSFETs have been presented and compared with conventional n‐ and p‐type doped MOSFETs. The different regions of dopingless devices (n‐ and p‐type dopingless MOSFETs) have been realized by using metal work function engineering: a charge plasma concept. The simulation studies of the doped (n‐ and p‐type doped MOSFETs) and dopingless (n‐ and p‐type dopingless MOSFETs) devices have been performed using Atlas 2D simulator. It has been observed that the dopingless devices outperform the conventional doped devices by sizeable margin. The various performance measuring parameters in which dopingless devices shows improvement in comparison with conventional doped devices are ON current (Ion), cutoff frequency (fT), subthreshold swing (SS). A comparative analysis for DL‐nMOSFET shows 19% improvement in Ion, 24% in fT, 1.5% in SS, approximately seven times in DIBL, and 38% in Ion/Ioff. Almost similar improvement has been seen in DL‐pMOSFET when compared conventional doped pMOSFET (D‐pMOSFET). Besides this, Complementary Metal Oxide Semiconductor (CMOS) inverter has been designed using doped‐ and dopingless‐based MOSFETs. A significant improvement of 34.2% in switching delay has been achieved in the dopingless CMOS‐based inverter. Further, it has been observed that the process variation effect at device and circuit level are almost negligible in dopingless‐based devices and circuit configuration in comparison with conventional doped counterpart.

Gate-All-Around Charge Plasma-Based Dual Material Gate-Stack Nanowire FET for Enhanced Analog Performance

In this paper, a gate-all-around (GAA) charge plasma-based dopingless dual material gate nanowire FET is proposed (CP-DM). This structure is further explored by adding gate-stack (high-k + SiO2) feature (CP-GS-DM). In these dopingless structures, source/drain is induced using a charge plasma concept by an appropriate selection of work functions for source/drain electrodes. The dopingless devices offer low thermal budget with easier fabrication steps and reduced random dopant fluctuations effect. Both the dopingless structures are investigated for analog performance, and results are compared with those obtained from the GAA junctionless dual material (JL-DM) gate and the JL gate-stacked DM gate (JL-GS-DM), respectively. The charge plasma-based dopingless devices when compared with their JL counterpart show improvement in drive current ( ${I}_{\text {D}}$ ), transconductance ( ${g}_{m}$ ), transconductance gain factor ( ${g}_{m}/{I}_{D}$ ), output conductance ( ${g}_{\text {ds}}$ ), early voltage ( ${V}_{\text {AE}}$ ), intrinsic gain ( $A_{\text {v}}$ ), drain-induced barrier lowering, and subthreshold slope. Thus, dopingless structures show enhanced analog performance with reduced short channel effects. The charge plasma based dopingless gate stacked dual material gate (CP-GS-DM) shows the best performance of all the structures. The analysis is further carried out for investigating the device design parameters effect on performance, namely, total gate length, ${L}_{G}$ , and ratio of control gate length to total gate length, $L_{\text {M1}}/{L}_{G}$ . This way dopingless charge plasma-based devices incorporate DM and GS features that make these devices interesting and reliable candidates for analog application with cost-effective fabrication.

Impact of interface trap charges on dopingless tunnel FET for enhancement of linearity characteristics

For the first time, we have explored the effect of positive and negative interface trap charges on the dopingless device using charge plasma concept and named the proposed device as heterogeneous gate dielectric charge plasma tunnel field-effect transistor (HD-CP-TFET). The heterogeneous gate dielectric is considered to improve the ON-state current and device performance. The main intention of this work is to improve the drain current, transconductance characteristics along with linearity figure-of-merits (FOMs). A comparative analysis is done with conventional CP-TFET in the presence of interface trap charges (ITCs). From comparative results, it is found that the proposed device shows a better performance in the presence of interface trap charges. All the simulations are performed on ATLAS TCAD device simulator. The results show that the proposed device has a better tunneling current, transconductance (\(g_{\text {m}}\)), cut-off frequency (\(f_{\text {T}}\)), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3), and third-order intermodulation distortion (IMD3). Thus, the proposed device (HD-CP-TFET) shows the better performance in the presence of interface trap charges and indicates that this device is suitable for low-voltage analog/RF applications.

Incorporation of hafnium and platinum metal in vertical power MOSFETs

A novel, vertical single-diffused metal–oxide–semiconductor (VSDMOS) structure is proposed by applying workfunction engineering to a vertical power metal–oxide–semiconductor field-effect transistor (MOSFET) with source and drain regions formed using the charge plasma concept. Electron and hole plasma was induced by employing hafnium and platinum metal. Furthermore, the electrical characteristics of the proposed VSDMOS were compared with those of conventional vertical double-diffused metal–oxide–semiconductor devices, revealing that the proposed VSDMOS exhibits a 14 % increase in current driving capability, with improved breakdown voltage.

A dopingless gate-all-around (GAA) gate-stacked nanowire FET with reduced parametric fluctuation effects

This paper proposes a gate-all-around silicon nanowire dopingless field-effect transistor (FET), utilizing a gate-stacked technique. The source and drain regions are formed by employing a charge plasma concept, with the application of appropriate work functions for metal contacts. The charge plasma approach reduces the need for doping control during fabrication, and thus reduces the thermal budget, while the gate-stacked structure solves the problem of scaling limitations with respect to the \(\hbox {SiO}_{2}\) dielectric thickness (< 2 nm). The simulation results show that the proposed device, when compared with a conventional junctionless nanowire FET (JL-NWFET), possesses enhanced performance parameters, with improved immunity to short-channel effects. The random dopant fluctuations (RDFs) of the proposed device are analyzed and compared with those of a conventional JL-NWFET. The conventional device has a high doping concentration, and as a result suffers from higher RDFs, whereas the proposed dopingless device possesses lower RDFs. The process parameters used to measure sensitivity to RDFs include the radius, doping concentration and gate oxide thickness. When the radius of the nanowire is varied by \(+\) 30%, changes in threshold voltage, on-state current and subthreshold slope of 66, 63 and 12%, respectively, are observed in the JL-NWFET, versus 5, 22.6 and 1.8% for the proposed dopingless device (CP-NWFET). Similar variations in doping concentration and gate oxide thickness are seen with the JL-NWFET, whereas the CP-NWFET is largely unaffected. Thus, the proposed gate-stacked dopingless CP-NWFET solves the issue of both doping control and scaling limitation of the gate oxide layer, which paves the way for easier fabrication, with exceptional immunity against parametric variations, making it a good candidate for future nanoscale devices.

Performance analysis of gate all around GaAsP/AlGaSb CP-TFET

Illustration of importance of gate all around (GAA) structure and hetero-junction formed by III-V semiconductor compounds has been analysed through GaAsP/AlGaSb CP-TFET (charge plasma tunnel field effect transistor). Charge plasma concept has been incorporated here to make this device more immune towards random dopant fluctuations (RDF). A high driving current of 1.28×10−5 A/μm and transconductance (gm) of 96.4 μS at supply voltages VGS = 1V and VDS = 0.5V is achieved. Further, implications of employing this device in analog/RF circuits have been supported with simulated results showing a high cut-off frequency of 34.5 THz and device efficiency of 3.45 MV−1. Apart from this, an insight of the linearity performances has also been included. Simultaneously, all the results are compared with a conventional gate all around charge plasma TFET.

A High-Performance Gate Engineered InGaN Dopingless Tunnel FET

A gate engineered InGaN dopingless tunnel FET (DL-TFET) using the charge plasma concept is proposed and investigated by silvaco Atlas simulation. In0.75Ga0.25N is a direct gap semiconductor, and the effective tunneling mass of electron and hole is smaller than that of silicon, which induces that the drain current and average subthreshold swing (SSavg) of InGaN DL-TFET improve $\text {1.3}\times \text {10}^{\text {2}}$ times and 51.1% than that of Si DL-TFET at the overdrive voltage of 0.5 V, respectively. What is more, better device performances are achieved by gate engineering with appropriate “In” fraction, proper space between the gate and source ( ${L}_{\text {gs}}$ ), and appropriate tunneling gate work function ( $\Phi _{\text {TG}}$ ). The direct-current, RF, and energy-efficient performance studies show that SSavg of 7.9 mV/dec, an on-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) of $\text {8.02} \times \text {10}^{-\text {5}}$ A/ $\mu \text{m}$ , a cutoff frequency ( ${f}_{T}$ ) of 119 GHz, and an energy delay product of 0.64 fJ-ps/ $\mu \text{m}$ can be obtained in the proposed TFET. This paper indicates that the gate engineered InGaN DL-TFET is a promising TFET for low-power RF and digital logic applications.

Impact of asymmetric dual-k spacers on tunnel field effect transistors

In this paper, we propose a novel device structure for tunneling FETs, based on charge plasma concept, such as junctionless-TFET (JLTFET) and dopingless-TFET (DLTFET) with asymmetric dual-k spacer. Using 2-D simulations, we demonstrate that ON-state current increases significantly with the use of asymmetric dual-k spacers between the gate and p-gate/source in JLTFET and DLTFET. We optimize the spacer length ( $$L_\mathrm{S}$$ ) between gate and p-gate/source for these transistors having low-k spacer only. We have employed dual-k spacer, which consists of high-k spacer on gate side and low-k spacer on source side, which could also be interchangeably used. We also optimize the inner high-k spacer length for better analog and digital performance and investigate their impacts on the transistor performance. The simulation results for asymmetric dual-k spacers JLTFET (ADK-JLTFET) offer an improvement of two orders in ON-state current, with point subthreshold slope of 40 mV/dec, and a high $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ ratio of $$\sim 10^{8}$$ . We estimate the improvement in digital performance using ‘ $$I_{\mathrm{o}}/C_{\mathrm{in}}$$ ’ ( $$I_{\mathrm{D}}/C_{\mathrm{GG}}$$ ) and analog performance using unity gain frequency ‘ $$f_{\mathrm{T}}$$ ’ as the figure of merit. We observe that the proposed ADK-JLTFET offers 30 times increase in $$I_{\mathrm{o}}/C_{\mathrm{in}}$$ and 24 times increase in $$f_{\mathrm{T}}$$ as compared to JLTFET with only low-k spacer. Due to similar working mechanism, ADK-DLTFET also shows similar improvements.

Design and simulation of a doping-less charge plasma based enhancement mode GaN MOSFET

In this work, we design and simulate a doping-less normally OFF/enhancement mode GaN based MOSFET. The novelty of the device is that it uses the charge plasma concept to induce n type charge plasma in an undoped GaN film, by employing metal electrodes, to realize source and drain regions of a GaN MOSFET. The proposed device is not a hetero-structure device, like the conventional GaN/AlGaN MOSFET and is hence more reliable and free from the hetero-epitaxial defects, inverse piezoelectric effects, and can have reduced leakage. Further, the proposed device can be fabricated at a reduced thermal budget as it does not possess any doped region. A two dimensional calibrated simulation study of the proposed device has revealed that it exhibits a threshold voltage of 1.4 V, large $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ ratio of $$10 ^{12}$$ , cutoff frequency ( $$f_\mathrm{T}$$ ) of 0.58 GHz, maximum oscillation frequency ( $$f_{\mathrm{max}}$$ ) of 3.2 GHz, transconductance ( $$g_{\mathrm{m}}$$ ) of 40 mS/mm and a breakdown voltage of 22 V (at $$L_\mathrm{GD}= 0$$ ). Further, the enhancement mode operation in the proposed device has been realized in a much easier way than that in the state of the art doping less AlGaN/GaN based devices. A process flow for the fabrication of the proposed device is also given.

A high-performance channel engineered charge-plasma-based MOSFET with high-κ spacer

In this paper, the performance of graded channel double-gate MOSFET (GC-DGFET) that utilizes the charge-plasma concept and a high-κ spacer is investigated through 2-D device simulations. The results demonstrate that GC-DGFET with high-κ spacer can effectively improve the ON-state driving current (ION) and reduce the OFF-leakage current (IOFF). We find that reduction of the initial energy barrier between the source and channel is the origin of this ION enhancement. The reason for the IOFF reduction is identified to be the extension of the effective channel length owing to the fringing field via high-κ spacers. Consequently, these devices offer enhanced performance by reducing the total gate-to-gate capacitance (Cgg) and decreasing the intrinsic delay (τ).

Analytical modeling of label free biosensor using charge plasma based gate underlap dielectric modulated MOSFET

In this paper charge plasma based dielectric modulated four gated MOSFET (CP-GUDM-MOSFET) has been proposed for the efficacy of label free electrical detection of the biomolecules. To achieve low thermal budgeting, charge-plasma concept is employed using appropriate metal work function electrodes. Extensive simulations have been done using the Sentaurus TCAD to validate the proposed architecture. An analytical modeling has also been done on surface potential and drain current to consolidate the feasibility of the structure. Significant improvements in the on current (ION) and threshold voltage have been observed in presence of the charged biomolecules. The performance of proposed structure is found to be sensitive to gate-oxide thickness variations. High sensitivity of the proposed CP-GUDM-MOSFET based biosensor with low thermal budgeting scheme; simple structure and its compatibility with the existing CMOS processes make it an exciting alternative to the conventional FET-based biosensors.