Charge Packet Size Research Articles

X-ray Photon Counting and Two-Color X-ray Imaging Using Indirect Detection.

In this paper, we report on the design and performance of a 1 cm2, 90 × 92-pixel image sensor. It is made X-ray sensitive by the use of a scintillator. Its pixels have a charge packet counting circuit topology with two channels, each realizing a different charge packet size threshold and analog domain event counting. Here, the sensor’s performance was measured in setups representative of a medical X-ray environment. Further, two-energy-level photon counting performance is demonstrated, and its capabilities and limitations are documented. We then provide an outlook on future improvements.

A Quantum-Limited Highly Linear Monolithic CMOS Detector for Computed Tomography

Computed tomography (CT) detector requires quantizing the wide dynamic range (WDR) photocurrent with high speed. Existing CMOS CT detectors are limited by their low linearity. They also need high-resolution external analog-to-digital converters (ADC) to quantize the WDR. In this work, a novel synchronous partial quantization technique is developed to enable monolithic CMOS CT pixel detector. Improved from previous current quantization designs, the new pixel detector quantizes the photocurrent in the charge domain with constant charge packet size. As the result, the pixel detector can quantize the WDR photocurrent with improved linearity. The two-step charge-domain ADC scheme also allows low resolution single-slope ADCs for residual voltage quantization, which enables in-pixel integration. A prototype pixel detector is fabricated in a 0.35 μm CMOS process. Silicon measurements show the detector can quantize signal currents from 6 pA to 63.4 nA with relative gain deviation lower than 0.06% at 1.1 kHz frame rate, which does not generate detector-induced artifact after the image reconstruction. The detector noise is smaller than the X-ray Poisson noise in the whole signal range. The minimum detector noise is 0.8 pArms. Hence, the detector achieves 16.6 bits dynamic range. The geometrical detective efficiency (GDE) of the detector is 75.5% including the band-gap voltage reference and ADC. The digital pixel detector can be easily tiled into a 2-D CT detection panel.

The double-sided floating-surface detector: an enhanced charge-detection architecture for CCD image sensors

A new high speed, low noise, nondestructive charge detector, called the Double-Sided Floating-Surface Detector (DS-FSD), which is fabricated in a standard CCD image sensor process, is reported. This detector can be integrated in CCD image sensors and is capable of detecting large charge packets at very low noise levels. Typical values are 5-8 noise electrons (within a bandwidth of 5 MHz) for a charge packet size of 100000 to 250000 electrons. The detector is used as the first MOS transistor in a three-stage source-follower configuration with a bandwidth of 150 MHz. The performance of both the traditional Floating-Surface Detector and Double-Sided Floating-Surface Detector (DSFSD) are calculated using a new, simple, model, This model is experimentally verified.

Noise analysis and measurements on buried channel charge coupled devices

Abstract Noise analysis of buried channel CCD by computer simulation is presented. The potential profile and signal charge distribution in potential well are obtained by solving Poisson's equation with a depletion approximation model. According to this model, it is possible to predict the volume occupied by signal charges in potential well. Thereby, the well capacitance and free carrier density are obtained. Then the device noise in the buried channel charge‐coupled device, including the output reset noise, dark current noise, transfer noise and electrical injection noise at the input, can be calculated. Also, the charge handling capacity can be evaluated by integrating over the charge occupied volume. The dependences of the electrical injection noise and transfer noise on charge packet size and operating frequency have been calculated. This model can also calculate quantitatively the dependence of the charge handling capacity and the position of maximum potential on the magnitude of clock voltage. The no...

Optimum scaling of buried-channel CCD's

The maximum charge packet size in a two-phase charge-coupled device (CCD) is limited by many constraints relating to the transfer efficiency requirement and control circuit limitations. The constraints are quantified and an optimization routine is developed for designing CCD's with maximum charge capacity per unit area under these constraints. The optimum charge capacity for scaled down CCD's is calculated and it is shown that the normal buried channel cannot be designed to have adequate charge capacity at small geometries. A novel low-voltage buried-channel structure is introduced which uses a shallow p-type surface implant to minimize surface trapping and increases the charge capacity per unit area 2.4× compared to the normal buried channel. The optimum charge packet size at ∼1-µm geometry for these CCD structures, based on these calculations, is shown to be inadequate for VLSI dynamic memory applications.

Determination of buried channel parameters from IV and CV measurements

A simple, direct method is described for the extraction of the minimum carrier potential vs charge packet size in a buried channel CCD. Also obtainable from this technique is a direct measurement of the location of the top of the charge packet with respect to the silicon surface. Close correlation is found between the results obtained from this technique and the predictions of the step junction depletion layer approximation.

Noise measurements in charge-coupled devices

Measurements of the noise levels at the output of surface and bulk channel charge-coupled devices with three-phase overlapping polysilicon electrodes are presented. Pulser noise, correlated transfer noise, shot noise, dark current noise, and electrical insertion noise at the input have been measured and studied. The dependences of the electrical insertion noise and the transfer noise on charge packet size and clock frequency are discussed in detail and the latter related to interface state densities. New schemes and input circuits for low-noise electrical insertion of the signal charge are discussed. Our measurements indicate that the noise levels due to the intrinsic noise sources (transfer and storage noise) agree with our physical understanding of the device operation. The noise levels due to the extrinsic noise sources (pulser noise and electrical insertion noise) are above the expected theoretical values.

Operation of three-phase charge-coupled devices with two-level clocking waveforms

Both theoretical and experimental investigations of three-phase C.C D.'s have been carried out. The results of these investigations show that when these devices are driven by two-level clock pulses with linear edges backwards flow loss is an important loss mechanism. The exact value of the transfer inefficiency is strongly influenced by the clock voltage turn-off time with longer turn-off times giving, in general, lower inefficiencies. It has also been shown that the transfer inefficiency is a function of the charge-packet size and that for a given turn-off time the transfer inefficiency is independent of frequency over a wide range of clock frequencies.