Charge Handling Capacity Research Articles

The controlled-drift detector

A new position-sensing X-ray detector is presented. The novel device is called Controlled-Drift Detector (CDD). The detector is fully depleted and is operated by switching between integration and drift modes. The relevant details of the detector design are discussed. A complete experimental characterization of the fast readout of the integrated signal charges achievable with static drift fields in the range 100–400 V/cm has been carried out. Preliminary measurements to evaluate the charge-handling capacity are also shown. The CDD can provide unambiguous two-dimensional position measurement, high-resolution X-ray spectroscopy and time resolution below 1 ms.

Dynamic range of quadrature radio-frequency time-integrating acousto-optic correlator

A new time-integrating acousto-optic correlator (TIAOC) was developed. It combines relatively low complexity with an exceedingly wideband of signals analyzed. The main feature of the architecture is the use of the light beams interference to provide the quadrature processing channel. The dynamic range (DR) of the new TIAOC is calculated for the active and passive operating modes. Parameter optimization to achieve the maximum DR is performed. The photodetector charge handling capacity is shown to be the main DR limiter.

A new position sensing X-ray detector: working principle and experimental results

The working principle and the first experimental characterization of a new fully depleted X-ray detector, called controlled-drift detector (CDD), are presented. The detector is operated in integrate-readout mode. During the integration phase the signal electrons generated by the incident X-ray are stored in suitably engineered potential wells. During the readout phase the potential wells are removed and replaced by a uniform drift field that transports the signal electrons to the readout electrode. The drift time gives the position of incidence. Full depletion of the detector wafer allows for high X-ray efficiency and for backward illumination. The first experimental measurements demonstrate the fast readout of the integrated signal electrons achievable with a static drift field. At a drift field of 300 V/cm the measured readout speed is 0.35 cm//spl mu/s. The expected charge handling capacity is 10/sup 5/-10/sup 6/ electrons per pixel. The new detector provides unambiguous two-dimensional (2-D) position measurement with readout times of the order of 10 /spl mu/s.

LWIR 256 × 256 HgCdTe focal plane array operating at 88 K

A 256 × 256 IRCMOS array with a 35 μm pitch operating at 88 K and above 10 μm has been developed at LETI/LIR. High performance has been obtained using, on the one hand, a reduced dark current detector technology and, on the other, a new readout circuit architecture which maximises both charge handling capacity and responsivity. We have measured a NEDT of 13 mK at 88 K for a cutoff wavelength of 10.1 μm. A description of the array is given and the main electro-optical characteristics of the component are presented.

Long-wavelength 640×486 GaAs-AlGaAs quantum well infrared photodetector snap-shot camera

A 9-/spl mu/m cutoff 640/spl times/486 snap-shot quantum well infrared photodetector (QWIP) camera has been demonstrated. The performance of this QWIP camera is reported including indoor and outdoor imaging. The noise equivalent differential temperature (NE/spl Delta/T) of 36 mK has been achieved at 300 K background with f/2 optics. This is in good agreement with expected focal plane array sensitivity due to the practical limitations on charge handling capacity of the multiplexer, read noise, bias voltage, and operating temperature.

Thermionic-emission-based barrier height analysis for precise estimation of charge handling capacity in CCD registers

In designing charge-coupled device (CCD) image sensors, it is essential to be able to estimate charge handling capacity. Because electrons have thermal energy, storing electrons in a well in a CCD register requires a sufficient potential barrier height to keep them from overflowing. As the quantity of electrons in a well depends on the barrier height, knowledge of this height is indispensable for precise estimation of the charge handling capacity. The authors have derived an expression describing the barrier height on the basis of thermionic emission, assuming current coefficient I/sub 0/ and well capacitance C. We derived the current coefficient I/sub 0/ and well capacitance C with computer simulations and from the results estimate the magnitude of the barrier height for a typical Vertical-CCD (V-CCD) structure. We have also examined barrier height dependence on structural parameters. Finally, we determined the barrier heights experimentally, and our results support the values obtained in the simulation.

Low dark current infrared hot-electron transistor for 77 K operation

Recently, thermal imaging using quantum well infrared photodetector (QWIP) focal plane arrays has been demonstrated. However, the operating temperature needs to be kept around 60 K due to the large dark current occurring at higher temperatures. In order to achieve thermal imaging at 77 K, we have designed and demonstrated two infrared hot-electron transistor structures, whose dark current is two to three orders of magnitude lower than that of a QWIP. The resultant dark current falls within the limit of the charge handling capacity of a readout circuit, and the infrared detection is demonstrated to be background limited at 77 K. The noise equivalent temperature difference of the detectors is estimated to be 14 and 26 mK, respectively.

ＨＤＴＶカメラ用１インチ１５０万画素ＩＴ‐ＣＣＤ撮像素子

A one-inch format 1.5 M pixel Interline Transfer (IT) CCD image sensor has been developed for an HDTV camera system. We focused on two areas to achieve a low smear ratio while maintaining high sensitivity. One is the VCCD device structure. By using the device simulator, we have developed a new impurity profile for the buried P+-layer under the VCCD. The other focus area is the optical structure. Considering the incident angle, we simulated the optical path. This simulation helped us determine the size of an optical shield and an onchip microlens made of a deep-UV resist. We have achieved a sensivity of 80 nA/lx, a maximum charge handling capacity of 1.2×105 electrons, and a smear ratio less than-110 dB. A high-fidelity picture with a horizontal resolution of 820 TV lines has been obtained.

Noise analysis and measurements on buried channel charge coupled devices

Abstract Noise analysis of buried channel CCD by computer simulation is presented. The potential profile and signal charge distribution in potential well are obtained by solving Poisson's equation with a depletion approximation model. According to this model, it is possible to predict the volume occupied by signal charges in potential well. Thereby, the well capacitance and free carrier density are obtained. Then the device noise in the buried channel charge‐coupled device, including the output reset noise, dark current noise, transfer noise and electrical injection noise at the input, can be calculated. Also, the charge handling capacity can be evaluated by integrating over the charge occupied volume. The dependences of the electrical injection noise and transfer noise on charge packet size and operating frequency have been calculated. This model can also calculate quantitatively the dependence of the charge handling capacity and the position of maximum potential on the magnitude of clock voltage. The no...

A 1" format 1.5 M pixel IT-CCD image sensor for an HDTV camera system

A 1-in. format 1.5-million pixel IT (interline transfer) CCD (charge coupled device) image sensor has been developed for an HDTV (high-definition television) camera system. To achieve a low smear ratio while maintaining a high level of sensitivity, the authors have developed a new impurity profile of a buried P/sup +/-layer and an on chip microlens array whose material is a deep-UV resist. Using this sensor, a high-fidelity picture with a horizontal resolution of 820 TV lines has been obtained. The IT-CCD sensor has achieved a smear ratio of less than -90 dB, a sensitivity level of 80 nA/Lx, and a maximum charge handling capacity of 1.2*10/sup 5/ electrons. >

On the charge-handling capacity of epitaxial and ion-implanted GaAs buried channel charge-coupled devices

The charge-handling capacity of GaAs B.C.C.D.'s has been studied on the basis of the numerical solution of the 1-D and 2-D Poisson equations. Epitaxial and ion-implanted channels have been considered for two kinds of devices, respectively Schottky or M.I.S. gate B.C.C.D.'s. After having defined bulk storage conditions, we have showed that a 3-phase system and Schottky gate B.C.C.D. allow to store the more important signal-charge. A double implant channel structure is proposed to overcome the contact of the carriers with the interface in ion-implanted channel B.C.C.D. For both kinds of devices, the charge capacity increases when the channel doping concentration (or the dose) and when the channel thickness (or the implantation range) are reduced.

Two-dimensional transient analysis of a buried-channel charge-coupled device

An effective method of two-dimensional transient analysis of potential and charge carrier distribution in a buried-channel charge-coupled device (BCCD) operating in storage and transfer modes has been developed with the aid of the finite Fourier transform (FET) technique. The effect of different clocking schemes on charge carrier transfer inefficiency and charge handling capacity are examined and discussed using the method developed. It is also shown that, for a BCCD operating in the storage mode, two-dimensional analysis indicates that the charge handling capacity determined by one-dimensional analysis can result in overestimation, which is misleading.

Barrier lowering in short-channel CCD's

In a two-phase overlapping CCD structure, the potential barrier height in the gap between the two storage gates decreases as the gap length is reduced due to fringing field effects. The barrier lowering limits the charge handling capacity in short-channel CCD's. A two-dimensional model is developed to calculate the barrier height for the various gap lengths. A simple measurement technique is developed to obtain experimental data using submicrometer structures and the data is compared with the model. Several important process parameters relating to the barrier lowering are investigated for design consideration.

Photodetectors for acousto-optic signal processors

A description of devices, architecture, and performance criteria is presented for solid-state CCD and photodiode sensors useful in acousto-optic processing systems. Special attention is given to sensors used in both bulk and integrated optical acousto-optic instantaneous Fourier transform systems. The device physics of silicon photodetectors is presented in detail including discussion and analysis of quantum efficiency, responsivity, ctosstalk, charge handling capacity, data rate, optical to electrical transfer function, noise sources, dynamic range, and sensitivity. A description of new technologies, such as VHSIC and GaAs IC's which are applicable to sensor technology for AO signal processing systems is also presented.

Limitations of multilevel storage in charge-coupled devices

The feasibility of applying multilevel storage (MLS) in charge-coupled devices (CCD's) is demonstrated in this paper. The effect on the allowable number of levels of the different noise sources in the CCD, the input-signal power, the charge-handling capacity, and the effective bandwidth have been considered. Accurate noise measurements, by means of statistical correlation are presented. With eight levels of charge, three bits of data have been achieved in one storage cell with two-phase stepped-oxide double-polysilicon CCD's, and detected with an average error probability of 2 \times 10^{-10}. Four bits of data in one storage cell could be achieved in similar devices with a charge-transfer inefficiency of \epsilon \leq 1 \times 10^{-3} with an average error probability of less than 9 \times 10^{-8}.

The charge-handling capacity of buried-channel structures under hot-electron conditions

Hot-electron effects have been included in calculations of the charge-handling capacity of buffed-channel MOS structures. The calculation shows that the charge-handling capacity is drastically reduced by high electric fields parallel to the interface. For an electric field of 1.5-5 × 104V/cm the maximum charge capacity decreases by at least a factor of 2.

Calculation of charge-handling capacity in twin-layer peristaltic charge-coupled devices

Charge-handling capacity is an important parameter in determining the dynamic range of a charge-coupled device (CCD). Based on depletion approximation, a one-dimensional charge storage capacity calculation is given for an n-channel twin-layer peristaltic CCD with constant layer dopings. The charge capacity is found to increase linearly with surface layer implant dose for lower level implant and saturate at higher level implant.

Charge handling capacity in charge coupled devices

In analog signal processing applications, the charge handling capacity of a charge coupled device (CCD) is an important parameter that determines the dynamic range. In this paper, approximate expressions for the signal handling capacity for surface-channel and buried-channel CCD's are derived and compared. The upper limit for the buried-channel charge capacity is imposed by the onset of surface electron accumulation.

On the design of ion implanted buried channel charge coupled devices (BCCDs)

The allowable range for the channel dose of a buried channel CCD is obtained. The maximum charge handling capacity without surface trapping effect is found to depend on the channel dose and the substrate concentration. In the case of two phase buried channel CCDs, the barrier implant dose can be estimated depending on the charge storage capacity desired. The result is applicable to ion implanted shallow junction devices and can be extended to deeper junction epitaxial buried channel devices.

Twin-layer PCCD performance for different doping levels of the surface layer

The performance and technology of the twin-layer PCCD has been investigated for different doping levels of the surface layer. With respect to charge transfer efficiency and charge handling capacity, optimum conditions for the doping level of the surface layer can be established.