Charge-coupled Device Signal Research Articles

Deflection Basin Detection of Pavements Based on Linear Array Charge-Coupled Device (CCD) Photoelectric Sensors

Deflection is an important indicator of the overall pavement strength, and it is generally detected using the Falling Weight Deflectometer (FWD). In response to the shortcomings of FWD in use, a pavement deflection detection method based on a linear array charge-coupled device (CCD) photoelectric displacement sensor is proposed. Firstly, a detailed description is given of the working principle of the deflection detection photoelectric sensor for the center point of the deflection basin and other points. Secondly, a photoelectric displacement sensor using linear array CCD deflection detection is designed, including a laser, CCD signal processing module, CCD and its driver module, and upper computer communication module. Among them, the EPF10K20TC144-4 device of the FLEX 10K series from ALTERA company is used to generate CCD driving pulses; Two DM54LS245 are selected as the driving interface for CCD photoelectric sensors, and corresponding filtering and signal amplification circuits are designed to address the noise problem of CCD photoelectric signal injection. Finally, the fixed threshold method separates the background and image signals in the CCD photoelectric signal, and the microcontroller is connected to the serial port of the upper computer through the MAX232 chip. The displacement measurement experiment uses the designed linear array CCD photoelectric displacement sensor. The results show that the road deflection basin detection method by the linear array CCD photoelectric displacement sensor fully meets the actual detection requirements and can obtain dynamic deformation information of the tested road surface. It is helpful for a detailed understanding of the changes in the deflection basin of the road surface under load.

A digital CDS technique and its performance testing**Supported by National Natural Science Foundation of China (10978002)

Readout noise is a critical parameter for characterizing the performance of charge-coupled devices (CCDs), which can be greatly reduced by the correlated double sampling (CDS) circuit. However, a conventional CDS circuit inevitably introduces new noise since it consists of several active analog components such as operational amplifiers. This paper proposes a digital CDS circuit technique, which transforms the pre-amplified CCD signal into a train of digital presentations by a high-speed data acquisition card directly without the noisy CDS circuit, then implements the digital CDS algorithm through a numerical method. A readout noise of 3.3 e− and an energy resolution of 121 eV@5.9 keV can be achieved via the digital CDS technique.

A Low-Jitter Fast-Locking Multi-phase Clock for High Resolution CCD Processor

ABSTRACTA multi-phase clock circuit for a 14 bit 80 MHz charge-coupled device (CCD) signal processor is designed based on the Delay-Locked Loop (DLL) structure. To accelerate the DLL locking time, a new fast locking controller circuit is proposed in this paper. Besides, a low jitter delay cell circuit is used to reduce the influence of the jitter generated by multiple phase clock generating circuit on the performance of correlated double sampling (CDS) and A/D conversion in the high resolution CCD signal processor. A clock signal with adjustable phase for the CCD signal processor can be obtained by changing the value of the edge selected register. The proposed clock circuit implemented and simulated with SMIC 0.18 μm 3.3 V 1P6M mixed CMOS process and the area of layout is 1000 × 350 μm. Under the condition of TT/3.3V/27 °C, the simulation results with the input clock frequency of 80 MHz show that the DLL locking time is 1.3 μs. Besides, the peak-to-peak jitter is 1.09 ps and the RMS jitter is 182 fs.

CDS circuit with 0 to 18 dB, 9‐bit VGA functionality

For processing charge coupled device (CCD) signals, a correlated double sampling (CDS) circuit must be used to eliminate noise. Usually, the amplitude of the CCD signals is uncertain, either too small or too large, hence a variable-gain amplifier (VGA) is also needed to amplify the CCD signals. Traditionally, the CDS and the VGA are separated, each of which consumes much energy and large area. If only the CDS and the VGA would be combined together, much energy and area could be saved. Hence, a CDS with VGA functionality is proposed to achieve this goal. Besides, the VGA functionality provides a gain range of 0–18 dB, programmable with a 9 bit resolution, which is far better than the traditional ones. Also, the VGA gain curve follows a linear-in-dB characteristic, hence the VGA functionality has rather good linearity. Finally, the VGA gain curve demonstrates the good performance of the VGA functionality.

Multimodality Imaging of β-Cells in Mouse Models of Type 1 and 2 Diabetes

OBJECTIVEβ-Cells that express an imaging reporter have provided powerful tools for studying β-cell development, islet transplantation, and β-cell autoimmunity. To further expedite diabetes research, we generated transgenic C57BL/6 “MIP-TF” mice that have a mouse insulin promoter (MIP) driving the expression of a trifusion (TF) protein of three imaging reporters (luciferase/enhanced green fluorescent protein/HSV1-sr39 thymidine kinase) in their β-cells. This should enable the noninvasive imaging of β-cells by charge-coupled device (CCD) and micro-positron emission tomography (PET), as well as the identification of β-cells at the cellular level by fluorescent microscopy.RESEARCH DESIGN AND METHODSMIP-TF mouse β-cells were multimodality imaged in models of type 1 and type 2 diabetes.RESULTSMIP-TF mouse β-cells were readily identified in pancreatic tissue sections using fluorescent microscopy. We show that MIP-TF β-cells can be noninvasively imaged using microPET. There was a correlation between CCD and microPET signals from the pancreas region of individual mice. After low-dose streptozotocin administration to induce type 1 diabetes, we observed a progressive reduction in bioluminescence from the pancreas region before the appearance of hyperglycemia. Although there have been reports of hyperglycemia inducing proinsulin expression in extrapancreatic tissues, we did not observe bioluminescent signals from extrapancreatic tissues of diabetic MIP-TF mice. Because MIP-TF mouse β-cells express a viral thymidine kinase, ganciclovir treatment induced hyperglycemia, providing a new experimental model of type 1 diabetes. Mice fed a high-fat diet to model early type 2 diabetes displayed a progressive increase in their pancreatic bioluminescent signals, which were positively correlated with area under the curve–intraperitoneal glucose tolerance test (AUC-IPGTT).CONCLUSIONSMIP-TF mice provide a new tool for monitoring β-cells from the single cell level to noninvasive assessments of β-cells in models of type 1 diabetes and type 2 diabetes.

Design and performance of the SLD vertex detector: a 307 Mpixel tracking system

This paper describes the design, construction, and initial operation of SLD's upgraded vertex detector which comprises 96 two-dimensional charge-coupled devices (CCDs) with a total of 307 Mpixel. Each pixel functions as an independent particle detecting element, providing space point measurements of charged particle tracks with a typical precision of 4 μm in each co-ordinate. The CCDs are arranged in three concentric cylinders just outside the beam-pipe which surrounds the e +e − collision point of the SLAC Linear Collider (SLC). The detector is a powerful tool for distinguishing displaced vertex tracks, produced by decay in flight of heavy flavour hadrons or tau leptons, from tracks produced at the primary event vertex. The requirements for this detector include a very low mass structure (to minimize multiple scattering) both for mechanical support and to provide signal paths for the CCDs; operation at low temperature with a high degree of mechanical stability; and high speed CCD readout, signal processing, and data sparsification. The lessons learned in achieving these goals should be useful for the construction of large arrays of CCDs or active pixel devices in the future in a number of areas of science and technology.

A high performance CMOS A/D converter for a digital camcorder system

In a digital camcorder system, an A/D converter which converts the analog CCD (charge coupled device) signal into digital codes has an important role in determining the system performance. An A/D converter which has an 8-bit resolution and a 40 MSPS conversion speed is proposed. It has a ping-pong architecture. With 0.8 /spl mu/m double poly and double metal CMOS technology, the experimental prototype of the proposed A/D converter has a /spl plusmn/0.5 LSB integral nonlinearity error (INL) and /spl plusmn/0.5 LSB differential nonlinearity error (DNL).

Optical measurements with the aid of a one-dimensional CCD detector

The metrological characteristics of a multichannel optical detector based on a linear charge-coupled device (CCD) array were investigated. The method and results of measurements of the following quantities are given: the absolute sensitivity, conversion efficiency, noise, dynamic range, and nonlinearity. Sources of systematic errors are identified and ways for reducing them are discussed. A description is given of an image recording system in which a CCD 1200TsL7 array was used. The following parameters are reported for this system: the dynamic range (1600), the absolute sensitivity (400 photons per pixel), the conversion effciency (200 photons per reading), the nonuniformity of sensitivity (0.5%), and the nonlinearity coefficient (1.07). Software developed for this system makes it possible to correct for the CCD signal distortion. After correction, the large-signal measurement error is 0.15%.

Charge-coupled device signal processing models and comparisons

CCD signal processing schemes attempt to reduce the effect of (KTC), 1/f, and broadband noise on the output signal. A number of schemes have been reported over the years. These schemes employ time delay and subtraction to eliminate KTC noise and attenuate 1/f noise. They also include a low-pass function to reduce the effect of broadband noise. Signal processing schemes include dual-slope integration, correlated-double sampling, a variation of correlated-double sampling referred to as switchedexponential filtering, and transversal filters. Signal processing that does not use delay and subtraction to eliminate KTC noise is also discussed. A consistent technique is used to analyze the various processing schemes. Transfer functions for signal and noise are presented for each. Performance comparisons are given with emphasis on their applicability to relatively high speed CCD readout applications (readout rates of 1 Mpixel/s and faster).

Combined digital zooming and digital effects system utilizing CCD signal characteristics

An image processing system for digital zooming and digital effects is proposed. This system directly processes the CCD (charge coupled device) signal without separating it into luminance and chrominance signals, based on the characteristics of the color filter array in the CCD. By using the proposed color signal processing method, and efficient and high-quality digital zooming system is obtained. Various special effect functions are included in the system by adding simple controls for the addresses of the accompanied image buffers. The digital zooming can magnify the real-time dynamic images up to 4 times by 25 discrete steps. The digital effects unit achieves various visual effects by controlling the accompanied image buffers. To realize the proposed system, approximately 270000 transistors are integrated in a single chip VLSI by using 0.8 mu m double metal CMOS technology. >

A 1-GHz charge-packet replicator/subtractor circuit for GaAs CCD signal processing

A novel charge-packet replicator/subtractor circuit based on GaAs charge-coupled device (CCD) technology is described. The circuit exhibits linear gain of 0.989 operating at 1-GHz replication frequency, while consuming only several milliwatts of dynamic power. Experimental results for a prototype circuit operating over the frequency range of 1 MHz to 1 GHz are presented. Due to the low parasitic capacitance of the GaAs semi-insulating substrate, the gain is linear and nearly unity. The chip area required for the circuit consists of several CCD gates and a small MESFET. Based on C-V measurements, the dynamic power consumed for the replication/subtraction process (operating with 5-V clock swings) is estimated to be on the order of several milliwatts at 1 GHz where the operation takes place in 1 ns. Design constraints are outlined and compared to experimental results in an effort to explore the tradeoff between speed and gain. The circuit is shown to be relatively insensitive to the precise voltages used during operation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Signal processing techniques for CCD image sensors

Charge coupled device (CCD) image sensors are currently used in many image processing applications such as facsimile and bar code reading. Because the photodetectors in the device have finite areas, the output signal from the CCD image sensor is only an approximation to the sampled value of the image. In this paper we discuss the reconstruction of bar codes from the imperfect CCD signal by digital signal processing techniques. Schemes for encoding digital data in the form of bar codes are also discussed.

Radar Signal Processing: Digital, Charge-Coupled Device (CCD), Or Surface Acoustic Wave (SAW)?

Recent emphasis placed upon real-time coherent radar signal processing has fostered competition between digital, charge-coupled device (CCD) and surface acoustic wave (SAW) technologists. In that this stimulates and encourages technological advances, this competition is a healthy one; to the extent that the complementary rather than competitive properties of the technologies are not effectively utilized, the competition is counterproductive. The application of the various technologies to ground radar signal processors is investigated. The emergent theme emphasizes the fact that all signal processor tasks must be considered to properly assess the applicability of the various technologies; it is insufficient to compare signal processor implementations on the basis of a filtering function alone. To illustrate this viewpoint, examples of digital, CCD, and SAW signal processors are given.