A Low-Jitter Fast-Locking Multi-phase Clock for High Resolution CCD Processor

Abstract

ABSTRACTA multi-phase clock circuit for a 14 bit 80 MHz charge-coupled device (CCD) signal processor is designed based on the Delay-Locked Loop (DLL) structure. To accelerate the DLL locking time, a new fast locking controller circuit is proposed in this paper. Besides, a low jitter delay cell circuit is used to reduce the influence of the jitter generated by multiple phase clock generating circuit on the performance of correlated double sampling (CDS) and A/D conversion in the high resolution CCD signal processor. A clock signal with adjustable phase for the CCD signal processor can be obtained by changing the value of the edge selected register. The proposed clock circuit implemented and simulated with SMIC 0.18 μm 3.3 V 1P6M mixed CMOS process and the area of layout is 1000 × 350 μm. Under the condition of TT/3.3V/27 °C, the simulation results with the input clock frequency of 80 MHz show that the DLL locking time is 1.3 μs. Besides, the peak-to-peak jitter is 1.09 ps and the RMS jitter is 182 fs.