Transistor Characteristics Research Articles

Deep-learning-based precise characterization of microwave transistors using fully-automated regression surrogates

Accurate models of scattering and noise parameters of transistors are instrumental in facilitating design procedures of microwave devices such as low-noise amplifiers. Yet, data-driven modeling of transistors is a challenging endeavor due to complex relationships between transistor characteristics and its designable parameters, biasing conditions, and frequency. Artificial neural network (ANN)-based methods, including deep learning (DL), have been found suitable for this task by capitalizing on their flexibility and generality. Yet, rendering reliable transistor surrogates is hindered by a number of issues such as the need for finding good match between the input data and the network architecture and hyperparameters (number and sizes of layers, activation functions, data pre-processing methods), possible overtraining, etc. This work proposes a novel methodology, referred to as Fully Adaptive Regression Model (FARM), where all network components and processing functions are automatically determined through Tree Parzen Estimator. Our technique is comprehensively validated using three examples of microwave transistors and demonstrated to offer a competitive edge over the state-of-the-art methods in terms of modeling accuracy and handling the aforementioned issues pertinent to standard ANN-based surrogates.

Effects of Channel Length Scaling on the Electrical Characteristics of Multilayer MoS2 Field Effect Transistor

With the rapid miniaturization of integrated chips in recent decades, aggressive geometric scaling of transistor dimensions to nanometric scales has become imperative. Recent works have reported the usefulness of 2D transition metal dichalcogenides (TMDs) like MoS2 in MOSFET fabrication due to their enhanced active surface area, thin body, and non-zero bandgap. However, a systematic study on the effects of geometric scaling down to sub-10-nm nodes on the performance of MoS2 MOSFETs is lacking. Here, the authors present an extensive study on the performance of MoS2 FETs when geometrically scaled down to the sub-10 nm range. Transport properties are modelled using drift-diffusion equations in the classical regime and self-consistent Schrödinger-Poisson solution using NEGF formulation in the quantum regime. By employing the device modeling tool COMSOL for the classical regime, drain current vs. gate voltage (ID vs. VGS) plots were simulated. On the other hand, NEGF formulation for quantum regions is performed using MATLAB, and transfer characteristics are obtained. The effects of scaling device dimensions, such as channel length and contact length, are evaluated based on transfer characteristics by computing performance metrics like drain-induced barrier lowering (DIBL), on-off currents, subthreshold swing, and threshold voltage.

Poole-Frenkel (PF)-MOS: A Proposal for the Ultimate Scale of an MOS Transistor.

This work reports, for the first time, the phenomenon of lateral Poole-Frenkel current conduction along the dielectric/Si interface of a silicon nanowire metal-oxide semiconductor (MOS) transistor. This discovery has a great impact on the study of device characteristic modeling and device reliability, leading to a new kind of electronic device with a distinct operation mechanism for replacing the existing MOS transistor structure. By measuring the current-voltage characteristics of silicon nanowire MOS transistors with different nanowire widths and at elevated temperatures up to 450 K, we found that the current level in the conventional ohmic region of MOS transistors, especially for the transistors with a nanowire width of 10 nm, was significantly enhanced and the characteristics are no longer linear or in an ohmic relationship. The enhancement strongly depended on the applied drain voltage and strictly followed the Poole-Frenkel emission characteristics. Based on this discovery, we proposed a new type of MOS device: a Poole-Frenkel emission MOS transistor, or PF-MOS. The PF-MOS uses the high defect state Si/dielectric interface layer as the conduction channel and is expected to possess several unique features that have never been reported. PF-MOS could be considered as the ultimate MOS structure from a technological point of view. In particular, it eliminates the requirement of a subnanometer gate dielectric equivalent oxide thickness (EOT) and eradicates the server mobility degradation issue in the sub-decananometer nanowires.

A Phenomenological Model for Electrical Transport Characteristics of MSM Contacts Based on GNS.

Graphene nanoscroll, because of attractive electronic, mechanical, thermoelectric and optoelectronics properties, is a suitable candidate for transistor and sensor applications. In this research, the electrical transport characteristics of high-performance field effect transistors based on graphene nanoscroll are studied in the framework of analytical modeling. To this end, the characterization of the proposed device is investigated by applying the analytical models of carrier concentration, quantum capacitance, surface potential, threshold voltage, subthreshold slope and drain induced barrier lowering. The analytical modeling starts with deriving carrier concentration and surface potential is modeled by adopting the model of quantum capacitance. The effects of quantum capacitance, oxide thickness, channel length, doping concentration, temperature and voltage are also taken into account in the proposed analytical models. To investigate the performance of the device, the current-voltage characteristics are also determined with respect to the carrier density and its kinetic energy. According to the obtained results, the surface potential value of front gate is higher than that of back side. It is noteworthy that channel length affects the position of minimum surface potential. The surface potential increases by increasing the drain-source voltage. The minimum potential increases as the value of quantum capacitance increases. Additionally, the minimum potential is symmetric for the symmetric structure (Vfg = Vbg). In addition, the threshold voltage increases by increasing the carrier concentration, temperature and oxide thickness. It is observable that the subthreshold slope gets closer to the ideal value of 60 mV/dec as the channel length increases. As oxide thickness increases the subthreshold slope also increases. For thinner gate oxide, the gate capacitance is larger while the gate has better control over the channel. The analytical results demonstrate a rational agreement with existing data in terms of trends and values.

Bulk-fin field-effect transistor-based capacitorless dynamic random-access memory and its immunity to the work-function variation effect

In this study, we developed a capacitorless dynamic random-access memory (DRAM) (1T-DRAM) device based on a junctionless (JL) bulk-fin field-effect transistor structure with excellent reliability and negligible variability against work-function variation (WFV). We investigated the variation in the transfer characteristics and memory performance of the memory cell owing to WFV. In particular, to investigate the WFV effect, we analyzed the transfer characteristics and memory performance of 200 samples using four metal-gate materials—TiN, MoN, TaN and WN. Consequently, we discovered that the WFV affected the transfer characteristics of the JL bulk-fin field-effect transistor. However, the proposed 1T-DRAM demonstrated that the sensing margin and retention time produced minimal effect owing to the adoption of a structure storing holes in the fin region. Consequently, the proposed 1T-DRAM exhibited strong WFV immunity and excellent reliability for memory applications.

Effects of Interface States on Electrical Characteristics of Feedback Field-Effect Transistors

Effects of Interface States on Electrical Characteristics of Feedback Field-Effect Transistors

Deep Neural Networks for Determining Subgap States of Oxide Thin-Film Transistors

In this study, we propose a deep neural network (DNN) model that extracts the subgap states in the channel layer of oxide thin-film transistors. We have developed a framework that includes creating a model training set, preprocessing the data, optimizing the model structure, decoding from density-of-state (DOS) parameters to current–voltage (I–V) characteristics, and evaluating the model performance and accuracy of curve fitting. We investigate in detail the effect of data preprocessing methods and model structure on the performance of the model. The primary finding is that the input data type and the last hidden layer significantly affects the performance of the regression model. Using double-type input data composed of several voltages and linear current values is more advantageous than using log-scale current. Moreover, the number of nodes in the last hidden layer of a regression model with multiple output nodes should be large enough to avoid interference between the output values. The proposed model outputs five DOS parameters, and the resulting parameters are decoded to an I–V curve through interpolation based on the nearest 32 data from the given dataset. We evaluate the model performance using the threshold voltage and on-current difference between a target curve and the decoded curve. The proposed model calibrates 97.1% of the 14,400 curves within the threshold voltage difference of 0.2V and on-current error of 5%. Hence, the proposed model is verified to effectively extract DOS parameters with high accuracy based on the current characteristics of oxide thin-film transistors. We expect to improve the efficiency of defect analysis by replacing the iterative manual technology computer aided design (TCAD) curve fitting with an automatic DNN model.

Study on characteristics of neutron-induced leakage current increase for SiC power devices

In this paper, the displacement damage degradation characteristics of silicon carbide (SiC) Schottky barrier diode (SBD) and metal oxide semiconductor field effect transistor (MOSFET) are studied under 14-MeV neutron irradiation. The experimental results show that the neutron irradiation with a total fluence of 1.18×10<sup>11</sup> cm<sup>–2</sup> will not cause notable degradation of the forward <i>I-V</i> characteristics of the diode, but will lead to a significant increase in the reverse leakage current. A defect with energy level position of <inline-formula><tex-math id="Z-20230916130504">\begin{document}$ E_{\rm{C}} - 1.034 $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="18-20230976_Z-20230916130504.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="18-20230976_Z-20230916130504.png"/></alternatives></inline-formula> eV is observed after irradiation by deep level transient spectroscopy (DLTS) testing, which is corresponding to the neutron-induced defect cluster in SiC. This deep level defect may cause the Fermi level of n-type doping drift region to move toward the mid-gap level. It ultimately results in the decrease of the Schottky barrier and the increase of the reverse leakage current. In addition, neutron-induced gate leakage increase is also observed for SiC MOSFET. The gate current corresponding to <i>V</i><sub>gs</sub> = 15 V after irradiation increases nearly 3.3 times that before irradiation. The donor-type defects introduced by neutron irradiation in the oxide layer result in the difference in the conductivity mechanism of gate oxygen between before and after irradiation. The defects have an auxiliary effect on carrier crossing the gate oxide barrier, which leads to the increase of gate leakage current. The defects introduced by neutron irradiation are neutral after capturing electrons. The trapped electrons can cross a lower potential well and enter the conduction band to participate in conduction when the gate is positively biased, thus causing the gate current to increase with the electric field increasing. After electrons captured by donor-type defects enter the conduction band, positively charged defects are left from the gate oxide, leading to the negative shift of the transfer characteristics of SiC MOSFET. The results of DLTS testing indicate that the neutron irradiation can not only cause the intrinsic defect state of SiC material to change near the channel of MOSFET, but also give rise to new silicon vacancy defects. However, these defects are not the main cause of device performance degradation due to their low density relative to the intrinsic defect’s.

An Investigation of Process Variations and Mismatch Characteristics of Vertical Bipolar Junction Transistors

An Investigation of Process Variations and Mismatch Characteristics of Vertical Bipolar Junction Transistors

Fab-to-fab and run-to-run variability in 130 nm and 65 nm CMOS technologies exposed to ultra-high TID

The discovery of a large fab-to-fab variability in the TID response of the CMOS technologies used in the design of ASICs for the particle detectors of the HL-LHC triggered a monitoring effort to verify the consistency of the CMOS production process over time. As of 2014, 22 chips from 3 different fabs in 130 nm CMOS technology and 11 chips from 2 different fabs in 65 nm CMOS technology have been irradiated to ultra-high doses, ranging from 100 Mrad(SiO2) to 1 Grad(SiO2). This unprecedented monitoring effort revealed significant fab-to-fab and run-to-run variability, both dependent on the characteristics of the MOS transistors.

A guide for the characterization of organic electrochemical transistors and channel materials.

The organic electrochemical transistor (OECT) is one of the most versatile devices within the bioelectronics toolbox, with its compatibility with aqueous media and the ability to transduce and amplify ionic and biological signals into an electronic output. The OECT operation relies on the mixed (ionic and electronic charge) conduction properties of the material in its channel. With the increased popularity of OECTs in bioelectronics applications and to benchmark mixed conduction properties of channel materials, the characterization methods have broadened somewhat heterogeneously. We intend this review to be a guide for the characterization methods of the OECT and the channel materials used. Our review is composed of two main sections. First, we review techniques to fabricate the OECT, introduce different form factors and configurations, and describe the device operation principle. We then discuss the OECT performance figures of merit and detail the experimental procedures to obtain these characteristics. In the second section, we shed light on the characterization of mixed transport properties of channel materials and describe how to assess films' interactions with aqueous electrolytes. In particular, we introduce experimental methods to monitor ion motion and diffusion, charge carrier mobility, and water uptake in the films. We also discuss a few theoretical models describing ion-polymer interactions. We hope that the guidelines we bring together in this review will help researchers perform a more comprehensive and consistent comparison of new materials and device designs, and they will be used to identify advances and opportunities to improve the device performance, progressing the field of organic bioelectronics.

Germanium Spherical Quantum-Dot Single-Hole Transistors With Self-Organized Tunnel Barriers and Self-Aligned Electrodes

We report the fabrication and electrical characterization of single-hole transistors (SHTs), in which a Ge spherical quantum dot (QD) weakly couples to self-aligned electrodes via self-organized tunnel barriers of Si3N4. A combination of lithographic patterning, sidewall spacers, and selfassembled growth was used for fabrication. The core experimental approach is based on the selective oxidation of poly-SiGe spacer islands located at the specially designed included-angle locations of Si3N4/Si-trenches. By adjusting processing times for conformal deposition, etch back and thermal oxidation, good tunability in the Ge QD size and its tunnel-barrier widths were controllably achieved. Each Ge QD is electrically addressable via self-aligned Si gate and reservoirs, thus offering an effective building block for implementing single-charge devices.

Narrow-Width Effects in 28-nm FD-SOI Transistors Operating at Cryogenic Temperatures

In this paper, we present on the cryogenic characterization of short channel 28-nm FD-SOI nMOS and pMOS transistors having widths of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 ~\mu \text{m}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.08 ~\mu \text{m}$ </tex-math></inline-formula> at temperatures ranging from T = 300 K down to T = 10 K. We report, for the first time, the alarming concerns that the narrow-width effect imposes on the overall performance of highly scaled FD-SOI technologies, at temperatures below T = 77 K. The performance comparison between nMOS and pMOS devices is based on their drain current, threshold voltage, transconductance, subthreshold slope, low field mobility and total resistance. Our results show that the sensitivity of narrow width effects towards drain current, threshold voltage and total resistance is smaller in pMOS as compared to nMOS. The effective improvement in transconductance is also significantly larger in narrow width pMOS in comparison to their nMOS counterparts. A substantial degradation of subthreshold swing, total resistance and low field mobility is also observed in narrow nMOS devices, which questions the width scaling benefits of these technologies at cryogenic temperatures.

Edge and Interface Resistances Create Distinct Trade-Offs When Optimizing the Microstructure of Printed van der Waals Thin-Film Transistors

Inks based on two-dimensional (2D) materials could be used to tune the properties of printed electronics while maintaining compatibility with scalable manufacturing processes. However, a very wide range of performances have been reported in printed thin-film transistors in which the 2D channel material exhibits considerable variation in microstructure. The lack of quantitative physics-based relationships between film microstructure and transistor performance limits the codesign of exfoliation, sorting, and printing processes to inefficient empirical approaches. To rationally guide the development of 2D inks and related processing, we report a gate-dependent resistor network model that establishes distinct microstructure-performance relationships created by near-edge and intersheet resistances in printed van der Waals thin-film transistors. The model is calibrated by analyzing electrical output characteristics of model transistors consisting of overlapping 2D nanosheets with varied thicknesses that are mechanically exfoliated and transferred. Kelvin probe force microscopy analysis on the model transistors leads to the discovery that the nanosheet edges, not the intersheet resistance, limit transport due to their impact on charge carrier depletion and scattering. Our model suggests that when transport in a 2D material network is limited by the near-edge resistance, the optimum nanosheet thickness is dictated by a trade-off between charged impurity screening and gate screening, and the film mobilities are more sensitive to variations in printed nanosheet density. Removal of edge states can enable the realization of higher mobilities with thinner nanosheets due to reduced junction resistances and reduced gate screening. Our analysis of the influence of nanosheet edges on the effective film mobility not only examines the prospects of extant exfoliation methods to achieve the optimum microstructure but also provides important perspectives on processes that are essential to maximizing printed film performance.

Fabrication and characterization of T-gate polysilicon thin-film transistors with lightly-doped drain

We report detailed fabrication and characterization of poly-Si thin-film transistors (TFTs) with T-shaped gate (T-gate) and lightly-doped drain (LDD) structures. The formation of the LDD underneath the wings of a T-gate primarily relies on the shadowing of implanted dopants during the implantation of source and drain. Therefore, the fabrication of LDD structures in our proposed T-gate poly-Si TFTs can save a number of process steps as compared to conventional poly-Si TFTs with LDD structures. Our fabricated T-gated poly-Si TFTs with LDD structures not only exhibit suppressed off-state leakage current but also show a significant improvement in on-state current as compared to that of conventional poly-Si TFTs with the same top-gate dimension.

Furan-Containing Quinoidal Compounds for High-Performance Copper/Silver Electrode-Based n-Channel Organic Transistors

Furan-containing quinoidal compounds FTzTzF-C10 and FTzTzF-C8 were synthesized. These compounds have low lowest unoccupied molecular orbital (LUMO) energy levels and can form a charge transfer complex with Ag and Cu films, proved by cyclic voltammograms and Raman spectra. Single crystal diffraction results reveal that they adopt a lamellar layer structure with strong π–π interactions in crystals. Thin film transistor characterization shows that FTzTzF-C10 and FTzTzF-C8 exhibit n-channel behavior with an electron mobility of 1.18 cm2 V–1 s–1, one of the highest electron mobilities reported for thin film devices based on furan-containing semiconductors. Notably, the performance of FTzTzF-C10 and FTzTzF-C8 devices is nearly independent of the metals (Au, Cu, and Ag) of source–drain electrodes, which is ascribed to the ultrathin charge transfer layer formed by the spontaneous reaction of FTzTzFs and electrodes (Ag, Cu). These results demonstrate that furan is an excellent block for quinoidal semiconductors and promote the development of Cu/Ag electrode-based organic transistors.

Solution-Processed Isoindigo- and Thienoisoindigo-Based Donor-Acceptor-Donor π-Conjugated Small Molecules: Synthesis, Morphology, Molecular Packing, and Field-Effect Transistor Characterization.

Molecular design and precise control of thin-film morphology and crystallinity of solution-processed small molecules are important for enhancing charge transport mobility of organic field-effect transistors and gaining more insight into the structure-property relationship. Here, two donor-acceptor-donor (D-A-D) architecture small molecules TRA-IID-TRA and TRA-TIID-TRA comprising an electron-donating triarylamine (TRA) and two different electron-withdrawing cores, isoindigo (IID) and thienoisoindigo (TIID), respectively, were synthesized and characterized. Replacing the phenylene rings of central IID A with thiophene gives a TIID core, which reduces the optical band gap and upshifts the energy levels of frontier molecular orbitals. The single-crystal structures and grazing-incidence wide-angle X-ray scattering (GIWAXS) analysis revealed that TRA-TIID-TRA exhibits the relatively tighter π-π stacking packing with preferential edge-on orientation, larger coherence length, and higher crystallinity due to the noncovalent S···O/S···π intermolecular interactions. The distinctly oriented and connected ribbon-like TRA-TIID-TRA crystalline film by the solution-shearing process achieved a superior hole mobility of 0.89 cm2 V-1 s-1 in the organic field-effect transistor (OFET) device, which is at least five times higher than that (0.17 cm2 V-1 s-1) of TRA-IID-TRA with clear cracks. Eventually, rational modulation of fused core in the π-conjugated D-A-D small molecule provides a new understanding of structural design for enhancing the performance of solution-processed organic semiconductors.

Unidirectionally Aligned Donor–Acceptor Semiconducting Polymers in Floating Films for High‐Performance Unipolar n‐Channel Organic Transistors

AbstractThe orientational control of semiconducting polymers (SCPs) in floating films offers several advantages over conventional solution‐processing methods for device fabrication, and the unidirectional floating film transfer method (UFTM) has been applied to fabricate large‐area oriented p‐type SCP films. Here, UFTM can be used to prepare high‐performance n‐type SCP films of P(NDI2OD‐T2) is reported. A strong correlation between the degree of polymer orientation and the solvent used for the preparation of P(NDI2OD‐T2) floating films is observed. In particular, the size of the nanofibers aligned along the orientation direction prepared using chloroform is dramatically increased by adding a small amount of chlorobenzene. Microstructural characterization reveals that the P(NDI2OD‐T2) floating films are uniaxially aligned with edge‐on orientation, whereas the spin‐coated films are isotropic with face‐on orientation. Notably, the floating films of P(NDI2OD‐T2) prepared with solvent blending have higher electron mobility with ambipolar‐like device characteristics and high threshold voltage (VTH) of ≈25 V. Finally, using the one‐step immersion process, the introduction of an interlayer of hexa(ethylene glycol)‐dithiol between the source/drain contacts and P(NDI2OD‐T2) film results in a drastic improvement in device, giving unipolar n‐channel transistor characteristics with a VTH of ≈0 V, on/off ratio of &gt;105, and mobility reliability factor of almost 100%.

PENGEMBANGAN MEDIA PEMBELAJARAN VIDEO MENGGUNAKAN APLIKASI POWTOON PADA MATERI KARAKTERISTIK TRANSISTOR

Abstract: The product developed is a video learning media using a powtoon application on transistor characteristics. The development of this learning media is needed to assist teaching and learning activities during the pandemic, both online and offline learning. Online learning or non-face-to-face learning requires learning media that are easy to access and use. The purpose of research and development of this learning media is to produce a product in the form of ICT-based audiovisual learning media, namely video learning media using a powtoon application on transistor characteristics.This type of research uses the ADDIE development method. This method consists of 5 stages, namely Analysis, Design, Development, Implementation, Evaluation. The instrument used is an assessment questionnaire. There are two methods used: the first is an expert validation questionnaire with 2 assessments (material and media), this validation is used to assess the feasibility of the media, and the second is a student response questionnaire to assess the user's response to the developed media.Based on the results of the validation with the results of the percentage value of the feasibility of the tool, namely 93.35% for media experts with very feasible criteria, 92.7% for material expert validation with very feasible criteria and 75.78% for student responses with appropriate criteria. From the results of these data obtained an average percentage of 87.28% with proper criteria. Based on the exposure of the results of the product feasibility test and the practicality of the product, it can be concluded that the video learning media using the Powtoon application on transistor characteristics, teaching materials for integers and fractions with Islamic values is very feasible and practical to use for learning.Keywords: learning media; powderoon; transition; development

DTCO flow for air spacer generation and its impact on power and performance at N7

A novel DTCO flow is described with the principal aim to study the impact of air spacer fabrication on the power and performance of a 5-stage inverter ring oscillator at the 7 nm node. The flow incorporates physical and analytical process models from the in-house ViennaPS simulation tool together with device and circuit simulations from GTS Framework’s Cell Designer. The air spacer is usually filled by sequential conformal and non-conformal deposition steps. The impact of the thickness of the conformal layer and the sticking probability during non-conformal deposition on the ring oscillator performance is studied here. The air gap, which forms the core of the air spacer, is generated during the non-conformal deposition step. We extract the relative effective permittivity of the air spacer as a function of these two fabrication parameters by solving the Poisson equation to obtain the spacer capacitance. Finally, SPICE model cards are extracted automatically from the TCAD transistor characteristics and the parasitic network is calculated from the full 3D ring oscillator logic cell using a field solver. We apply our framework on two fabrication flows, when the air gap is created before and after the deposition of the first metal contacts layer. We observe that introducing the air gap inside the spacer results in an at-least 15% improvement in the ring oscillator’s performance, when the power is kept constant. Further improvements can be achieved by reducing the conformal layer thickness and increasing the sticking probability by increasing the chamber partial pressure or increasing the process temperature.