Transistor Characteristics Research Articles

Understanding Quasi-Static and Dynamic Characteristics of Organic Ferroelectric Field Effect Transistors.

Leveraging poly(vinylidene fluoride-trifluoroethylene) [(PVDF-TrFE)] as the dielectric, we fabricated organic ferroelectric field-effect transistors (OFe-FETs). These devices demonstrate quasi-static transfer characteristics that include a hysteresis window alongside transient phenomena that bear resemblance to synaptic plasticity-encapsulating excitatory postsynaptic current (EPSC) as well as both short-term and long-term potentiation (STP/LTP). We also explore and elucidate other aspects such as the subthreshold swing and the hysteresis window under dynamic state by varying the pace of voltage sweeps. In addition, we developed an analytical model that describes the electrical properties of OFe-FETs, which melds an empirical formula for ferroelectric polarization with a compact model. This model agrees well with the experimental data concerning quasi-static transfer characteristics, potentially serving as a quantitative tool to improve the understanding and design of OFe-FETs.

Bidirectional Synaptic Operations of Triple‐Gated Silicon Nanosheet Transistors with Reconfigurable Memory Characteristics

AbstractIn this study, a triple‐gated transistor with a p+‐i‐n+ silicon nanosheet (NS) is proposed as a single synaptic device, and bidirectional synaptic functions are realized using reconfigurable memory characteristics. The triple‐gated NS transistor features steep switching and bistable characteristics with a subthreshold swing below 5 mV dec−1 and an ON/OFF current ratio of ≈5 × 106 for both the n‐ and p‐channel modes. This transistor exhibits electrically symmetric reconfigurable memory characteristics with an ON current ratio of 1.02 for the n‐ and p‐channel modes. Moreover, the bidirectional synaptic weight updates of binarized spike‐timing‐dependent plasticity learning are successfully performed in a single transistor. This study demonstrates the potential of a triple‐gated NS transistor for achieving compact synaptic arrays in large‐scale silicon‐based neuromorphic computing systems.

Temperature-Dependent Feedback Operations of Triple-Gate Field-Effect Transistors.

In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of -200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel regions such that a positive feedback loop forms rapidly. Thus, the latch-up voltage shifts from -1.01 V (1.34 V) to -11.01 V (10.45 V) in the n-channel (p-channel) mode. In contrast, with decreasing temperature from 25 °C to -200 °C, the thermally generated charge carriers decrease, causing a shift in the latch-up voltage in the opposite direction to that of the increasing temperature case. Despite the shift in the latch-up voltage, the TG FBFETs exhibit ideal switching characteristics, with subthreshold swings of 6.6 mV/dec and 7.2 mV/dec for the n-channel and p-channel modes, respectively. Moreover, the memory window widens with increasing temperature. Specifically, at temperatures above 85 °C, the memory windows are wider than 3.05 V and 1.42 V for the n-channel and p-channel modes, respectively.

Variations in the characteristics of low-voltage logic gates based on vertical silicon nanotransistors with a conical channel

The issues of numerical simulation of fluctuations in the electro-physical characteristics of low-voltage logic gates based on silicon vertical nanotransistors with a surrounding gate with a conical geometry are discussed. Instrumentation and technological models of n- and p-types of conductivity of conical nanotransistors have been developed for the case when the conical working area is set as follows. On the source side, for a large diameter, the condition for suppressing short-channel effects is not fulfilled, and on the drain side, for a small diameter, it is fulfilled. Such transistor structures in the control voltage range from 0 to 0.6 V are characterized by a higher transistor current, a low leakage current and a slope of the subthreshold characteristic close to the theoretical limit. Prototypes of transistors with optimal parameters for the synthesis of logic gates with a gate length of 25 nm and a working area diameter ratio of 8.5/10 nm have been selected. The fluctuation range of the drain current is distributed according to the normal law for both types of transistors with an average of 12.25 µA for the n-type and 6.5 µA for the p-type and a standard deviation of 19.3. The total spread is 3.06 µA and 1.45 µA, or 25% and 22%, respectively. To offset the influence of the considered mechanisms, it is recommended to limit the level of doping of the drain/source regions and use relatively large cross-sections of the working area from the range of possible ones. This will ensure stable electro-physical characteristics of transistors with high parry of short-channel effects. An instrument-technological model of an inverter based on vertically arranged n- and p-type transistors with an optimized diameter ratio has been developed. Variations of electro-physical characteristics in the range of control voltages 0...0.6 V and a clock frequency of 20 GHz are numerically investigated. In all cases, the prototypes demonstrate picosecond delays and low power consumption. The valve model predicts a general fluctuation of switching times of 18% at average values of 1.6 and 0.8 ps, respectively, active power of 16% at an average value of 0.2 µW and static power of 11% at an average value of 0.7 pW. The results of the study can be used in the design of digital circuits to expand the SOA zone.

Growth of CuAlO2 on SiO2 under a layer-by-layer approach conducted by digitally processed DC sputtering and its transistor characteristics

A CuAlO2 (CAO) bottom gate top contact p-type thin film transistor (TFT) is demonstrated. The CAO thin film is synthesized through a digitally processed DC sputtering (DPDS) technique, employing a precise layer-by-layer (LBL) deposition strategy. X-ray diffraction analysis exhibited distinct peaks beyond 600 °C. The CAO film shows a dominant phase along the (004) plane at the elevated temperature of 990 °C. The fabricated CAO p-TFT exhibits field effect mobility of 4.1 cm2 V−1 s−1. In addition, the p-TFT characteristics were observed even in the as-deposited CAO film. The DPDS-assisted LBL approach offers a promising pathway for controlled stacking deposition routes in the growth of CAO thin films, enabling enhanced performance and device integration.

GaAsSb/InGaAs tunnel FETs using thick SiO2 mask for regrowth

The regrowth conditions for lateral tunnel FETs featuring heterojunctions involve a tradeoff between selective growth and heavy doping. This study mitigated the connection between single crystals on the InP layer and polycrystals on the SiO2 mask by significantly increasing the thickness of the SiO2 mask to surpass that of the growing GaAsSb layer. We successfully fabricated p-GaAsSb/i-InGaAs tunnel FETs using a thick SiO2 mask, wherein the carrier concentration of the p-GaAsSb source was 5 × 1019 cm−3, and the growth temperature was maintained at 500 °C. The observed current–voltage (I–V) characteristics exhibited an on/off ratio of 5 × 104 and demonstrated ambipolar current behavior, confirming the presence of a p-type source. However, the observed subthreshold swing (SS) was limited to 120 mV dec−1. In comparison with the I–V characteristics of the planar transistor, degradation of SS can be explained by interface state, and the factor that characterizes the change of the drain current with the surface potential dΨs/d(log10ID) is estimated as 52 mV dec−1.

Electrical Characteristics of H-Diamond Transistors With ZrO2/Zr Stacked Dielectrics Deposited by Electron Beam Evaporation

Electrical Characteristics of H-Diamond Transistors With ZrO₂/Zr Stacked Dielectrics Deposited by Electron Beam Evaporation

Output breakdown characteristics of amorphous InGaZnO thin-film transistors at high gate voltage

Output characteristics of top-gate amorphous InGaZnO thin-film transistors are investigated at high gate voltage. With the increasing drain voltage, an output breakdown crops up closely following a drastic uprush of drain current. Such dramatically elevated drain current derives from the self-heating (SH) effect-generated channel donors. Measured at different high gate voltages, the output breakdown occurs in either linear or saturation regime, respectively, corresponding to normally-on and normally-off transfer curve, while the SH-triggering powers are almost identical. The conductor-like channel originates from the SH-induced high donor population, while the disconnection between channel and drain is caused by a highly defective region near drain, where the hot-carrier damage is violently activated by the SH-induced high temperature and the high drain electric field in saturation regime.

Ferroelectric 2D SnS2 Analog Synaptic FET.

In this study, the development and characterization of 2D ferroelectric field-effect transistor (2D FeFET) devices are presented, utilizing nanoscale ferroelectric HfZrO2 (HZO) and 2D semiconductors. The fabricated device demonstrated multi-level data storage capabilities. It successfully emulated essential biological characteristics, including excitatory/inhibitory postsynaptic currents (EPSC/IPSC), Pair-Pulse Facilitation (PPF), and Spike-Timing Dependent Plasticity (STDP). Extensive endurance tests ensured robust stability (107 switching cycles, 105 s (extrapolated to 10 years)), excellent linearity, and high Gmax /Gmin ratio (>105 ), all of which are essential for realizing multi-level data states (>7-bit operation). Beyond mimicking synaptic functionalities, the device achieved a pattern recognition accuracy of ≈94% on the Modified National Institute of Standards and Technology (MNIST) handwritten dataset when incorporated into a neural network, demonstrating its potential as an effective component in neuromorphic systems. The successful implementation of the 2D FeFET device paves the way for the development of high-efficiency, ultralow-power neuromorphic hardware which is in sub-femtojoule (48 aJ/spike) and fast response (1 µs), which is 104 folds faster than human synapse (≈10ms). The results of the research underline the potential of nanoscale ferroelectric and 2D materials in building the next generation of artificial intelligence technologies.

Electrochemical Analysis of Ion Effects on Electrolyte-Gated Synaptic Transistor Characteristics.

Electrolyte-gated transistors (EGTs) are promising candidates as artificial synapses owing to their precise conductance controllability, quick response times, and especially their low operating voltages resulting from ion-assisted signal transmission. However, it is still vague how ion-related physiochemical elements and working mechanisms impact synaptic performance. Here, to address the unclear correlations, we suggest a methodical approach based on electrochemical analysis using poly(ethylene oxide) EGTs with three alkali ions: Li+, Na+, and K+. Cyclic voltammetry is employed to identify the kind of electrochemical reactions taking place at the channel/electrolyte interface, which determines the nonvolatile memory functionality of the EGTs. Additionally, using electrochemical impedance spectroscopy and qualitative analysis of electrolytes, we confirm that the intrinsic properties of electrolytes (such as crystallinity, solubility, and ion conductivity) and ion dynamics ultimately define the linearity/symmetricity of conductance modulation. Through simple but systematic electrochemical analysis, these results offer useful insights for the selection of components for high-performing artificial synapses.

Modulating Electrical Characteristics of ZnO Thin-Film Transistors by Scaling Down Gate Dielectric Thickness

Modulating Electrical Characteristics of ZnO Thin-Film Transistors by Scaling Down Gate Dielectric Thickness

Improved dynamic characteristics of oxide electrolyte-gated transistor for time-delayed reservoir computing

Time-delayed reservoir computing (RC) equipped with prominent superiorities such as easy training and friendly hardware implementation is identified as a high-efficient answer to complex temporal tasks, and thereby draws increasing attention. Oxygen ion-based oxide electrolyte-gated transistor (Ox-EGT) with rich ion dynamic characteristics is deemed as a promising candidate for RC. However, it is still a challenge to produce the required dynamic characteristics for RC implementation. Herein, we develop an Ox-EGT with an oxygen vacancy-electron-coupled electric-double-layer at the electrolyte/channel interface to implement time-delayed RC. Effects of oxygen vacancy concentration on the short-term plasticity are investigated, revealing the optimal concentration range of oxygen vacancies for the dynamic characteristics improvement. The underlying physical mechanism is demonstrated by TCAD simulations. Simulations using the waveform classification and handwritten-digit recognition tasks validate the good information processing ability of the Ox-EGT RC system. These results provide a promising approach to exploit Ox-EGT dynamics for large-scale and energy-efficient neuromorphic computing hardware.

Incorporation of total ionizing dose effects into a compact model for p-GaN gate high electron mobility transistors

Total ionizing dose (TID) characteristics of p-GaN gate high electron mobility transistors (HEMTs) under different bias conditions are explored in this work. Potential mechanism accounting for the TID response of p-GaN gate HEMTs is analyzed, based on which a TID effects model is developed. The TID effects model describes the relationship among threshold voltage of p-GaN gate HEMTs, total radiation dose, and electric field inside the p-GaN cap layer. Furthermore, an approach incorporating the TID effects model into Advanced Spice Model for HEMT (ASM-HEMT) is proposed, the reliability of which is validated by the well-fitted modeled results in comparison with the measured ones. This approach makes it possible to probe into the impact of TID effects on p-GaN gate HEMTs from the perspective of circuit level, which provides a basis for the follow-up GaN-based circuit design.

Control of Polar/Antipolar Layered Organic Semiconductors by the Odd-Even Effect of Alkyl Chain.

Some rodlike organic molecules exhibit exceptionally high layered crystallinity when composed of a link between π-conjugated backbone (head) and alkyl chain (tail). These molecules are aligned side-by-side unidirectionally to form self-organized polar monomolecular layers, providing promising 2D materials and devices. However, their interlayer stacking arrangements have never been tunable, preventing the unidirectional arrangements of molecules in whole crystals. Here, it is demonstrated that polar/antipolar interlayer stacking can be systematically controlled by the alkyl carbon number n, when the molecules are designed to involve effectively weakened head-to-head affinity. They exhibit remarkable odd-even effect in the interlayer stacking: alternating head-to-head and tail-to-tail (antipolar) arrangement in odd-n crystals, and uniform head-to-tail (polar) arrangement in even-n crystals. The films show excellent field-effect transistor characteristics presenting unique polar/antipolar dependence and considerably improved subthreshold swing in the polar films. Additionally, the polar films present enhanced second-order nonlinear optical response along normal to the film plane. These findings are key for creating polarity-controlled optoelectronic materials and devices.

Optimization of electrothermal response of GAAFET using Taguchi's approach and an artificial neural network

This work aims to propose a numerical optimization of the electrothermal behavior of a gate-all-around field effect transistor (GAAFET). The electrothermal model is composed of semiconductor equations coupled with heat conduction equations. The finite element method was adopted for the discretization of equations describing the electrothermal model. The effects of geometric and electrical parameters such as gate length (Lg), oxide thickness (tox), nanowire radius (R), trap density (Nt), ramp parameter (α),gate voltage (Vg), and drain voltage (Vd) were analyzed based on a Taguchi L27(37) orthogonal array. Optimization of the control factors was performed. Multiple linear and nonlinear regressions, as well as an artificial neural network, were used. Numerical analysis revealed that the overall optimal drain current and peak temperature device reach the maximum drain current with lower temperature. The analysis of variance shows that the maximum contribution (39 % for the drain current and 36 % for Tmax) is occupied by the ramp coefficient (α) while the other parameters have a small contribution (less than 3 %) to optimize the performance of the GAAFET transistor. The statistical analysis reveals that the developed artificial neural network model is efficient for the prediction of the electrical and thermal characteristics of the GAAFET transistor. The results of this study are promising for advancing our understanding of these innovative transistor technologies, enabling them to be efficiently integrated into the next generation of electronic products.

Area-selective chalcogenization of transition metals through graphene mask

Area-selection reactions have been extensively investigated to control or change physicochemical properties of substances with micro- or nanoscale precision. Several polymeric materials called photoresists have been used to mask and pattern the specific region, which can block chemical reactions or deposition. However, they are not suitable for certain chemical reaction since they are vulnerable to high temperature. Here, we report the graphene mask to achieve area-selective chalcogenization, which is performed at high temperature by chemical vapor deposition method. Due to its physicochemical properties, graphene does not allow chalcogen precursor gases to penetrate into metal films. Several characterizations are performed to prove the successful sulfurization and selenization of molybdenum and tungsten films. As an application, WS2 field-effect transistors with graphene mask are fabricated, and they show the typical characteristics of transistors successfully. Therefore, we expect that graphene-assisted area-selective reaction can be utilized for various fields such as semiconductors, sensors, and etc.

Physics-based modeling of surface potential and leakage current for vertical Ga2O3 FinFET

Gallium oxide (Ga2O3) is a promising ultra-wide bandgap material offering a large bandgap (>4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga2O3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga2O3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga2O3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga2O3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga2O3 power transistors.

Low voltage operation of organic thin-film transistor with atmospheric coating of high-k polymer dielectric

We investigated high-k polymers as gate dielectrics to develop an atmospheric-pressure process for organic transistors. A high-k terpolymer, p(VDF-TrFE-CFE), was formed by drop-casting. Self-assembled molecules (SAM) of triptycene derivatives have been utilized as surface modifiers for high-k gate dielectrics to improve the transistor characteristics. High-k terpolymers reduce the operating voltage of organic thin-film transistors (TFTs) by up to 2.5 V to their high capacities. Introducing a SAM onto the gate dielectric surface improved the organic TFTs’ mobility by more than three orders of magnitude. In addition, a terpolymer and a SAM can be formed simultaneously by drop-casting. This atmospheric processing of the gate dielectric is expected to contribute to organic electronics in large-area or mass production, such as roll-to-roll processes.

Investigation of Temperature Effects on the Characteristics of Bipolar Junction Transistor

Temperature rise on the electronic board can have a noticeable impact on the electronic circuit which result in some changes in the basic parameters of the circuit elements. The aim of this paper is to study and analyzes the effects of high temperature on the static and dynamic characteristics of a bipolar transistor. The research was carried out experimentally by studying and analyzing several parameters of the NPN BJT transistor type 2SC2120 at different temperatures. The obtained results showed that there is a significant increase in collector current from 0.19 A to 0.23 A and current gain from 0.14 to 0.22 by increasing the temperature from 25°C to 130°C. As for the threshold voltage, it was found that its value decreased from 0.6 volts to 0.4 volts. The results obtained also indicate that for the dynamic properties, the diffusion capacitance of the emitter-base junction, increased from 10.1 nF to 45.02 nF by increasing the temperature up to 130°C. Finally, it was found that the reverse capacitance of the gate-drain junction increased from 41.4 pF to 47.3 pF under the same temperature ranges.

Correlation Between Quantum Confinement Effect and Characteristics of Thin-Film Transistors in Solution-Processed Oxide-Based Thin-Films

Correlation Between Quantum Confinement Effect and Characteristics of Thin-Film Transistors in Solution-Processed Oxide-Based Thin-Films