Characteristics Of Flash Memory Research Articles

Review of neuromorphic computing based on NAND flash memory.

The proliferation of data has facilitated global accessibility, which demands escalating amounts of power for data storage and processing purposes. In recent years, there has been a rise in research in the field of neuromorphic electronics, which draws inspiration from biological neurons and synapses. These electronics possess the ability to perform in-memory computing, which helps alleviate the limitations imposed by the 'von Neumann bottleneck' that exists between the memory and processor in the traditional von Neumann architecture. By leveraging their multi-bit non-volatility, characteristics that mimic biology, and Kirchhoff's law, neuromorphic electronics offer a promising solution to reduce the power consumption in processing vector-matrix multiplication tasks. Among all the existing nonvolatile memory technologies, NAND flash memory is one of the most competitive integrated solutions for the storage of large volumes of data. This work provides a comprehensive overview of the recent developments in neuromorphic computing based on NAND flash memory. Neuromorphic architectures using NAND flash memory for off-chip learning are presented with various quantization levels of input and weight. Next, neuromorphic architectures for on-chip learning are presented using standard backpropagation and feedback alignment algorithms. The array architecture, operation scheme, and electrical characteristics of NAND flash memory are discussed with a focus on the use of NAND flash memory in various neural network structures. Furthermore, the discrepancy of array architecture between on-chip learning and off-chip learning is addressed. This review article provides a foundation for understanding the neuromorphic computing based on the NAND flash memory and methods to utilize it based on application requirements.

Neural Network-Based prediction for Cross-Temperature induced VT distribution shift in 3D NAND flash memory

In this study, a neural network (NN) was proposed for predicting the VT characteristics of NAND flash memories under cross-temperature conditions. The training data were obtained from commercial NAND flash memory chip measurements at various temperatures. The VT distribution shift caused by cross-temperature was accurately predicted by investigating the optimum data dimensions while minimizing the data generation process. Two types of NNs were used to achieve an accurate VT distribution prediction, and each network was optimized using specific parameters based on the data characteristics at various program verify levels. Finally, quantitative and visual evaluations were conducted to verify the performance of the trained NNs. When the program-measured temperature varied from low to high, the NNs achieved mean errors of 1.87%, 1.41% at low and 0.34%, 0.77% at high for the average and width of the VT distribution, respectively. Similarly, when the temperature varied from high to low, the corresponding mean errors were 2.01%, 0.74% at high and 0.23%, 1.59% at low. These findings demonstrate that NNs can minimize the procedures for detecting the VT distribution shift caused by cross-temperature, thereby offering a promising approach to enhance reliability in the presence of such effects.

Critical Data Backup with Hybrid Flash-Based Consumer Devices

Hybrid flash-based storage constructed with high-density and low-cost flash memory has become increasingly popular in consumer devices in the last decade due to its low cost. However, its poor reliability is one of the major concerns. To protect critical data for guaranteeing user experience, some methods are proposed to improve the reliability of consumer devices with non-hybrid flash storage. However, with the widespread use of hybrid storage, these methods will result in severe problems, including significant performance and endurance degradation. This is caused by the fact that the different characteristics of flash memory in hybrid storage are not considered, e.g., performance, endurance, and access granularity. To address these problems, a critical data backup (CDB) design is proposed to ensure critical data reliability at a low cost. The basic idea is to accumulate two copies of critical data in the fast memory first to make full use of its performance and endurance. Then, one copy will be migrated to the slow memory in the stripe to avoid the write amplification caused by different access granularity between them. By respecting the different characteristics of flash memory in hybrid storage, CDB can achieve encouraging performance and endurance improvement compared with the state-of-the-art. Furthermore, to avoid performance and lifetime degradation caused by the backup data occupying too much space of fast memory, CDB Pro is designed. Two advanced schemes are integrated. One is making use of the pseudo-single-level-cell (pSLC) technique to make a part of slow memory become high-performance. By supplying some high-performance space, data will be fully updated before being evicted to slow memory. More invalid data are generated which reduces eviction costs. Another is to categorize data into three types according to their different life cycles. By putting the same type of data in a block, the eviction efficiency is improved. Therefore, both can improve device performance and lifetime based on CDB. Experiments are conducted to prove the efficiency of CDB and CDB Pro. Experimental results show that compared with the state-of-the-arts, CDB can ensure critical data reliability with lower device performance and lifetime loss whereas CDB Pro can diminish the loss further.

PcGC: A Parity-Check Garbage Collection for Boosting 3-D NAND Flash Performance

Garbage collection or GC running in the controller of 3D NAND flash-based solid-state disks -SSDs -plays a critical role in the performance of storage systems. SSD manufacturers have developed various garbage collection solutions based on internal data movement or IDM to mitigate the impacts of garbage collection on request latency. Due to the circuit characteristics of flash memory, existing IDM-based garbage collection strategies are restricted by the page parity during data movement: odd pages must be migrated to odd pages, and even pages to even pages. When migrating two consecutive pages with the same parity, the free page between the two migrated pages will be wasted after the migration is complete. This ever-increasing page waste problem inevitably deteriorates the storage space utilization of flash memory, thereby degrading the overall performance of 3D NAND flash-based SSDs. To address this issue, we propose a parity-check garbage collection scheme called PcGC to revamp SSD performance by alleviating page waste during garbage collection. We build a parity-check unit in PcGC to facilitate checking the parity of migrated valid pages and destination pages. According to the parity results offered by the parity-check unit, PcGC dynamically adjusts the migration order of valid pages during the course of garbage collection. In doing so, PcGC fundamentally averts page waste caused by the page parity restriction, thereby enhancing 3D NAND flash performance. We quantitatively evaluate the performance of PcGC in terms of wasted pages, storage utilization, GC counts, write amplification, and average response time. We compare PcGC against the two state-of-the-art schemes -Amphibian and TTflash. The experimental results derived from the nine real-world workload traces unfold that compared with Amphibian and TTflash, (1) PcGC curtails the number of wasted pages by up to 91.4% with an average of 53.75%, (2) cuts back the number of GC counts by up to 52.2% with an average of 11.9%, and (3) slashes average write response time by up to 77.8% with an average of 13.0%.

High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage

3D NAND flash memory is the ubiquitous non-volatile memory (NVM) on the market because of its large storage capacities, high reliability, and low bit-cost. The reliability characteristics of 3D NAND flash memory, however, are considerably different from those of 2D NAND flash memory due to the peculiar architectures. In this paper, read disturb (RD) at various program/erase (P/E) stages is thoroughly explored. To adjust the low-density parity check (LDPC) codes dynamically and extend the lifetime of 3D NAND flash memory, short-term lifetime prediction models of RD and endurance are proposed based on in-depth studies on the correlations of fail bit count (FBC) at various lifetime stages, and their accuracy is tested experimentally. A new short-term warning system (STWS) is proposed to extend the lifetime of 3D NAND-based storages. It consists of the error-bits’ prediction module (EBPM) and the self-adjustable low-density parity check codes module (SLDPC), where EBPM predicts FBC periodically and SLDPC pre-allocates LDPC codes for future use based on the result of EBPM. The experimental result shows that our prediction models have high reliability, and STWS can effectively prolong the lifetime of NAND flash. The findings of this study provide fundamental insights into FBC degradation in 3D NAND flash, as well as a simple and practical method for building 3D NAND-based storage with high reliability.

Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics

3D flash memories have been widely developed to further increase the storage capacity of SSDs by vertically stacking multiple layers. However, this special physical structure brings new error characteristics. Existing studies have discovered that there exist significant Raw Bit Error Rate (RBER) variations among different layers and RBER similarity inside the same layer due to the manufacturing process. These error characteristics would introduce a new data reliability issue. Currently, Low-Density Parity-Check (LDPC) code has been widely used to ensure the data reliability of flash memories. It can provide stronger error correction capability for high RBERs by trading with longer read latency. Traditional LDPC codes designed for planar flash memories do not consider the layer RBER characteristics of 3D flash memories, which may induce sub-optimal read performance. This article first investigates the effect of RBER characteristics of 3D flash memories on read performance and then obtains two observations. On one hand, we observe that LDPC read latencies are largely diverse in different flash layers and increase in diverse speeds along with data retention. This phenomenon is caused by the inter-layer RBER variation. On the other hand, we also compare RBERs between different pages of the same flash layer and observe that read latencies with LDPC codes are quite similar, which is caused by the intra-layer RBER similarity. Then, by exploiting these two observation results, this article proposes a Multi-Granularity LDPC (MG-LDPC) read method to adapt read latency increase characteristics across 3D flash layers. In detail, we design five LDPC decoding engines with varied read level increase granularity (higher level induces higher latency) and assign these engines to each layer dynamically according to prior information, or in a fixed way. A series of experimental results demonstrate that the fixed and dynamic MG-LDPC methods can reduce SSD read response time by 21% and 51% on average, respectively.

Light-/steam-driven polymeric crosslinking with porous multistructure pattern for ultrastable and fast-speed memory

Organic memories typically comprise memristive polymer mediums sandwiched between two electrodes, with the advantages of wet manufacturing and modulated function. However, the issues associated with structural instability, low-speed switch, and hard pattern in polymeric memories are the main obstacles towards practical uses. Here, we present an ultrastable and fast-speed memory array that uses amorphous polymer nanofilm with light-/steam-driven crosslinked porous multistructure as memristive materials. The polymer diode shows nonvolatile rewritable flash memory characteristics, with a high ON/OFF ratio, long retention time, and high speeds of set (70 ns) and reset (845 ns) operations. Impressively, the memory cell undergoes harsh conditions in ultraviolet irradiation and extreme temperatures. By rationally integrating the array with target sensors, an artificial sensory memory architecture is constructed to mimic visual/thermal perception and recording, demonstrating great potential for biomimetic neuromorphic electronics. Our results advance a commercial perspective on memristive organics capable of integration patterns and high performance.

LLSM: A Lifetime-Aware Wear-Leveling for LSM-Tree on NAND Flash Memory

The advancement of nonvolatile memory (NVM) technology reduces the cost-per-unit of solid-state drives (SSDs). Flash memory-based SSDs have become ubiquitous because they provide better performance and energy efficiency than hard disk drives. However, it suffers from wear-out problems caused by the out-of-place updates that limit its lifetime. Log-structured merge tree (LSM-tree) is a level-based data structure that is widely used in many database systems because it eliminates the random write operations to the storage devices. By transferring the random write operations into sequential write operations, the write performance of hard disk drives can be improved. However, LSM-tree is not efficient for SSDs because it is not aware of the access characteristics of flash memory. Moreover, the level-based indexing strategy of the LSM-tree significantly shortens the lifetime of SSDs because the data must be frequently updated due to the compaction operations between different levels. In contrast to many previous works that focus on alleviating the write amplification on SSDs for the database systems implemented by LSM-tree, we propose LLSM, a lifetime-aware wear-leveling for LSM-tree on NAND flash memory with open-channel SSD. By considering the data access frequency of the LSM-tree between different levels, LLSM rethinks the block allocation strategy during the compaction to evenly erase all the blocks of SSD storage devices, prolonging the SSD lifetime. Moreover, a proactive swapping strategy is designed to reorganize the data blocks for resolving the potential wear-leveling issues caused by the behaviors of the LSM-tree. The extensive experiments show that the results of lifetime improvement are encouraging.

Defending against OS-Level Malware in Mobile Devices via Real-Time Malware Detection and Storage Restoration

Combating the OS-level malware is a very challenging problem as this type of malware can compromise the operating system, obtaining the kernel privilege and subverting almost all the existing anti-malware tools. This work aims to address this problem in the context of mobile devices. As real-world malware is very heterogeneous, we narrow down the scope of our work by especially focusing on a special type of OS-level malware that always corrupts user data. We have designed mobiDOM, the first framework that can combat the OS-level data corruption malware for mobile computing devices. Our mobiDOM contains two components, a malware detector and a data repairer. The malware detector can securely and timely detect the presence of OS-level malware by fully utilizing the existing hardware features of a mobile device, namely, flash memory and Arm TrustZone. Specifically, we integrate the malware detection into the flash translation layer (FTL), a firmware layer embedded into the flash storage hardware, which is inaccessible to the OS; in addition, we run a trusted application in the Arm TrustZone secure world, which acts as a user-level manager of the malware detector. The FTL-based malware detection and the TrustZone-based manager can communicate with each other stealthily via steganography. The data repairer can allow restoring the external storage to a healthy historical state by taking advantage of the out-of-place-update feature of flash memory and our malware-aware garbage collection in the FTL. Security analysis and experimental evaluation on a real-world testbed confirm the effectiveness of mobiDOM.

Characterization Summary of Performance, Reliability, and Threshold Voltage Distribution of 3D Charge-Trap NAND Flash Memory

Solid-state drive (SSD) gradually dominates in the high-performance storage scenarios. Three-dimension (3D) NAND flash memory owning high-storage capacity is becoming a mainstream storage component of SSD. However, the interferences of the new 3D charge-trap (CT) NAND flash are getting unprecedentedly complicated, yielding to many problems regarding reliability and performance. Alleviating these problems needs to understand the characteristics of 3D CT NAND flash memory deeply. To facilitate such understanding, in this article, we delve into characterizing the performance, reliability, and threshold voltage ( V th ) distribution of 3D CT NAND flash memory. We make a summary of these characteristics with multiple interferences and variations and give several new insights and a characterization methodology. Especially, we characterize the skewed ( V th ) distribution, ( V th ) shift laws, and the exclusive layer variation in 3D NAND flash memory. The characterization is the backbone of designing more reliable and efficient flash-based storage solutions.

First-Principles Study of Defect Levels Caused by Transition Metal Atoms in Silicon Nitride for Non-Volatile Memory Applications

The silicon nitride-based charge trap memory architecture has been considered as one of the promising solutions for high-bit-density three-dimensional NAND-type flash memories [1]. In this architecture, electrons and holes are trapped by point defects distributed in silicon nitride. This phenomenon induces a shift of the threshold voltage of memory transistors and is applied to store data. Recently, multi-level cell technology has been introduced in NAND-type flash memories to increase the bit density, which has needed to enlarge the threshold voltage shift [2]. Thus, the increase in the density of the point defects which can generate deep trap levels in silicon nitride is demanded to realize the high-bit-density flash memories. In the present work, we investigate the energy levels caused by transition metal (Ti, V, or Mn) defects in silicon nitride using first-principles calculations.Amorphous silicon nitride film has been used as the charge trap layer in flash memories. The hexagonal β-Si3N4 crystalline phase is believed to have similar local structures as amorphous silicon nitride [3]. Therefore, to discuss the realistic nature of transition metal atoms in silicon nitride, a 168-atom supercell was formed by expanding a unit cell of β-Si3N4 phase in a 2x2x3 matrix on a-axis, b-axis, and c-axis, respectively. The structure optimization and self-consistent field (SCF) calculations were performed using Advance/PHASE ver. 3.5 software. The generalized-gradient approximation with the PBE functional was used for the exchange-correlation energy of electrons. The kinetic energy cutoffs for wavefunctions were 40, 52, 64, 76, and 88 Ry and those for charge density were 400, 520, 640, 760, and 880 Ry in the calculations. 2x2x4 k-points sampling in the Monkhorst-Pack grid was used to perform SCF calculations.The behavior of transition metal atoms in semiconductors and dielectrics has been widely studied. Shibata et al. explained the behavior of transition metal atoms in silicon nitride using density-functional theory (DFT) calculations in terms of formation energies [4]. However, there are few reports on the energy levels generated by transition metal atoms in silicon nitride. In the present work, the density of states (DOS) of electrons in four supercell structures of Si72N96, Si71N96Mn, Si71N96V, and Si71N96Ti have been investigated. The calculations with the conditions mentioned earlier have been performed on the supercells, where a transition metal atom (Ti, V, or Mn) was substituted for a Si atom.Figure 1(a) shows total DOS calculated for the supercell Si71N96Mn. We can see five different defect levels of energy 1.59, 1.91, 2.03, 3.00, and 3.12 eV below the bottom of the conduction band. From Atomic Layer DOS (ALDOS) calculation results, we have found that all five trap levels are mainly localized at the Mn atom. Some of these trap levels would be able to behave as deep electron trap levels.Total DOS calculated for the supercell Si71N96V is shown in Fig. 1(b). Similar to the Si71N96Mn, five different defect levels appeared. However, three levels close to the bottom of the conduction band in Si71N96V are shallower in energy as compared to those in Si71N96Mn. Electrons trapped by these shallow levels might be easily emitted to the conduction band. The emission of electrons from the defect levels would degrade the retention characteristics of flash memories. We also calculated total DOS for the supercell Si71N96Ti. No defect levels appeared in the forbidden gap of Si71N96Ti.In conclusion, we have performed the DFT calculations to investigate the defect levels generated by transition metal atoms (Ti, V, or Mn) in silicon nitride. The substitution of a Si atom with a Mn atom generated deep defect levels in the forbidden gap. Some of the defect levels can be expected to behave as deep trap levels for electrons. The doping of silicon nitride with Mn atoms would have potential for enhancing the carrier trapping properties of the silicon nitride charge trap layer. Further experimental studies would be needed to validate the effectiveness of doping of silicon nitride with Mn atoms to the enhancement of the charge trapping properties in flash memories.We would like to show our gratitude to K. Niisato, Y. Ota and T. Inushima for sharing their pearls of wisdom with us during the course of this research. This work was partly supported by JSPS KAKENHI Grant Number JP18K04244.[1] S. Inaba, 2018 IEEE Inte. Memory Workshop, Kyoto, 1 (2018).[2] K. Parat et al., 2018 IEEE Inter. Electron Devices Meeting, San Francisco, 2.1.1 (2018).[3] L. E. Hintzsche et al., Physical Review B., 86, 235204 (2012).[4] D. Shibata et al., ECS Transactions, 64(11), 229 (2014). Figure 1

LiveSSD: A Low-Interference RAID Scheme for Hardware Virtualized SSDs

Hardware virtualization has been increasingly used to provide performance isolation between multiple tenants sharing an SSD. It exploits the SSD's highly parallel architecture by allocating dedicated flash dies to each tenant. On the other hand, intra-SSD RAID, which stripes data and parity across flash dies, is essential to enhance storage reliability, such as protecting data against die failures and read errors. However, parity updates introduce I/O interference, degrading tenants' performance significantly, and violating performance isolation. To solve this problem, we propose a low-interference RAID scheme for hardware virtualized SSDs, called LiveSSD. Flash pages with the same offset across dies constitute a stripe in a RAID-4 manner. High-speed NVRAM is employed as parity storage. Thus, LiveSSD allows each tenant to read/write its flash die(s) independently and avoids parity updates being a performance bottleneck. Nonetheless, parity updates introduce I/O interference during garbage collection, i.e., extra reads of invalid flash pages. LiveSSD actively conducts parity updates in advance by utilizing both page access feature of flash memory and idle time in workloads. Extensive simulation results show that LiveSSD enables RAID protection in a hardware-virtualized SSD with minimum I/O interference caused by parity updates.

Devices with Tuneable Resistance Switching Characteristics Based on a Multilayer Structure of Graphene Oxide and Egg Albumen.

We used graphene oxide (GO) and egg albumen (EA) to fabricate bipolar resistance switching devices with indium tin oxide (ITO)/GO/EA/GO/Aluminum (Al) and ITO/EA/Al structures. The experimental results show that these ITO/GO/EA/GO/Al and ITO/EA/Al bio-memristors exhibit rewritable flash memory characteristics. Comparisons of ITO/GO/EA/GO/Al devices with 0.05 ωt %, 0.5 ωt %, and 2 ωt % GO in the GO layers and the ITO/EA/Al device show that the ON/OFF current ratio of these devices increases as the GO concentration decreases. Among these devices, the highest switching current ratio is 1.87 × 103. Moreover, the RESET voltage decreases as the GO concentration decreases, which indicates that GO layers with different GO concentrations can be adopted to adjust the ON/OFF current ratio and the RESET voltage. When the GO concentration is 0.5 ωt %, the device can be switched more than 200 times. The retention times of all the devices are longer than 104 s.

Exploiting Asymmetric Errors for LDPC Decoding Optimization on 3D NAND Flash Memory

By stacking layers vertically, the adoption of 3D NAND has significantly increased the capacity for storage systems. The complex structure of 3D NAND introduces more errors than planer flash. To address the reliability issue, low-density parity-check (LDPC) code with a strong error correction capability is now widely applied on 3D NAND flash memory. However, LDPC has long decoding latency when the raw bit error rates (RBER) are high. This is because it needs fine-grained soft sensing between voltage states to iteratively decode the raw data. Multiple sensing voltages are applied on flash cell array to gain necessary information for decoding. In this article, a new sensing level placement scheme with reduced number of sensing levels is proposed. The basic idea for the placement scheme is motivated by three asymmetric error characteristics of flash memory: the asymmetric errors between different states, the asymmetric errors caused by voltage left-shifts and right-shifts and asymmetric errors among layers in a 3D NAND flash block. With awareness of these three types of error characteristics, reduced number of sensing levels are placed to achieve reduced read latency for LDPC decoding while maintaining the error correction capability of LDPC. Experiment analysis shows that the proposed scheme achieves significant performance improvement.

DSFTL: An Efficient FTL for Flash Memory Based Storage Systems

Flash memory is widely used in solid state drives (SSD), smartphones and so on because of their non-volatility, low power consumption, rapid access speed, and resistance to shocks. Due to the hardware features of flash memory that differ from hard disk drives (HDD), a software called FTL (Flash Translation Layer) was presented. The function of FTL is to make flash memory device appear as a block device to its host. However, due to the erase before write features of flash memory, flash blocks need to be constantly availed through the garbage collection (GC) of invalid pages, which incurs high-priced overhead. In the previous hybrid mapping schemes, there are three problems that cause GC overhead. First, operation of partial merge causes more page copies than operation of switch merge. However, many authors just concentrate on reducing operation of full merge. Second, the availability between a data block and a log block makes the space availability of the log block lower, and it also generates a very high-priced operation of full merge. Third, the space availability of the data block is low because the data block, which has many free pages, is merged. Therefore, we propose a new FTL named DSFTL (Dynamic Setting for FTL). In this FTL, we use many SW (sequential write) log blocks to increase operation of switch merge and to decrease operation of partial merge. In addition, DSFTL dynamically handles the data blocks and log blocks to reduce the operations of erase and the high-priced operation of full merge. Additionally, our scheme prevents the data block with many free pages from being merged to increase the space availability of the data block. Our extensive experimental results prove that our proposed approach (DSFTL) reduces the count of erase and increases the operation of switch merge. As a result, DSFTL decreases the garbage collection overhead.

Synthesis, electrochromic properties and flash memory behaviors of novel D-A-D polyazomethines containing EDOT and thiophene units

A series of novel polyazomethines containing EDOT and thiophene units coded as PEDOTs (PEDOT-TPA, PEDOT-TDD, PEDOT-THIO, PEDOT-APM) and PTHIOs (PTHIO-TPA, PTHIO-TDD, PTHIO-THIO, PTHIO-APM) were synthesized successfully. They were gained in short time, low cost and mild reaction conditions by a straightforward synthetic path. It can be easily found from the electrochemical properties of these polymers that the polymers containing 3,4-ethylenedioxythiophene (EDOT) unit (PEDOTs) have lower initial oxidation potentials as compared to the polymers containing thiophene unit (PTHIOs). Spectroelectrochemical properties reveal that all of the polymer films exhibit outstanding multielectrochromic behaviors, distinct color contrast and excellent electrochemical stabilities. Kinetic studies show that the PEDOT-TPA film has the shortest response time (a color switching time of 4.54 s and a bleaching time of 3.88 s at 428 nm) and the PEDOT-THIO film exhibits the highest CE of 343.56 cm 2 C −1 . Typical I-V characteristics of the ITO/plymer/Al memory devices exhibit that all the memory devices based on PEDOTs and PTHIOs exhibited nonvolatile flash memory characteristics, with an ON/OFF current density ratio of 10 3 -10 4 and low threshold voltages (around 1 V). Thus, these characteristics illustrate that these novel polymers have great potential in optoelectronics applications as electrochromic materials and memory devices. • Eight kinds of novel polyazomethines were synthesized successfully by a straightforward synthetic path. • All of these polyazomethines exhibit outstanding electrochromic behavior and excellent electrochemical stability. • The polymers containing 3,4-ethylenedioxythiophene (EDOT) units (PEDOTs) have low initial oxidation potential. • Among these polymers, the PEDOT-TPA film has the shortest response time and the PEDOT-THIO film exhibits the highest CE. • All the memory devices exhibited nonvolatile flash memory characteristics.

A Flash-Based SSD Cache Management Scheme for High Performance Home Cloud Storage

In the home cloud environment, storage performance is the most important factors affecting the user experience. In order to improve storage performance, we introduce a technique for managing flash-based storage devices as a cache. Although there are various studies on the use of flash caches, we focus on managing read requests that take into account flash memory characteristics and destaging methods from solid state drive cache to hard disk drives (HDDs) to improve performance. In this paper, we propose a scheme for managing flash-based solid state cache (SSC) called hybrid unit 2level-least recently used to improve input/output performance of HDD-based storage. Through the proposed scheme, cache hit ratio is increased and the number of disk access is reduced by keeping frequently accessed pages in SSC. In addition, the disk head movement is reduced when pages are destaged to disk by grouping write requested pages with adjacent pages. The number of cached pages is dynamically adjusted according to the ratio of read and write requests to improve performance on various workloads. For performance evaluation, we implemented the proposed scheme in a trace-based simulator. Performance evaluation shows up to 51% reduction in execution time compared to existing representative schemes.

Exploiting flash memory characteristics to improve performance of RAIS storage systems

Redundant array of independent SSDs (RAIS) is generally based on the traditional RAID design and implementation. The random small write problem is a serious challenge of RAIS. Random small writes in parity-based RAIS systems generate significantly more pre-reads and writes which can degrade RAIS performance and shorten SSD lifetime. In order to overcome the well-known write-penalty problem in the parity-based RAID5 storage systems, several logging techniques such as Parity Logging and Data Logging have been put forward. However, these techniques are originally based on mechanical characteristics of the HDDs, which ignore the properties of the flash memory. In this article, we firstly propose RAISL, a flash-aware logging method that improves the small write performance of RAIS storage systems. RAISL writes new data instead of new data and pre-read data to the log SSD by making full use of the invalid pages on the SSD of RAIS. RAISL does not need to perform the pre-read operations so that the original characteristics of workloads are kept. Secondly, we propose AGCRL on the basis of RAISL to further boost performance. AGCRL combines RAISL with access characteristic to guide read and write cost regulation to improve the performance of RAIS storage systems. Our experiments demonstrate that the RAISL significantly improves write performance and AGCRL improves both of write performance and read performance. AGCRL on average outperforms RAIS5 and RAISL by 39.15% and 16.59% respectively.

A Behavioral Compact Model for Static Characteristics of 3D NAND Flash Memory

We present a behavioral compact model for static characteristics of 3D NAND flash memory for integrated circuits and system-level applications utilizing BSIM-CMG 110.0.0. This model is easy to implement, computationally efficient, fast, accurate, and effectively accounts for the different parasitic capacitance coupling effects applicable to the 3D geometry of the vertical channel Macaroni body charge-trap flash memory. The model parameter extraction methodology is simple and can be extended to reproduce the electrical behavior of different 3D NAND flash memory architectures (with different page size, dimension, or a number of stacked layers). We believe that the developed compact model would equip the circuit designers and system architects with an effective tool for design-exploration of 3D NAND flash memory devices for diverse unconventional analog applications.

DPW-LRU: An Efficient Buffer Management Policy Based on Dynamic Page Weight for Flash Memory in Cyber-Physical Systems

Owing to its high performance, small size, and low energy consumption, NAND flash memory has been extensively adopted in cyber-physical systems. However, the inherent characteristics of flash memory, including not-in-place update and asymmetric I/O latencies, present difficulties in the design of buffer management policies. In this paper, we propose an enhanced buffer management policy for the flash memory referred to as dynamic page weight least recently used (DPW-LRU), which considers temporal locality and simultaneously provides effective utilization of limited buffer resources. Page migration is further enhanced by identifying the page access mode and frequency while separating the buffer into two different regions. A novel eviction algorithm is also designed to reduce the write operations and maintain a high hit ratio of the buffer regions, combining dynamic temporal locality, real-time eviction cost, and recency of pages. The experimental results show that DPW-LRU improves the hit ratio by up to 8.3%, decreases the write operation by up to 22.6%, and reduces the overall latency by up to 18.8% relative to those of other state-of-the-art buffers management policies.