Transistor Channel Research Articles

Comparing surface modification methods for silicon nanowire field-effect transistor biosensors for diagnosis applications: A case study of cardiac troponin I

This study is a debut of a side-by-side comparison of different methods to modify the surfaces of the silica-based substrates for biosensor fabrication. The fabricated biosensors are assessed for the quantification of cardiac troponin I (cTnI), a biomarker of acute myocardial infarction, at ultralow concentrations and small increment resolution in human serum. To accomplish this, silica samples and silicon nanowire field-effect transistor (SiNWFET) channels were modified with (3-aminopropyl)triethoxysilane, 1-(3-aminopropyl)silatrane, and the mixed self-assembly monolayer of silane-polyethylene glycol (silane-PEG, constituting of silane-PEG-NH2 and silane-PEG-OH at the ratio of NH2:OH = 1:10). Afterwards, they were treated with glutaraldehyde to immobilize aptamer probes for cTnI aptasensor detection. Thereafter, the modified-silica samples were investigated for surface roughness and antifouling capability, whereas the SiNWFET aptasensors were employed to determine cTnI. Empirical data revealed that only the silane-PEG-modified samples provided a superior surface for probe immobilization and high antifouling capability for the PEG-SiNWFET aptasensors to determine cTnI at ultralow levels with high resolution in human serum. Therefore, surface modification with silane-PEG provided an option for the challenge of precise quantification of cTnI, as well as of other protein biomarkers, at ultralow levels in bio-samples using the FET-based biosensors.

A review on source and drain formation in FinFETs

Silicon chip technology has been developing in accordance with Moores Law since its inception. As the device size shrinks, the transistor channel also shrinks. But when the channel is reduced to a point where electrons are free to travel between the source and drain, the transistor loses its switching power and the logic circuit becomes useless. Therefore, 3D fin field effective transistors (FinFETs) was designed to address the issue. This article highlights that compared to 2D MOSFETs, how difficult the process of source and drain formation in 3D FinFETs. The discussion focuses on the ion implantation and annealing technologies within the fabrication process.

Liquid-gate 2D material-on-insulator transistors for sensing applications

This research investigates the use of 2D materials (specifically graphene) as active channel in liquid-gate transistors used as detectors of biological targets on functionalized surfaces. However, before these sensors can be effectively used, it is crucial to establish a reliable sensing platform within two-dimensional materials as active channels, and to evaluate the fabrication, lithography, and reliability of these devices. In this study, we analyzed the inter-device variability and reliability of the transistors, as well as the potential factors that may exacerbate these issues under operative conditions. We performed structural characterization to confirm the quality of the materials, followed by photolithography and processing to create liquid-gate sensors. We then conducted electrical evaluations of the devices, which revealed significant reliability issues and inter-device variability. To address these problems, we propose the use of an intergate-coupling effect that utilizes both front- and back-gates simultaneously. Our findings have important implications for the design and optimization of 2D materials-based liquid-gate sensors for biological applications.

Fabrication of Multi-Bit SRAMs Using Quantum Dot Channel (QDC)-Quantum Dot Gate (QDG) FET

This paper presents fabrication of multi-state inverters incorporating SiOx-cladded Si quantum dot in the channel and gate region of driver, load, and access transistors. Experimental characteristics are presented exhibiting 3-state behavior in Quantum-dot Channel (QDC)-Quantum-dot Gate (QDG) FETs having Si quantum dots. It is shown that QDC-QDG-FETs-based enhancement mode inverter configurations are the building blocks of a multi-bit static random access memory (SRAM). QDC-QDG-FETs exhibiting four states can also be used to implement compact 4-state logic and nonvolatile memories or random access nonvolatile memories.

Design and fabrication of nanometer measurement platform for better understanding of silicon mechanical properties

Semiconductor industry is experiencing unprecedented growth, still driven by Moore's law, which is continually delivering devices with improved performance at lower costs. The continuation of this development places the industry in a divergent trade-off between economic attractiveness, technological feasibility, and the need for further performance improvement. Since the mainstream semiconductor technologies are silicon-based, new disruptive innovations are needed to gain additional performance margins. The use of nanowires is the preferred approach for preserving electrostatic control in the MOS transistor channel, and the application of mechanical stress is a booster of carrier mobility. It is in this context that this paper presents the design, fabrication, theoretical modeling, and characterization of a measurement platform to characterize the mechanical tensile stress of extremely narrow Si nanowires as small as 14.2 ± 1.12 nm in width. The proposed measurement platform enables a precise control of uniaxial strain, in terms of both amplitude and location, through the implementation of a stoichiometric Si3N4 pulling strand exerting a high tensile force on silicon nanowires. Reported devices are fabricated using a silicon-on-insulator wafer with fully complementary metal–oxide–semiconductor-compatible processing and top-down approach. It is observed that the mechanical strength of nanostructured Si is size-dependent and increases with miniaturization. Characterization revealed a record tensile strength value of 7.53 ± 0.8% (12.73 ± 1.35 GPa) for the narrowest nanowires fabricated using a top-down approach.

InZnTiON Channel Layer for Highly Stable Thin-Film Transistors and Light-Emitting Transistors.

In this study, we incorporated TiN as a carrier suppressor into an amorphous InZnO channel to achieve stable channels for thin-film transistors (TFTs) and light-emitting transistors (LETs). The low electronegativity and standard electrode potential of the Ti dopant led to a reduction in the number of oxygen vacancies in the InZnO channel. Moreover, the substitution of nitrogen into the oxygen sites of InZnO effectively decreased the excess electrons. As a result, the cosputtering of the TiN dopant resulted in a decrease in the carrier concentration of the InZnO channel, serving as an effective carrier suppressor. Due to the distinct structures of TiN and InZnO, the TiN-doped InZnO channel exhibited a completely amorphous structure and a featureless surface morphology. The presence of oxygen vacancies in the InZnO channel creates trap states for electrons and holes. Consequently, the TFT with the InZnTiON channel demonstrated an improved subthreshold swing and enhanced stability during the gate bias stress test. Furthermore, the threshold voltage shift (ΔVth) changed from 3.29 to 0.86 V in the positive bias stress test and from -0.92 to -0.09 V in the negative bias stress test. Additionally, we employed an InZnTiON channel in LETs as a substitute for organic semiconductors. The reduction in the number of oxygen vacancies effectively prevented exciton quenching caused by hole traps within the vacancies. Consequently, appropriate TiN doping in the InZnO channel enhanced the intensity of the LET devices.

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

AbstractWith continuous size scaling, the surface dangling bonds and short‐channel effects will degrade silicon based transistor performance. Thus, it is of great importance to seek new channel materials and transistor architectures to further continue Moore's law. Herein, a new ultra‐thin short‐channel tunneling transistor is developed comprising all 2D‐ components. Distinct from usual 2D planar transistor, this device is configured with vertical MoS2/WSe2 junction and in‐plane WSe2 channel, the switch states are realized by the gate‐regulated barrier height of heterojunction, enabling the transition of transport mechanism between thermionic‐emission and tunneling. Under dual‐gate configuration, the transistor exhibits high performance with drive current of 4.58 µA, on/off ratio of 4 × 107, subthreshold swing (SS) of 97 mV decade−1 and drain‐induced barrier lowering (DIBL) of 12 mV V−1, that can meet the requirement of logical applications in integrated circuits (IC). Taking advantage of the high‐speed tunneling current and unique short‐channel architecture, the device overcomes the issues of voltage spikes and long reverse recovery time that exist in usual electric components, and thus gains an access to the IC interface. This work provides a proof‐of‐concept transistor architecture relying on dual‐gate modulation, opening up a promising perspective for next generation low‐power, high‐density, and large‐scale IC technologies.

PHOTOSENSITIVE FIELD-EFFECT TRANSISTOR BASED ON REDUCED GRAPHENE OXIDE FILM

A photosensitive graphene field-effect transistor was created by depositing a reduced graphene oxide (rGO) film on the surface of the SiO2 layer on a silicon substrate, which serves as both a photosensitive medium and the field-effect transistor gate. The electrical and photoelectric properties of the field-effect transistor based on the rGO film were studied in DC and AC modes. Linear sections of the drain current on the gate voltage dependence and significant dependence of the electronic component of the rGO film conductivity on the irradiation with white light were revealed based on the analysis of the switching characteristics of the obtained field-effect transistor. A photoinduced decrease in the internal resistance and an increase in the capacitance of the conducting channel of the graphene field-effect transistor in the range of 102–105 Hz were revealed. It has been established that the photoresponse time of the obtained field-effect transistor to light pulses of IR, visible, and UV radiation is about 1.5 ms. The obtained results can be used to simplify the technology of manufacturing photodetectors based on graphene.

Single-Gate In-Transistor Readout of Current Superposition and Collapse Utilizing Quantum Tunneling and Ferroelectric Switching.

In nanostructure assemblies, the superposition of current paths forms microscopic electric circuits, and different circuit networks produce varying results, particularly when utilized as transistor channels for computing applications. However, the intricate nature of assembly networks and the winding paths of commensurate currents hinder standard circuit modeling. Inspired by the quantum collapse of superposition states for information decoding in quantum circuits, the implementation of analogous current path collapse to facilitate the detection of microscopic circuits by modifying their network topology is explored. Here, the superposition and collapse of current paths in gate-all-around polysilicon nanosheet arrays are demonstrated to enrich the computational resources within transistors by engineering the channel length and quantity. Switching the ferroelectric polarization of Hf0.5 Zr0.5 O2 gate dielectric, which drives these transistors out-of-equilibrium, decodes the output polymorphism through circuit topological modifications. Furthermore, a protocol for the single-electron readout of ferroelectric polarization is presented with tailoring the channel coherence. The introduction of lateral path superposition results into intriguing metal-to-insulator transitions due to transient behavior of ferroelectric switching. This ability to adjust the current networks within transistors and their interaction with ferroelectric polarization in polycrystalline nanostructures lays the groundwork for generating diverse current characteristics as potential physical databases for optimization-based computing.

Plasma wave resonances in Graphene channels under controlled gate for high frequency applications

Several devices based on 2D materials have become interesting for high-frequency applications especially sensors, amplifiers and modulators of Terahertz frequencies. Moreover, High Electron Mobility Transistors (HEMTs) have emerged as important competitors owing to the high quality of resonances associated with plasma-wave oscillations in the channel. In this study, the plasma wave resonances in a Graphene channel of High Electron Mobility Transistors (HEMTs) were studied. The calculations were based on our small-signal model and therefore can determine the resonances and voltage gain of the Monolayer and Bilayer graphene channels. The influence of the dielectric substrates between the gate and the channel, impurity depth positions and channel materials (InGaAs, Bilayer and Monolayer graphene) on the dynamic behavior of the Graphene transistor was investigated. This analysis can extract the high performance conditions of HEMTs Graphene amplifiers.

Potential of Transition Metal Dichalcogenide Transistors for Flexible Electronics Applications

AbstractSemiconducting transition metal dichalcogenides (TMDC) are 2D materials, combining good charge carrier mobility, ultimate dimension down‐scalability, and low‐temperature integration. These properties make TMDCs interesting for flexible electronics, where the thermal fabrication budget is strongly substrate limited. In this perspective, an overview of the state of TMDC research is provided by evaluating two scenarios, both with their own merit depending on the target application. First, high‐quality chemically grown 2D TMDCs are promising for nanoscale high‐performance and high‐frequency devices with excellent gate control and high current on/off ratios. Second, TMDC thin films can also be solution deposited from chemically exfoliated flakes allowing for moderate performance, but providing a path toward low‐cost production. A strong advantage of TMDCs is the possibility to realize p‐type and n‐type channels for complementary transistors having similar performance figures‐of‐merit. This aspect, as well as common transistor performance metrics are also compared with other flexible channel materials providing an overview of the state of the art of thin‐film transistors in the field of flexible electronics.

Single-Charge Tunneling in Codoped Silicon Nanodevices.

Silicon (Si) nano-electronics is advancing towards the end of the Moore's Law, as gate lengths of just a few nanometers have been already reported in state-of-the-art transistors. In the nanostructures that act as channels in transistors or depletion layers in pn diodes, the role of dopants becomes critical, since the transport properties depend on a small number of dopants and/or on their random distribution. Here, we present the possibility of single-charge tunneling in codoped Si nanodevices formed in silicon-on-insulator films, in which both phosphorus (P) donors and boron (B) acceptors are introduced intentionally. For highly doped pn diodes, we report band-to-band tunneling (BTBT) via energy states in the depletion layer. These energy states can be ascribed to quantum dots (QDs) formed by the random distribution of donors and acceptors in such a depletion layer. For nanoscale silicon-on-insulator field-effect transistors (SOI-FETs) doped heavily with P-donors and also counter-doped with B-acceptors, we report current peaks and Coulomb diamonds. These features are ascribed to single-electron tunneling (SET) via QDs in the codoped nanoscale channels. These reports provide new insights for utilizing codoped silicon nanostructures for fundamental applications, in which the interplay between donors and acceptors can enhance the functionalities of the devices.

Plasma instability and amplified mode switching effect in THz field effect transistors with a grating gate

We developed a theory of collective plasma oscillations in a dc current-biased field effect transistor with an interdigitated dual grating gate and demonstrated a new mechanism of electron plasma instability in this structure. The instability in the plasmonic crystal formed in the transistor channel develops due to conversion of the kinetic energy carried by the drifting plasmons into electromagnetic energy. The conversion happens at the opposite sides of the gate fingers due to the asymmetry produced by the current flow, and occurs through the gate finger fringing capacitances. The key feature of the proposed instability mechanism is the behavior of the plasma frequency peak and its width as functions of the dc current bias. At a certain critical value of the current, the plasma resonant peak with a small instability increment experiencing redshift with increasing current changes to the blue-shifting peak with a large instability increment. This amplified mode switching effect has been recently observed in graphene-interdigitated structures. The obtained theoretical results are in very good qualitative agreement with these experiments and can be used in future designs of the compact sources of THz electromagnetic radiation.

Effect of structure on semiconducting properties of a small molecule n-type organic semiconductor: Phenyl-C61-butyric acid methyl ester

The fullerene-based derivative phenyl-C61-butyric acid methyl ester (PCBM) has attracted attention as an n-type transistor channel and an organic photovoltaic material due to its solution processability, stability, and high electron mobility. However, disorder in solution-processed PCBM thin films makes understanding of charge carrier transport mechanisms difficult. We have fabricated PCBM-based field effect transistors and improved device performance by reducing electron trapping at the dielectric–semiconductor interface and improving charge carrier injection. Single-wall carbon nanotubes were successfully integrated into conventional gold electrodes to improve injection efficiency. Meyer–Neldel behavior has been investigated in a study of charge carrier transport in PCBM thin films. Crystallization of PCBM was observed during the measurement. We find that charge carriers hop between molecules in mostly amorphous regions from 145 to 240 K. The transport is facilitated by the formation of more crystallized regions when samples are heated as high as 240 K.

Write-Once-Read-Many-Times Memory Characteristics with a Large Memory Window Operating at a Low Voltage by Li-Ion Incorporation from the LiCoOx Ion-Supplying Layer into the InGaZnO Channel of a Thin-Film Transistor

Write-once-read-many-times (WORM) memory characteristics with a large memory window are demonstrated in a thin-film transistor (TFT) composed of an indium-gallium-zinc oxide (IGZO) channel and a lithium-cobalt oxide (LiCoOx) ion-supplying layer in the gate oxide. While the device with a thicker (5 nm) tunneling oxide showing a threshold voltage shift (ΔVT) of about 5 V by electron charging upon positive gate voltage (VGS) sweep to +25 V, the device with a 2 nm-thick tunneling oxide exhibits a large memory window with ΔVT > 20 V by Li-ion migration from LiCoOx to IGZO channel, which can be controlled as multilevel states with respect to the VGS amplitude. Incorporation of Li ions into the IGZO channel acting as p-type dopants reduces carrier concentration in the channel and consequently increases VT. The increased VT and the consequently reduced drain current are not instantly restored back by applying negative VGS, featuring WORM memory characteristics. Although the device undergoes partial retention loss, the retention remains up to about 90% after 100 min of retention time. These results verify WORM memory operations in the IGZO TFTs through gate voltage-driven Li-ion incorporation into the IGZO channel to modify its conductive states instead of using a typical electrical charging route.

ИНЖЕКЦИОННО-ПОЛЕВАЯ СТРУКТУРА, ВЫПОЛНЕННАЯ ДВОЙНОЙ ДИФФУЗИЕЙ ПРИМЕСЕЙ

In the 80s of the last century, integrated injection logic (I2L) was widely used as an elementbase. Somewhat later, in the development of I2L, injection-field logic (IPL) appeared for the constructionof VLSI. Both element bases are close in the degree of integration on a chip. An increase inthe degree of integration into VLSI can be achieved using self-displacement of regions, in which theintroduction of impurities of different types is carried out using a single boundary of the maskingmaterial. In this paper, this principle is used to create a vertical channel of a key field-effect transistorof IPL logic. In a p-type epitaxial film deposited on an n+-type substrate, an n-type region with adepth greater than the thickness of the epitaxial film is sequentially created first, and then impuritydiffusion is performed in the same window with the creation of a region p-type. The gap betweenthese n-type regions is the channel of the field-effect transistor being formed. Next, a shallow n+-typeregion is created that overlaps the channel, which is the drain region of a key field-effect transistorwith a vertical channel, the p-type diffusion region is a gate, and the uniformly alloyed region of theepitaxial film performs the function of an injector. Branching along the outlet in this IPL structure isprovided by placing several drains along the perimeter of the channel. Due to this geometry, thestructure has a greater reproducibility of parameters compared to the basic design of the IPL. Topologicalvariants of the implementation of the IPL cell and schemes based on it are considered:schemes 6 OR-NOT and Dt-trigger. The proposed design and technological version of the IPL cellcan be recommended for creating VLSI of a high degree of integration

Multilayer Porous Polymer Films for High‐Performance Stretchable Organic Electrochemical Transistors

AbstractPorous films offer a general and simple strategy for balancing the electron/hole transport, and ion doping/dedoping process in organic electrochemical transistor (OECT) channel. Here a universal 3D integrated approach that simultaneously achieves both enhanced transconductance (gm) and mechanical stretchability via constructing a multilayer breath‐figured porous polymer channel by poly(3‐hexylthiophene) (P3HT)/ polystyrene‐block‐poly(ethylene‐ran‐butylene)‐block‐polystyrene (SEBS) and poly(2,5‐bis(3‐triethyleneglycoloxythiophen‐2‐yl)‐co‐thiophene) (Pg2T‐T)/SEBS mixture is demonstrated. The formed multilayer elastic porous structure provides efficient and tunable ionic‐electronic coupling and transport pathways, while also introducing immunity toward mechanical tensile deformation. Remarkably, an obvious increase in gm [from 10.05 mS (2.13 mS) to 29.23 mS (7.38 mS) for Pg2T‐T (P3HT)] is acquired by assembling the OECT porous channel from a single layer to a 3D trilayer. Moreover, mechanical stretchability as high as 40% for Pg2T‐T and 60% for P3HT, is obtained with >21% gm retained. Furthermore, high gms (9.34 mS and 0.92 mS for Pg2T‐T and P3HT, respectively) are maintained after 600 stretching cycles (20% and 30% tensile strains for Pg2T‐T and P3HT, respectively). Overall, the 3D porous structure provides an effective strategy to enhance stretchability and electrical performance for OECTs, as well as opens possibilities for other electronics where both stretchability and a large surface‐to‐volume ratio are needed.

Outstanding intrinsic carrier mobility and transport properties of environmentally stable MX (M=Ga, In; X= S, Se, Te) atomic nanowires

Structural stability, electronic, and transport properties of metal monochalcogenides MX (M = Ga, In; X = S, Se, Te) atomic nanowires have been systematically investigated. To address the effects of the environment on the stability of the nanowires in experimental settings the nanowires are exposed to environmental oxygen. Based on the first-principle calculations, we confirm the energetic, dynamic, and environmental stability of chalcogenides nanowires exhibiting semiconducting nature and bandgaps in the visible region. The electron carrier mobility for InSe, GaTe, and InS nanowires is predicted to be 32,778 cm2 V−1 s−1, 3541 cm2 V−1 s−1, and 1173 cm2 V−1 s−1, respectively, which is higher than the corresponding 2D monolayer and MoS2. The modulations in geometrical parameters are captured using simulated STM analysis. Negative differential conductance predicted for GaTe and InSe nanowires can be used as a marker to characterize them using Current-Voltage profiling. The surface storage charge value of nanowires shows bias dependence indicating the flexible use of nanowires for cathode and anode material application in supercapacitors. Moreover, the outstanding values of mobilities in these nanowires may serve as an excellent electron transport channel in nanowires-based transistors. Therefore, our present study provides significant pointers for applying MX nanowires in fast-switching electronic devices and supercapacitors.

Molecular-electromechanical system for unamplified detection of trace analytes in biofluids.

Biological research and diagnostic applications normally require analysis of trace analytes in biofluids. Although considerable advancements have been made in developing precise molecular assays, the trade-off between sensitivity and ability to resist non-specific adsorption remains a challenge. Here, we describe the implementation of a testing platform based on a molecular-electromechanical system (MolEMS) immobilized on graphene field-effect transistors. A MolEMS is a self-assembled DNA nanostructure, containing a stiff tetrahedral base and a flexible single-stranded DNA cantilever. Electromechanical actuation of the cantilever modulates sensing events close to the transistor channel, improving signal-transduction efficiency, while the stiff base prevents non-specific adsorption of background molecules present in biofluids. A MolEMS realizes unamplified detection of proteins, ions, small molecules and nucleic acids within minutes and has a limit of detection of several copies in 100 μl of testing solution, offering an assay methodology with wide-ranging applications. In this protocol, we provide step-by-step procedures for MolEMS design and assemblage, sensor manufacture and operation of a MolEMS in several applications. We also describe adaptations to construct a portable detection platform. It takes ~18 h to construct the device and ~4 min to finish the testing from sample addition to result.

Improved noise performance from the next-generation buried-channel p-MOSFET SiSeROs

The Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detector output stage for charge-coupled device (CCD) image sensors. Developed at MIT Lincoln Laboratory, this technology uses a p-MOSFET transistor with a depleted internal gate beneath the transistor channel. The transistor source-drain current is modulated by the transfer of charge into the internal gate. At Stanford, we have developed a readout module based on the drain current of the on-chip transistor to characterize the device. In our earlier work, we characterized a number of first prototype SiSeROs with the MOSFET transistor channels at the surface layer. An equivalent noise charge (ENC) of around 15 electrons root mean square (RMS) was obtained. In this work, we examine the first buried-channel SiSeRO. We have achieved substantially improved noise performance of around 4.5 electrons root mean square (RMS) and a full width half maximum (FWHM) energy resolution of 132 eV at 5.9 keV, for a readout speed of 625 kpixel/s. We also discuss how digital filtering techniques can be used to further improve the SiSeRO noise performance. Additional measurements and device simulations will be essential to further mature the SiSeRO technology. This new device class presents an exciting new technology for the next-generation astronomical X-ray telescopes requiring fast, low-noise, radiation-hard megapixel imagers with moderate spectroscopic resolution.