Channel Of Field Effect Transistor Research Articles

Compute-in-Memory SRAM Cell Using Multistate Spatial Wavefunction Switched (SWS)-Quantum Dot Channel (QDC) FET

This paper presents multistate spatial wavefunction switched (SWS)-quantum dot channel (QDC) field-effect transistor (FET) static random access memory (SRAM)-based Compute-in-Memory (CIM) cell. The SWS-QDC FETs have two or more vertically stacked coupled quantum dot channels, and the spatial location of carriers within these channels is governed by the applied gate voltage. The location of the carriers can be utilized to encode multiple logic levels within a single device. The utilization of SWS-QDC FETs in CIM cell increases the data storage and energy-efficient computation in the memory. CIM reduces the data access time and improves performance for energy-efficient artificial intelligence (AI) edge devices.

PHOTOSENSITIVE FIELD-EFFECT TRANSISTOR BASED ON REDUCED GRAPHENE OXIDE FILM

A photosensitive graphene field-effect transistor was created by depositing a reduced graphene oxide (rGO) film on the surface of the SiO2 layer on a silicon substrate, which serves as both a photosensitive medium and the field-effect transistor gate. The electrical and photoelectric properties of the field-effect transistor based on the rGO film were studied in DC and AC modes. Linear sections of the drain current on the gate voltage dependence and significant dependence of the electronic component of the rGO film conductivity on the irradiation with white light were revealed based on the analysis of the switching characteristics of the obtained field-effect transistor. A photoinduced decrease in the internal resistance and an increase in the capacitance of the conducting channel of the graphene field-effect transistor in the range of 102–105 Hz were revealed. It has been established that the photoresponse time of the obtained field-effect transistor to light pulses of IR, visible, and UV radiation is about 1.5 ms. The obtained results can be used to simplify the technology of manufacturing photodetectors based on graphene.

Channel length dependence of the formation of quantum dots in GaN/AlGaN FETs

Quantum dots can be formed in simple GaN/AlGaN FETs by disordered potential induced by impurities and defects. Here, we investigate the channel length dependence of the formation of quantum dots. We observe a decrease in the number of formed quantum dots with a decrease in the FET channel length. A few quantum dots are formed in the case with a gate length of 0.05 μm and we evaluate the dot parameters and the disordered potential. We also investigate the effects of a thermal cycle and illumination of light and reveal the change of the disordered potential.

A Proposed Nonaligned Double Gate Junction FET Device and its Performance Improvement Using High-k Gate Oxide Material

This paper presents the effect of dielectric materials i.e., hafnium dioxide (HfO2, high-[Formula: see text] and silicon dioxide (SiO2, low-[Formula: see text], as gate-oxide material for the nonaligned double gate junction [Formula: see text]-channel field effect transistor (NADG-NFET). The NADGNFET device proposed in this work lowers the second order effects and improves the transistor linear performance at radio frequency. The device response with gate-oxide material is investigated by using two dielectric materials on the obtained current–voltage characteristics, intrinsic gain, and linearity parameter. The device simulations were done using a 2D-sentaurus TCAD tool. The results were examined in terms of DIBL (drain-induced barrier lowering), SS (subthreshold swing), [Formula: see text] current, [Formula: see text] ratio, the Intrinsic gain ([Formula: see text], and intermodulation distortion power-3 (IMD3) parameter. It has been found that high-[Formula: see text] dielectric decreases the DIBL by 40%, improves the [Formula: see text] ratio by 8 times, and also improves the intrinsic gain by 38% compared to low-[Formula: see text] dielectric material. However, the high frequency parameter result was better with low-[Formula: see text] dielectric material. This gives a trade-off in the device applications. The IMD3 plot shows that using the two gate-oxide material will give the same performance to the radio frequency (RF) signal.

Simple Fabrication Method for Solution-gated One-piece Transistors for Biosensing Applications

In this paper, we report on a novel and simple fabrication method for solution-gated thin-film indium tin oxide (ITO) channel field-effect transistors (FETs). These devices can be fabricated by etching a part of deposited conductive ITO film with about 100 nm thickness to 20 nm thickness as the channel, which exhibits semiconductor characteristics. The current measurement during etching enables the direct observation of the change in current at the channel, that is, the precise optimization of FET characteristics. The devices fabricated show a steep subthreshold slope (~80 mV/decade) and a large I d/I g ratio; thus, they have the potential to be applied in highly sensitive affordable biosensors.

Self-Limiting Growth of Monolayer Tungsten Disulfide Nanoribbons on Tungsten Oxide Nanowires

Transition metal dichalcogenides (TMDCs) are promising two-dimensional (2D) materials for next-generation optoelectronic devices; they can also provide opportunities for further advances in physics. Structuring 2D TMDC sheets as nanoribbons has tremendous potential for electronic state modification. However, a bottom-up synthesis of long TMDC nanoribbons with high monolayer selectivity on a large scale has not yet been reported yet. In this study, we successfully synthesized long WxOy nanowires and grew monolayer WS2 nanoribbons on their surface. The supply of source atoms from a vapor-solid bilayer and chemical reaction at the atomic-scale interface promoted a self-limiting growth process. The developed method exhibited a high monolayer selection yield on a large scale and enabled the growth of long (∼100 μm) WS2 nanoribbons with electronic properties characterized by optical spectroscopy and electrical transport measurements. The produced nanoribbons were isolated from WxOy nanowires by mechanical exfoliation and used as channels for field-effect transistors. The findings of this study can be used in future optoelectronic device applications and advanced physics research.

Investigating Charge Transport in Semiconducting Single‐Walled Carbon Nanotube Networks by Charge Modulation Microscopy

AbstractSolution‐processed networks of semiconducting single‐walled carbon nanotubes (SWCNTs) hold promise as active layers for large‐scale digital circuits, thermoelectric devices, and healthcare applications. Yet, the combined effects of local network properties and (n,m) species composition need to be addressed to improve the performance and reproducibility of state‐of‐the‐art devices. Charge modulation microscopy (CMM) is used to investigate charge transport in field‐effect transistors (FETs) based on monochiral (6,5) SWCNT networks and multichiral networks containing five semiconducting SWCNT species with different band gaps. By mapping the charge‐modulated signal within the FET channel with sub‐micrometer resolution, the spatial distribution of free carriers and its evolution during the switching of the FET are revealed. The CMM maps provide direct evidence that holes and electrons are transported preferentially through the same percolation paths. A moderate positive correlation between the SWCNT density in the monochiral (6,5) network and the charge density in subthreshold regime is demonstrated. In multichiral networks, the charge transport paths are on average less fragmented when involving low band gap species. CMM emerges as a valuable technique to estimate the size of preferential percolation domains associated with the average distance traversed by charge carriers on SWCNTs of the same chirality before tunneling onto other species.

DFT Simulation of a Gold Electrode Vapor-Deposition Growth Process and the Effect of Defects on the Electrode Work Function.

While two-dimensional (2D) semiconductors are explored as field-effect transistor (FET) channel materials for decreasing the short channel effects, electrical contact with 2D semiconductors is a major issue. Many efforts have been made toward this issue. However, the discrepancy in the contact type and the Schottky barrier height from the same contact is present in experiments. This discrepancy supposedly should be associated with the vapor-deposition electrode structures, on which little attention had been focused. Here, the crystal growth of the gold vapor-deposition electrode is simulated by adding gold atoms to the gold substrate one by one in the framework of density functional theory, and for every step, the spontaneously searching adsorption site method is used to find thermodynamically stable adsorption sites and the climbing nudged elastic band method is used to find kinetically stable ones. Simulation shows that the Au(111) face grows according to the ABC sequence packing, and possible defects are interstitial, vacancy, and the partly filled nascent layer (PFNL). These defects have an unequal effect on the electrode work function. The PFNL may be a non-negligible factor responsible for the discrepancy.

Scaling of MoS2 Transistors and Inverters to Sub-10 nm Channel Length with High Performance

Two-dimensional (2D) semiconductors such as monolayer molybdenum disulfide (MoS2) are promising building blocks for ultrascaled field effect transistors (FETs), benefiting from their atomic thickness, dangling-bond-free flat surface, and excellent gate controllability. However, despite great prospects, the fabrication of 2D ultrashort channel FETs with high performance and uniformity remains a challenge. Here, we report a self-encapsulated heterostructure undercut technique for the fabrication of sub-10 nm channel length MoS2 FETs. The fabricated 9 nm channel MoS2 FETs exhibit superior performances compared with sub-15 nm channel length including the competitive on-state current density of 734/433 μA/μm at VDS = 2/1 V, record-low DIBL of ∼50 mV/V, and superior on/off ratio of 3 × 107 and low subthreshold swing of ∼100 mV/dec. Furthermore, the ultrashort channel MoS2 FETs fabricated by this new technique show excellent homogeneity. Thanks to this, we scale the monolayer inverter down to sub-10 nm channel length.

Heteroepitaxial growth of CaGe2 films on high-resistivity Si(111) substrates and its application for germanane synthesizing

Realizing a germanane (GeH) film on insulating substrates is strongly required to understand its intrinsic electric properties in discussing the potential applications for the next-generation field-effect transistor channels. This study investigates the heteroepitaxial growth of CaGe2—the precursor of the GeH—films on a high resistive substrate of FZ-Si(111) using a molecular beam epitaxy with the deposition temperature (Tdepo) as a variable. X-ray diffraction and Raman spectroscopy analyses indicated that a metastable polytype of 2H was dominated in the epitaxial CaGe2 films; the Tdepo must be less than 700 °C to prevent Si diffusion from the substrates. We also synthesize GeH films by immersing some CaGe2 films in HCl acid solutions at a low temperature of −40 °C. Although the obtained grain size of GeH was still as small as several hundred nanometers, we believe that the present study is the first step in obtaining the GeH continuous films directly on insulators necessary for electrical characterizations.

Modulation of Grain Boundary conductance of nanocrystalline SnO[formula omitted] film by electrostatically induced carriers

Grain boundary (GB) conductance of a channel has an immense effect on the device performance of a field effect transistor (FET) fabricated by chemical routes. Here, we report the modulation of intra and inter grain conductance of the channel of SnO2 based FET device by varying electrostatic carrier induction using a polymer gate dielectric. The channel was found highly resistive in the absence of any gate bias, but the channel current (IDS) increased nearly twenty times when VG = 14 V was applied. The threshold gate voltage (VTh) to turn on the channel was measured as low as 2.2 V. Analysis of the experimental results using a suitable theoretical model revealed that the induced carriers (by field effect) play a crucial role to tune the intra grain as well as GB conductance of the FET channel and thus modulating the overall conductance of the FET channel more effectively.

A multi-timescale synaptic weight based on ferroelectric hafnium zirconium oxide

Brain-inspired computing emerged as a forefront technology to harness the growing amount of data generated in an increasingly connected society. The complex dynamics involving short- and long-term memory are key to the undisputed performance of biological neural networks. Here, we report on sub-µm-sized artificial synaptic weights exploiting a combination of a ferroelectric space charge effect and oxidation state modulation in the oxide channel of a ferroelectric field effect transistor. They lead to a quasi-continuous resistance tuning of the synapse by a factor of 60 and a fine-grained weight update of more than 200 resistance values. We leverage a fast, saturating ferroelectric effect and a slow, ionic drift and diffusion process to engineer a multi-timescale artificial synapse. Our device demonstrates an endurance of more than {10}^{10} cycles, a ferroelectric retention of more than 10 years, and various types of volatility behavior on distinct timescales, making it well suited for neuromorphic and cognitive computing.

Oxygen vacancy related hole fast trapping in high mobility cubic-Ge/ZrO2 interface

Ge has the potential to replace Si as the future field-effect transistors channel material due to its superior hole mobility, and cubic zirconia with high dielectric constant and small lattice mismatch can be selected as its oxide layer. At present, the mechanism of charge trapping caused by defects in the Ge oxide layer interface and bulk of such device has not been accurately analyzed. In our work, we have constructed the cubic Ge/ZrO2 interface, and studied the electronic structure and hole trapping characteristics of the interface structure by first-principles hybrid-functional calculations with Marcus theory. According to research oxygen vacancies with the different distances (abbr. d O-int) away from the Ge substrate, we confirm that the oxygen vacancy can act as a fast trap center to capture the hole of the valence band maximum (VBM) from Ge, resulting in the ultrafast or fast transient charge trapping in the high-k gate dielectric. We found that, when a given range of applied electric field, the hole trap is ultrafast with capture time of 10−6–10−5 when d O-int is within the range of 2–7 , and there is a 2–3 order of magnitude increases in capture time as d O-int exceeds 7 with the maximum capture cross section reducing substantially. Here, our work provides a clear and reasonable description of the distance-dependent hole trapping process at the Ge/high-k dielectrics metal-oxide-semiconductor (MOS) devices and provides significant support for solving the reliability problem of microelectronic devices.

Boron Nitride-Graphene (BN-G) Bilayer as a Channel of Graphene Based Field Effect Transistor

According to the effect of the interlayer interaction of the boron nitride sheet on electronic properties, especially the energy band gap of the graphene sheet in the boron nitride-graphene (BN-G) bilayer, we propose a gapless graphene-based field effect transistor (FET). It is comprised of a boron nitride layer on top of graphene in the channel region. In this study, we investigate the transfer characteristic and output characteristic of the proposed device for different values of the interlayer distance of (BN-G) bilayer. Also, we compare the output results with simulated bilayer graphene channel FET. We find that the Ion/Ioff ratio in the proposed device shows a significant promotion compared to graphene bilayer channel FET. Our first-principles calculations show that by decreasing the inter-layer distance of (BN-G) bilayer, the energy gap increase which leads to a dipper Ioff current and an increase of Ion/Ioff ratio up to 104 for an inter-layer distance of 2.7 angstroms. Moreover, it is found that the proposed device output characteristic displays a very good saturation due to improved pinch-off of the channel.

Highly Specific Antibiotic Detection on Water-Stable Black Phosphorus Field-Effect Transistors.

Two-dimensional (2D) black phosphorus (BP) has been reported to have appealing semiconducting properties as the sensing channel in field-effect transistor (FET) sensors. However, the intrinsic instability of BP in water greatly hinders its application, and little is known about its sensing performance and mechanism in aqueous medium. Herein, a water-stable BP FET sensor for antibiotic detection is reported. A novel surface engineering strategy with Ag+ coordination and melamine cyanurate (MC) supramolecular passivation is utilized to enhance the stability and transistor performance of BP. With molecularly imprinted polymers (MIPs) as the detection probe for tetracycline, the BPAg(+)/MC/MIPs sensor shows high sensitivity to tetracycline with a detection limit of 7.94 nM and a quick response within 6 s as well as high selectivity against other antibiotics with similar molecular structures. A new sensing mechanism relying on the conjugation effect of the probe structure is proposed, and new knowledge about alkalinity-enhanced and ionic strength-related response from the electrostatic gating effect is given based on the solution chemistry impact study. This work offers an efficient surface engineering strategy to enable the application of 2D BP for antibiotic detection in aqueous medium and presents a new sensing mechanism in chemical analysis by FET sensors.

Carrier tuning of 2D electron gas in field-effect devices based on Al2O3/ZnO heterostructures.

Two-dimensional electron gas (2DEG) formed at oxide heterointerfaces via atomic layer deposition (ALD) has attracted considerable interest toward fascinating electron-related physics and electronic device applications. The employment of oxide-based 2DEG in a confined channel in field-effect transistors (FETs) holds great promise for advanced electronic devices due to its high mobility, spatial confinement, and tunable conductivity. In this work, a 2DEG FET based on the Al2O3/ZnO heterostructure is fabricated with an optimized channel carrier density and oxide thickness. The carrier transport in the bulk and the oxide interface dominantly governed by percolation conduction, optical phonon scattering, and grain boundary scattering is comparatively studied through oxygen annealing and thickness engineering. A tunable carrier density from 4 × 1011 cm-2 to 2 × 1014 cm-2 is achieved with a maximum Hall mobility of ∼62 cm2 V-1 s-1. The electron distribution associated with the annealing process of the ZnO underlayer and the interface reaction during Al2O3 deposition are found to have an impact on the electrical characteristics of the devices. The fabricated Al2O3/ZnO-based 2DEG FET exhibits an on/off ratio over 108, a subthreshold swing of 224 mV dec-1, and a field-effect mobility of 5.7 cm2 V-1 s-1 which can be promising for advanced oxide thin film-containing device and system applications.

One dimensional MOSFETs for sub-5 nm high-performance applications: a case of Sb2Se3 nanowires.

Low-dimensional materials have been proposed as alternatives to silicon-based field-effect transistor (FET) channel materials in order to overcome the scaling limitation. In the present research, gate-all-around (GAA) Sb2Se3 nanowire FETs were simulated using the ab initio quantum transport method. The gate-length (Lg, Lg = 5 nm) GAA Sb2Se3 FETs with an underlap (UL, UL = 2, 3 nm) could satisfy the on-state current (Ion) and delay time (τ) of the 2028 requirements for high performance (HP) applications of the International Technology Roadmap for Semiconductors (ITRS) 2013. It is interesting that the Lg = 3 nm GAA Sb2Se3 FETs with a UL = 3 nm can meet the Ion, power dissipation (PDP), and τ of the 2028 requirements of ITRS 2013 for HP applications. Therefore, GAA Sb2Se3 FETs can be a potential candidate scaling Moore's law downward to 3 nm.

ReS2 Nanosheet-Based Channels for Two-Dimensional Field Effect Transistors and Phototransistors with High Photoresponsivity

ReS₂ Nanosheet-Based Channels for Two-Dimensional Field Effect Transistors and Phototransistors with High Photoresponsivity

Low-temperature solution-processed high-capacitance AlOx dielectrics for low-voltage carbon-based transistors

Low-temperature processing of high-capacitance metal oxide-based dielectrics by solution-based methods and their application in developing low-voltage carbon-based transistors may enable next-generation low-cost, power-efficient, flexible and transparent electronics. In this work, a high-capacitance AlO x film was developed at a relatively low annealing temperature of ⁓200 °C from its spin-coated precursor solution. Its application in both low-voltage n- as well as p -channel field-effect transistors (FETs) was demonstrated, gaining feedback on microstructure and dielectric properties by using X-ray diffraction, X-ray photoelectron spectroscopy, atomic force microscopy, as well as impedance and current-voltage measurements. The operating voltage of both n -channel FETs based on a semiconducting polymer as well as p -channel FETs with polymer-sorted semiconducting (6,5) single-walled carbon nanotube (s-SWCNT) networks was found to be within 1.5 V range. This work demonstrates the viability of low-temperature AlO x dielectrics in low-voltage carbon-based electronics towards low-power distributed, portable and wearable applications. • Solution-processed AlO x is developed at a low temperature of 200 °C. • A 78 nm thick AlO x film has an areal capacitance of 105 nF cm −2 at 10 kHz. • Field-effect transistors are realized using both n -and p -type carbon-based semiconductors and AlO x as the dielectric. • The operating voltage of both types of transistors is within 1.5 V. • Our devices could be useful in low-power, portable, and wearable electronics.

Gate Leakage and Reliability of GaN -Channel FET With SiNₓ/GaON Staggered Gate Stack

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